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Hdlmake
Commit acbb3699 authored by Benny Simonsen's avatar Benny Simonsen
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Include library in TOP_MODULE

parent 645fa346
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Showing with 25 additions and 4 deletions
hdlmake/tools/isim.py
View file @ acbb3699
......@@ -61,6 +61,7 @@ class ToolISim(MakefileSim):
def __init__(self):
super(ToolISim, self).__init__()
self.default_library = "work"
def _makefile_sim_top(self):
"""Print the top section of the Makefile for Xilinx ISim"""
......@@ -83,7 +84,14 @@ class ToolISim(MakefileSim):
# Ensure the path is absolute and normalized
return os.path.abspath(xilinx_ini_path)
self.writeln("## variables #############################")
self.writeln("TOP_MODULE := {}".format(self.manifest_dict.get("sim_top", '')))
top_module = self.manifest_dict.get("sim_top", None)
if top_module:
library = self.manifest_dict.get("library", self.default_library)
if top_module.startswith('.'):
top_module = library + top_module
elif '.' not in top_module:
top_module = library + '.' + top_module
self.writeln("TOP_MODULE := {}".format(top_module))
self.writeln("FUSE_OUTPUT ?= isim_proj")
self.writeln()
self.writeln("XILINX_INI_PATH := {}".format(__get_xilinxsim_ini_dir()))
......@@ -161,7 +169,7 @@ $(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
self.writeln("\t\t" + shell.copy_command() + " $< .")
self.writeln("""\
fuse:
\t\tfuse work.$(TOP_MODULE) -intstyle ise -incremental -o $(FUSE_OUTPUT)
\t\tfuse $(TOP_MODULE) -intstyle ise -incremental -o $(FUSE_OUTPUT)
""")
self._makefile_sim_libraries(libs)
......
hdlmake/tools/makefilesim.py
View file @ acbb3699
......@@ -24,6 +24,7 @@ class MakefileSim(ToolMakefile):
def __init__(self):
super(MakefileSim, self).__init__()
self.default_library = "work"
def write_makefile(self, top_manifest, fileset, filename=None):
"""Execute the simulation action"""
......@@ -43,7 +44,12 @@ class MakefileSim(ToolMakefile):
def _makefile_sim_top(self):
"""Generic method to write the simulation Makefile top section"""
self.writeln("TOP_MODULE := {}".format(self.manifest_dict["sim_top"]))
top_module = self.manifest_dict.get("sim_top")
if top_module:
if self.manifest_dict.get("library", '') not in ["", self.default_library]:
if top_module.startswith('.'):
top_module = self.manifest_dict["library"] + top_module
self.writeln("TOP_MODULE := {}".format(top_module))
self.writeln()
def _makefile_sim_options(self):
......
hdlmake/tools/makefilesyn.py
View file @ acbb3699
......@@ -79,6 +79,13 @@ SYN_DEVICE := {syn_device}
SYN_PACKAGE := {syn_package}
SYN_GRADE := {syn_grade}
"""
top_module = self.manifest_dict.get("syn_top", None)
if top_module:
if self.manifest_dict.get("library", '') not in ["", self.default_library]:
if top_module.startswith('.'):
top_module = self.manifest_dict["library"] + top_module
self.writeln(top_parameter.format(
tcl_interpreter=self.get_tool_bin(),
project_name=os.path.splitext(
......@@ -89,7 +96,7 @@ SYN_GRADE := {syn_grade}
syn_package=self.manifest_dict["syn_package"],
syn_grade=self.manifest_dict["syn_grade"],
tool_path=self.manifest_dict["syn_path"],
top_module=self.manifest_dict["syn_top"]))
top_module=top_module))
def _makefile_syn_prj_tcl_cmd(self):
"""Create the Makefile variables for the TCL project commands."""
......
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