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Hdlmake
Commits
b3b44979
Commit
b3b44979
authored
Oct 29, 2019
by
Tristan Gingold
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active_hdl.py: simplify code, avoid duplicates. Adjust test.
parent
775fa73d
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4 changed files
with
27 additions
and
22 deletions
+27
-22
active_hdl.py
hdlmake/tools/active_hdl.py
+5
-17
Makefile.ref
testsuite/006ahdl/Makefile.ref
+9
-3
Manifest.py
testsuite/006ahdl/Manifest.py
+2
-2
gatesv_tb.sv
testsuite/files/gatesv_tb.sv
+11
-0
No files found.
hdlmake/tools/active_hdl.py
View file @
b3b44979
...
...
@@ -62,23 +62,11 @@ class ToolActiveHDL(MakefileSim):
self
.
writeln
()
self
.
writeln
(
"
\t\t
echo # Compiling HDL source files >> run.command"
)
for
vl_file
in
fileset
.
filter
(
VerilogFile
):
self
.
writeln
(
"
\t\t
echo alog
\"
"
+
vl_file
.
rel_path
(
)
+
"
\"
>> run.command"
)
for
sv_file
in
fileset
.
filter
(
SVFile
):
self
.
writeln
(
"
\t\t
echo alog
\"
"
+
sv_file
.
rel_path
(
)
+
"
\"
>> run.command"
)
for
vl_file
in
fileset
.
filter
(
VerilogFile
)
.
sort
():
self
.
writeln
(
"
\t\t
echo alog
\"
{}
\"
>> run.command"
.
format
(
vl_file
.
rel_path
()))
for
vhdl_file
in
fileset
.
filter
(
VHDLFile
):
self
.
writeln
(
"
\t\t
echo acom
\"
"
+
vhdl_file
.
rel_path
(
)
+
"
\"
>> run.command"
)
self
.
writeln
(
"
\t\t
echo acom
\"
{}
\"
>> run.command"
.
format
(
vhdl_file
.
rel_path
()))
self
.
writeln
()
self
.
writeln
(
"
\t\t
vsimsa -do run.command"
)
testsuite/006ahdl/Makefile.ref
View file @
b3b44979
...
...
@@ -3,13 +3,17 @@
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE
:=
gate
TOP_MODULE
:=
gate
sv_tb
#target for performing local simulation
local
:
sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC
:=
VERILOG_OBJ
:=
VERILOG_SRC
:=
../files/gate2.v
\
../files/gatesv_tb.sv
\
VERILOG_OBJ
:=
work/gate2/.gate2_v
\
work/gatesv_tb/.gatesv_tb_sv
\
VHDL_SRC
:=
../files/gate.vhdl
\
VHDL_OBJ
:=
work/gate/.gate_vhdl
\
...
...
@@ -22,6 +26,8 @@ simulation:
echo
set
worklib
work
>>
run.command
echo
# Compiling HDL source files >> run.command
echo
alog
"../files/gate2.v"
>>
run.command
echo
alog
"../files/gatesv_tb.sv"
>>
run.command
echo
acom
"../files/gate.vhdl"
>>
run.command
vsimsa
-do
run.command
...
...
testsuite/006ahdl/Manifest.py
View file @
b3b44979
...
...
@@ -2,6 +2,6 @@ action = "simulation"
sim_tool
=
"active_hdl"
top_module
=
"gate"
top_module
=
"gate
sv_tb
"
files
=
[
"../files/gate.vhdl"
]
files
=
[
"../files/gate.vhdl"
,
"../files/gate2.v"
,
"../files/gatesv_tb.sv"
]
testsuite/files/gatesv_tb.sv
0 → 100644
View file @
b3b44979
module
gatesv_tb
;
reg
i
,
o
;
wire
o2
;
gate
dut
(
.
i
(
i
)
,
.
o
(
o
))
;
gate2
dut
(
.
i
(
i
)
,
.
o
(
o2
))
;
initial
begin
i
<=
0
;
#
1
;
$
stop
;
end
endmodule
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