change sim to be default target in a makefile

d45359d8 · Pawel Szostek · f4c747ff · d45359d8
Commit d45359d8 authored Aug 02, 2013 by Pawel Szostek
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Showing with 4 additions and 4 deletions

makefile_writer.py hdlmake/makefile_writer.py +4 -4

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--- a/hdlmake/makefile_writer.py
+++ b/hdlmake/makefile_writer.py
@@ -381,16 +381,16 @@ VSIM_FLAGS :=
 VLOG_FLAGS := -quiet -modelsimini modelsim.ini """ + self.__get_rid_of_incdirs(top_module.vlog_opt) + """
 """
        make_preambule_p2 = Template("""## rules #################################
+sim: check_tool sim_pre_cmd modelsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ)
+$$(VERILOG_OBJ): $$(VHDL_OBJ)
+$$(VHDL_OBJ): $$(LIB_IND) modelsim.ini
+
 sim_pre_cmd:
 \t\t${sim_pre_cmd}

 sim_post_cmd: sim
 \t\t${sim_post_cmd}

-sim: check_tool sim_pre_cmd modelsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ)
-$$(VERILOG_OBJ): $$(VHDL_OBJ)
-$$(VHDL_OBJ): $$(LIB_IND) modelsim.ini
-
 check_tool:
 \t\t${check_tool}
 modelsim.ini: $$(MODELSIM_INI_PATH)/modelsim.ini