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Commit eac0c5a3 authored by Tristan Gingold's avatar Tristan Gingold
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testsuite: adjust 076extra_modules test

parent b9baf697
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Showing with 14 additions and 7 deletions
testsuite/076extra_modules/Makefile.ref
View file @ eac0c5a3
......@@ -3,7 +3,7 @@
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate_tb
TOP_MODULE := gate
MODELSIM_INI_PATH := ../linux_fakebin/..
......@@ -18,8 +18,10 @@ VERILOG_SRC := ../files/gate_tb.v \
VERILOG_OBJ := work/hdlmake/gate_tb_v \
VHDL_SRC :=
VHDL_OBJ :=
VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/hdlmake/work-stamp
......@@ -34,7 +36,12 @@ modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
work/hdlmake/work-stamp:
(vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
work/hdlmake/gate_tb_v: ../files/gate_tb.v
work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
work/hdlmake/gate_tb_v: ../files/gate_tb.v \
work/hdlmake/gate_vhdl
vlog -work work $(VLOG_FLAGS) $(INCLUDE_DIRS) $<
@touch $@
......
testsuite/076extra_modules/Manifest.py
View file @ eac0c5a3
......@@ -2,7 +2,7 @@ action = "simulation"
sim_tool="modelsim"
top_module = "gate_tb"
top_module = "gate"
files = [ "../files/gate_tb.v" ]
extra_modules = [ "../files/gate.vhdl" ]
files = [ "../files/gate_tb.v", "../files/gate.vhdl" ]
extra_modules = [ "gate_tb"]
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