Commit eb10004a authored by Tristan Gingold's avatar Tristan Gingold

fix incorrect check.

parent 8ba02666
......@@ -13,9 +13,9 @@ from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
def _check_simulation_manifest(manifest_dict):
"""Check if the simulation keys are provided by the top manifest"""
if not manifest_dict["sim_top"]:
if manifest_dict.get("sim_top") is None:
raise Exception("sim_top variable must be set in the top manifest.")
if not manifest_dict["sim_tool"]:
if manifest_dict.get("sim_tool") is None:
raise Exception("sim_tool variable must be set in the top manifest.")
......
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