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Hdlmake
Commits
f7cfce26
Commit
f7cfce26
authored
Oct 30, 2019
by
Tristan Gingold
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Plain Diff
dep_file.py: split add_relation to add_depend/add_require
parent
fad48533
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4 changed files
with
23 additions
and
16 deletions
+23
-16
dep_file.py
hdlmake/sourcefiles/dep_file.py
+10
-3
vhdl_parser.py
hdlmake/sourcefiles/vhdl_parser.py
+7
-7
vlog_parser.py
hdlmake/sourcefiles/vlog_parser.py
+5
-5
xci_parser.py
hdlmake/sourcefiles/xci_parser.py
+1
-1
No files found.
hdlmake/sourcefiles/dep_file.py
View file @
f7cfce26
...
...
@@ -140,7 +140,8 @@ class File(object):
class
DepFile
(
File
):
"""Class that serves as base to all those HDL files that can be
parsed and solved (Verilog, SystemVerilog, VHDL)"""
parsed and solved (Verilog, SystemVerilog, VHDL). Inherit from
File but also provides dependencies"""
def
__init__
(
self
,
path
,
module
):
assert
isinstance
(
path
,
six
.
string_types
)
...
...
@@ -150,8 +151,14 @@ class DepFile(File):
self
.
dep_level
=
None
self
.
is_parsed
=
False
def
add_relation
(
self
,
rel
):
"""Add a new relation to the set provided by the file"""
def
add_require
(
self
,
rel
):
"""Add dependency :param rel:"""
assert
rel
.
direction
==
DepRelation
.
USE
self
.
rels
.
add
(
rel
)
def
add_provide
(
self
,
rel
):
"""Add provide :param rel:"""
assert
rel
.
direction
==
DepRelation
.
PROVIDE
self
.
rels
.
add
(
rel
)
def
satisfies
(
self
,
rel_b
):
...
...
hdlmake/sourcefiles/vhdl_parser.py
View file @
f7cfce26
...
...
@@ -69,14 +69,14 @@ class VHDLParser(DepParser):
if
text
.
group
(
1
)
.
lower
()
==
"work"
:
logging
.
debug
(
"use package
%
s.
%
s"
,
dep_file
.
library
,
text
.
group
(
2
))
dep_file
.
add_re
lation
(
dep_file
.
add_re
quire
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
text
.
group
(
2
)),
DepRelation
.
USE
,
DepRelation
.
PACKAGE
))
else
:
logging
.
debug
(
"use package
%
s.
%
s"
,
text
.
group
(
1
),
text
.
group
(
2
))
dep_file
.
add_re
lation
(
dep_file
.
add_re
quire
(
DepRelation
(
"
%
s.
%
s"
%
(
text
.
group
(
1
),
text
.
group
(
2
)),
DepRelation
.
USE
,
DepRelation
.
PACKAGE
))
...
...
@@ -95,7 +95,7 @@ class VHDLParser(DepParser):
to the file"""
logging
.
debug
(
"found entity
%
s.
%
s"
,
dep_file
.
library
,
text
.
group
(
1
))
dep_file
.
add_
relation
(
dep_file
.
add_
provide
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
text
.
group
(
1
)),
DepRelation
.
PROVIDE
,
DepRelation
.
ENTITY
))
...
...
@@ -116,11 +116,11 @@ class VHDLParser(DepParser):
relations to the file"""
logging
.
debug
(
"found architecture
%
s of entity
%
s.
%
s"
,
text
.
group
(
1
),
dep_file
.
library
,
text
.
group
(
2
))
dep_file
.
add_
relation
(
dep_file
.
add_
provide
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
text
.
group
(
2
)),
DepRelation
.
PROVIDE
,
DepRelation
.
ARCHITECTURE
))
dep_file
.
add_re
lation
(
dep_file
.
add_re
quire
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
text
.
group
(
2
)),
DepRelation
.
USE
,
DepRelation
.
ENTITY
))
...
...
@@ -141,7 +141,7 @@ class VHDLParser(DepParser):
relations to the file"""
logging
.
debug
(
"found package
%
s.
%
s"
,
dep_file
.
library
,
text
.
group
(
1
))
dep_file
.
add_
relation
(
dep_file
.
add_
provide
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
text
.
group
(
1
)),
DepRelation
.
PROVIDE
,
DepRelation
.
PACKAGE
))
...
...
@@ -252,7 +252,7 @@ class VHDLParser(DepParser):
lib
=
text
.
group
(
"LIB"
)
if
not
lib
or
lib
==
"work"
:
lib
=
dep_file
.
library
dep_file
.
add_re
lation
(
DepRelation
(
dep_file
.
add_re
quire
(
DepRelation
(
"
%
s.
%
s"
%
(
lib
,
text
.
group
(
"ENTITY"
)),
DepRelation
.
USE
,
DepRelation
.
ENTITY
))
return
"<hdlmake instance
%
s|
%
s|
%
s>"
%
(
text
.
group
(
"LABEL"
),
...
...
hdlmake/sourcefiles/vlog_parser.py
View file @
f7cfce26
...
...
@@ -528,7 +528,7 @@ class VerilogParser(DepParser):
relations to the file"""
logging
.
debug
(
"file
%
s imports/uses
%
s.
%
s package"
,
dep_file
.
path
,
dep_file
.
library
,
text
.
group
(
1
))
dep_file
.
add_re
lation
(
dep_file
.
add_re
quire
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
text
.
group
(
1
)),
DepRelation
.
USE
,
DepRelation
.
PACKAGE
))
import_pattern
.
subn
(
do_imports
,
buf
)
...
...
@@ -544,7 +544,7 @@ class VerilogParser(DepParser):
relations to the file"""
logging
.
debug
(
"found pacakge
%
s.
%
s"
,
dep_file
.
library
,
text
.
group
(
1
))
dep_file
.
add_
relation
(
dep_file
.
add_
provide
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
text
.
group
(
1
)),
DepRelation
.
PROVIDE
,
DepRelation
.
PACKAGE
))
m_inside_package
.
subn
(
do_package
,
buf
)
...
...
@@ -568,7 +568,7 @@ class VerilogParser(DepParser):
PROVIDE relations to the file"""
logging
.
debug
(
"found module
%
s.
%
s"
,
dep_file
.
library
,
text
.
group
(
1
))
dep_file
.
add_
relation
(
dep_file
.
add_
provide
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
text
.
group
(
1
)),
DepRelation
.
PROVIDE
,
DepRelation
.
MODULE
))
...
...
@@ -582,7 +582,7 @@ class VerilogParser(DepParser):
return
logging
.
debug
(
"-> instantiates
%
s.
%
s as
%
s"
,
dep_file
.
library
,
text
.
group
(
1
),
text
.
group
(
2
))
dep_file
.
add_re
lation
(
dep_file
.
add_re
quire
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
text
.
group
(
1
)),
DepRelation
.
USE
,
DepRelation
.
MODULE
))
for
stmt
in
[
x
for
x
in
m_stmt
.
split
(
text
.
group
(
2
))
if
x
and
x
[
-
1
]
==
")"
]:
...
...
@@ -590,7 +590,7 @@ class VerilogParser(DepParser):
if
match
:
do_inst
(
match
)
m_inside_module
.
subn
(
do_module
,
buf
)
dep_file
.
add_
relation
(
dep_file
.
add_
provide
(
DepRelation
(
dep_file
.
path
,
DepRelation
.
PROVIDE
,
...
...
hdlmake/sourcefiles/xci_parser.py
View file @
f7cfce26
...
...
@@ -51,7 +51,7 @@ class XCIParser(DepParser):
if
not
value
is
None
:
modulename
=
value
.
text
logging
.
debug
(
"found module
%
s.
%
s"
,
dep_file
.
library
,
modulename
)
dep_file
.
add_
relation
(
dep_file
.
add_
provide
(
DepRelation
(
"
%
s.
%
s"
%
(
dep_file
.
library
,
modulename
),
DepRelation
.
PROVIDE
,
DepRelation
.
MODULE
))
...
...
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