Merge branch 'iverilog-vhdl-counter-test' into develop

fa0d59ac · Garcia-Lasheras · 6d4d3661 · c3aecb01 · fa0d59ac · fa0d59ac
Commit fa0d59ac authored Feb 07, 2015 by Garcia-Lasheras
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iverilog.py hdlmake/tools/iverilog/iverilog.py +2 -1

Manifest.py tests/counter/sim/iverilog/vhdl/Manifest.py +12 -0

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--- a/hdlmake/tools/iverilog/iverilog.py
+++ b/hdlmake/tools/iverilog/iverilog.py
@@ -70,7 +70,8 @@ class ToolControls(MakefileWriter):

        makefile_tmplt_1 = string.Template("""TOP_MODULE := ${top_module}
 IVERILOG_CRAP := \
-run.command
+run.command \
+ivl_vhdl_work

 #target for performing local simulation
 local: sim_pre_cmd simulation sim_post_cmd

--- a/tests/counter/sim/iverilog/vhdl/Manifest.py
+++ b/tests/counter/sim/iverilog/vhdl/Manifest.py
+action = "simulation"
+sim_tool = "iverilog"
+top_module = "counter_tb"
+
+sim_pre_cmd ="echo IMPORTANT, IVerilog always needs a Verilog testbench, no matter if the DUT is written in VHDL!"
+sim_post_cmd = "vvp counter_tb.vvp; gtkwave counter_tb.vcd"
+
+files = [
+    "../../../modules/counter/vhdl/counter.vhd",
+    "../../../testbench/counter_tb/verilog/counter_tb.v",
+]
+