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Hdlmake
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033590e18cf27a8513928846321fb25e6ababc40
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hdl-make
tests
counter
top
proasic3_sk
verilog
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Simple 8-bit counter test for syn/sim, VHDL/Verilog
· cc56877a
garcialasheras
authored
Sep 16, 2014
cc56877a
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Manifest.py
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proasic3_top.v
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