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Hydra - a radiation-tolerant SoC
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Hydra - a radiation-tolerant SoC
Commits
39fb2038
Commit
39fb2038
authored
May 20, 2022
by
Tristan Gingold
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hydra_core: add triple_cpu generic
parent
da84f903
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49 additions
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9 deletions
+49
-9
hydra_core.vhd
hdl/rtl/hydra_core.vhd
+49
-9
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hdl/rtl/hydra_core.vhd
View file @
39fb2038
...
@@ -37,6 +37,7 @@ entity hydra_core is
...
@@ -37,6 +37,7 @@ entity hydra_core is
generic
(
generic
(
g_IRAM_LOG_SIZE
:
natural
:
=
12
;
-- In bytes
g_IRAM_LOG_SIZE
:
natural
:
=
12
;
-- In bytes
g_DRAM_LOG_SIZE
:
natural
:
=
12
;
g_DRAM_LOG_SIZE
:
natural
:
=
12
;
g_TRIPLE_CORE
:
boolean
:
=
True
;
g_SIM_SEU_PERIOD
:
natural
:
=
0
);
g_SIM_SEU_PERIOD
:
natural
:
=
0
);
port
(
port
(
clk_sys_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
...
@@ -166,12 +167,44 @@ begin
...
@@ -166,12 +167,44 @@ begin
dwb_o
<=
dwb_out
;
dwb_o
<=
dwb_out
;
cpu_rst2
<=
"111"
when
rst_n_i
=
'0'
or
cpu_rst_n_i
=
'0'
else
cpu_rst
;
cpu_rst2
<=
"111"
when
rst_n_i
=
'0'
or
cpu_rst_n_i
=
'0'
else
cpu_rst
;
inst_cpus
:
entity
work
.
hydra_triple_cpu
gen_triple_cpu
:
if
g_TRIPLE_CORE
generate
inst_cpus
:
entity
work
.
hydra_triple_cpu
port
map
(
clk_i
=>
clk_sys_i
,
clk_cpu_i
=>
clk_cpu_i
,
cpu_rst_i
=>
cpu_rst2
,
im_addr_o
=>
im_addr
,
im_rd_o
=>
im_rd
,
im_data_i
=>
im_data
,
im_valid_i
=>
im_valid
,
dm_addr_o
=>
dm_addr
,
dm_data_s_o
=>
dm_data_s
,
dm_data_l_i
=>
dm_data_l
,
dm_data_select_o
=>
dm_data_select
,
dm_store_o
=>
dm_store
,
dm_load_o
=>
dm_load
,
dm_load_done_i
=>
dm_load_done
,
dm_store_done_i
=>
dm_store_done
,
cpu_sync_o
=>
cpu_sync
,
dm_force_divergence_i
=>
dm_force_divergence
,
err_cpu_im_o
=>
err_cpu_im
,
err_cpu_dm_o
=>
err_cpu_dm
);
end
generate
;
gen_one_cpu
:
if
not
g_TRIPLE_CORE
generate
inst_cpu
:
urv_cpu
generic
map
(
g_timer_frequency
=>
0
,
g_with_hw_debug
=>
0
,
g_with_hw_mul
=>
0
,
g_with_hw_div
=>
0
)
port
map
(
port
map
(
clk_i
=>
clk_sys_i
,
clk_i
=>
clk_sys_i
,
clk_cpu_i
=>
clk_cpu_i
,
rst_i
=>
cpu_rst2
(
1
)
,
cpu_rst_i
=>
cpu_rst2
,
irq_i
=>
'0'
,
im_addr_o
=>
im_addr
,
im_addr_o
=>
im_addr
,
im_rd_o
=>
im_rd
,
im_rd_o
=>
im_rd
,
im_data_i
=>
im_data
,
im_data_i
=>
im_data
,
...
@@ -184,11 +217,18 @@ begin
...
@@ -184,11 +217,18 @@ begin
dm_load_o
=>
dm_load
,
dm_load_o
=>
dm_load
,
dm_load_done_i
=>
dm_load_done
,
dm_load_done_i
=>
dm_load_done
,
dm_store_done_i
=>
dm_store_done
,
dm_store_done_i
=>
dm_store_done
,
dbg_force_i
=>
'0'
,
cpu_sync_o
=>
cpu_sync
,
dbg_enabled_o
=>
open
,
dm_force_divergence_i
=>
dm_force_divergence
,
dbg_insn_i
=>
x"0000_0000"
,
err_cpu_im_o
=>
err_cpu_im
,
dbg_insn_set_i
=>
'0'
,
err_cpu_dm_o
=>
err_cpu_dm
);
dbg_insn_ready_o
=>
open
,
dbg_mbx_data_i
=>
x"0000_0000"
,
dbg_mbx_write_i
=>
'0'
,
dbg_mbx_data_o
=>
open
);
cpu_sync
<=
"111"
;
err_cpu_im
<=
'0'
;
err_cpu_dm
<=
'0'
;
end
generate
;
-- Add registers on uRV data bus
-- Add registers on uRV data bus
process
(
clk_sys_i
)
process
(
clk_sys_i
)
...
...
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