hdl:move the files to a hdl folder

69026a32 · Cesar Prados · 0281f760 · 69026a32 · 69026a32 · 69026a32
Commit 69026a32 authored Oct 04, 2013 by Cesar Prados
20 changed files
--- a/hdl/Manifest.py
+++ b/hdl/Manifest.py
+files = [ "xVME64xCore_Top.vhd",
+          "xvme64x_pack.vhd",
+          "VME_Access_Decode.vhd",
+          "VME_Am_Match.vhd",
+          "VME_bus.vhd",
+          "VME_CR_CSR_Space.vhd",
+          "VME_CR_pack.vhd",
+          "VME_CSR_pack.vhd",
+          "VME_CRAM.vhd",
+          "VME_Funct_Match.vhd",
+          "VME_Init.vhd",
+          "VME_IRQ_Controller.vhd",
+          "VME_SharedComps.vhd",
+          "VME_swapper.vhd",
+          "VME_Wb_master.vhd"]
--- a/hdl/VME64xCore_Top.vhd
+++ b/hdl/VME64xCore_Top.vhd
--- a/hdl/VME_Access_Decode.vhd
+++ b/hdl/VME_Access_Decode.vhd
--- a/hdl/VME_Am_Match.vhd
+++ b/hdl/VME_Am_Match.vhd
+--_______________________________________________________________________________________
+--                             VME TO WB INTERFACE
+--
+--                                CERN,BE/CO-HT 
+--______________________________________________________________________________________
+-- File:                       VME_Am_Match.vhd
+--______________________________________________________________________________________
+-- Description: this component checks if the AM match. 
+-- If it is the correspondent AmMatch's bit is asserted. This condition is necessary but 
+-- not sufficient to select the function and access the board.
+-- If DFS = '0' the function supports only access modes with the same address width; 
+-- 1 function --> only 1 address width;
+-- with address width I mean A16, A24, A32 or A64.
+-- is sufficient check the AMCAP; AmMatch(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am))).
+-- If DFS = '1' the function supports access modes with different address widths so AmMatch(i)
+-- is asserted only if ADER[7:2] = AM and s_FUNC_AMCAP(i)(to_integer(unsigned(Am)))='1'.
+-- If ADER(i)'s XAM bit is asserted than AmMatch(i) is asserted only if AM = 0x20 and if the 
+-- XAMCAP(i)(to_integer(unsigned(XAm))) = '1' and if DFS = '1' also ADER[9:2] must be equal 
+-- to XAM[7:0] lines.
+--______________________________________________________________________________________
+-- Authors:                                   
+--               Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)                             
+--               Davide Pedretti       (Davide.Pedretti@cern.ch)  
+-- Date         11/2012                                                                           
+-- Version      v0.03 
+--______________________________________________________________________________________
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                
+--                              ------------------------------------    
+-- Copyright (c) 2009 - 2011 CERN                           
+-- This source file is free software; you can redistribute it and/or modify it 
+-- under the terms of the GNU Lesser General Public License as published by the 
+-- Free Software Foundation; either version 2.1 of the License, or (at your option) 
+-- any later version. This source is distributed in the hope that it will be useful, 
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for 
+-- more details. You should have received a copy of the GNU Lesser General Public 
+-- License along with this source; if not, download it from 
+-- http://www.gnu.org/licenses/lgpl-2.1.html                     
+----------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use work.xvme64x_pack.all;
+
+--===========================================================================
+-- Entity declaration
+--===========================================================================
+
+entity VME_Am_Match is
+   Port ( clk_i          : in  std_logic;
+          reset          : in  std_logic;
+          mainFSMreset   : in  std_logic;
+          Ader0          : in  std_logic_vector (31 downto 0);
+          Ader1          : in  std_logic_vector (31 downto 0);
+          Ader2          : in  std_logic_vector (31 downto 0);
+          Ader3          : in  std_logic_vector (31 downto 0);
+          Ader4          : in  std_logic_vector (31 downto 0);
+          Ader5          : in  std_logic_vector (31 downto 0);
+          Ader6          : in  std_logic_vector (31 downto 0);			  
+          Ader7          : in  std_logic_vector (31 downto 0);	
+          AmCap0         : in  std_logic_vector (63 downto 0);
+          AmCap1         : in  std_logic_vector (63 downto 0);
+          AmCap2         : in  std_logic_vector (63 downto 0);
+          AmCap3         : in  std_logic_vector (63 downto 0);
+          AmCap4         : in  std_logic_vector (63 downto 0);
+          AmCap5         : in  std_logic_vector (63 downto 0);
+          AmCap6         : in  std_logic_vector (63 downto 0);
+          AmCap7         : in  std_logic_vector (63 downto 0);
+          XAmCap0        : in  std_logic_vector (255 downto 0);
+          XAmCap1        : in  std_logic_vector (255 downto 0);
+          XAmCap2        : in  std_logic_vector (255 downto 0);
+          XAmCap3        : in  std_logic_vector (255 downto 0);
+          XAmCap4        : in  std_logic_vector (255 downto 0);
+          XAmCap5        : in  std_logic_vector (255 downto 0);
+          XAmCap6        : in  std_logic_vector (255 downto 0);
+          XAmCap7        : in  std_logic_vector (255 downto 0);
+          Am             : in  std_logic_vector (5 downto 0);
+          XAm            : in  std_logic_vector (7 downto 0);  
+          DFS_i          : in  std_logic_vector (7 downto 0);
+          decode         : in  std_logic;
+          AmMatch        : out std_logic_vector (7 downto 0));
+end VME_Am_Match;
+--===========================================================================
+-- Architecture declaration
+--===========================================================================
+architecture Behavioral of VME_Am_Match is
+   signal s_FUNC_ADER    : t_FUNC_32b_array;
+   signal s_FUNC_AMCAP   : t_FUNC_64b_array;
+   signal s_FUNC_XAMCAP  : t_FUNC_256b_array;
+   signal s_amcap_match  : std_logic_vector(7 downto 0);
+   signal s_xamcap_match : std_logic_vector(7 downto 0);
+--===========================================================================
+-- Architecture begin
+--===========================================================================
+begin
+
+   s_FUNC_ADER(0)   <= unsigned(Ader0);
+   s_FUNC_ADER(1)   <= unsigned(Ader1);
+   s_FUNC_ADER(2)   <= unsigned(Ader2);
+   s_FUNC_ADER(3)   <= unsigned(Ader3);
+   s_FUNC_ADER(4)   <= unsigned(Ader4);
+   s_FUNC_ADER(5)   <= unsigned(Ader5);
+   s_FUNC_ADER(6)   <= unsigned(Ader6);
+   s_FUNC_ADER(7)   <= unsigned(Ader7);
+
+   s_FUNC_AMCAP(0)  <= unsigned(AmCap0);
+   s_FUNC_AMCAP(1)  <= unsigned(AmCap1);
+   s_FUNC_AMCAP(2)  <= unsigned(AmCap2);
+   s_FUNC_AMCAP(3)  <= unsigned(AmCap3);
+   s_FUNC_AMCAP(4)  <= unsigned(AmCap4);
+   s_FUNC_AMCAP(5)  <= unsigned(AmCap5);
+   s_FUNC_AMCAP(6)  <= unsigned(AmCap6);
+   s_FUNC_AMCAP(7)  <= unsigned(AmCap7);
+
+   s_FUNC_XAMCAP(0) <= unsigned(XAmCap0);
+   s_FUNC_XAMCAP(1) <= unsigned(XAmCap1);
+   s_FUNC_XAMCAP(2) <= unsigned(XAmCap2);
+   s_FUNC_XAMCAP(3) <= unsigned(XAmCap3);
+   s_FUNC_XAMCAP(4) <= unsigned(XAmCap4);
+   s_FUNC_XAMCAP(5) <= unsigned(XAmCap5);
+   s_FUNC_XAMCAP(6) <= unsigned(XAmCap6);
+   s_FUNC_XAMCAP(7) <= unsigned(XAmCap7);
+
+   p_AMmatch : process(clk_i)
+   begin
+      if rising_edge(clk_i) then  
+         if mainFSMreset = '1' or reset = '1' then
+            AmMatch <= (others => '0');
+         elsif decode = '1' then	  
+            for i in AmMatch'range loop
+               if DFS_i(i) = '1' then
+                  if s_FUNC_ADER(i)(XAM_MODE) = '0' then
+                     if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(Am) then
+                        AmMatch(i) <= s_amcap_match(i);                   
+                     else
+                        AmMatch(i) <= '0';
+                     end if;
+                  else
+                     if (unsigned(XAm) = unsigned(s_FUNC_ADER(i)(9 downto 2))) then
+                        AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);                 
+                     else
+                        AmMatch(i) <= '0';
+                     end if;
+                  end if;
+               else  
+                  if s_FUNC_ADER(i)(XAM_MODE) = '1' then
+                     AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);                        				
+                  else
+                     AmMatch(i) <= s_amcap_match(i);              
+                  end if;
+               end if;		
+            end loop;
+         end if;	
+      end if;
+   end process;
+------------------------------------------------------
+-- Check if the AM is in the AMCAP register
+   process(s_FUNC_AMCAP, Am)
+   begin
+      s_amcap_match <= (others => '0');
+      for i in 0 to 7 loop
+         s_amcap_match(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am)));  
+      end loop;
+   end process;
+-------------------------------------------------------
+-- Check if the XAM is in the XAMCAP register    
+   process(s_FUNC_XAMCAP, XAm)
+   begin
+      s_xamcap_match <= (others => '0');
+      for i in 0 to 7 loop    
+         s_xamcap_match(i) <= s_FUNC_XAMCAP(i)(to_integer(unsigned(XAm)));
+      end loop;
+   end process;
+------------------------------------------------------
+end Behavioral;
+--===========================================================================
+-- Architecture end
+--===========================================================================
--- a/hdl/VME_Buffer.vhd
+++ b/hdl/VME_Buffer.vhd
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.VME_Buffer_pack.all;
+use work.xVME64x_pack.all;
+
+-- Buffer direction
+-- VME to FPGA -> _v2f_ in schematics ab, negative logic
+-- FPGA to VME -> _f2v_ in schematics ba, negative logic
+
+entity VME_Buffer_ctrl  is
+   generic(
+      g_bus_mode        : bus_mode  := LATCHED); -- CLOCK         
+      
+   port( 
+      clk_i             : in  std_logic;
+      rst_i             : in  std_logic;
+      buffer_stat_i     : in  t_VME_BUFFER;
+      
+      buffer_clk_o      : out std_logic;
+
+      data_buff_v2f_o   : out std_logic;
+      data_buff_f2v_o   : out std_logic;
+
+      addr_buff_v2f_o   : out std_logic;
+      addr_buff_f2v_o   : out std_logic;
+
+      latch_buff_o      : out std_logic
+   );
+end entity;
+
+architecture behavioural of VME_Buffer_ctrl is
+
+   signal   pre_clk  :  std_logic := '0';
+begin
+	
+   clock_buff_gen :  process(clk_i, rst_i)
+   begin
+   
+      if rising_edge(clk_i)   then
+         if rst_i =  '0'   then
+            buffer_clk_o      <= '0';
+				pre_clk				<= '0';
+        else
+			  pre_clk <= buffer_stat_i.s_clk;
+			  
+           if (pre_clk = buffer_stat_i.s_clk) or  
+              (buffer_stat_i.s_clk = '0') then
+
+              buffer_clk_o    <= '0';
+
+           else   -- There is a transition 
+
+              buffer_clk_o    <= '1';
+           end if;
+         end if;
+      end if;
+   end process;
+	
+-- VME -> FPGA, WRITE from VME_bus s_DataDir = 0
+-- FPGA -> VME, READ  from FPGA    s_DataDir = 1
+	with buffer_stat_i.s_buffer_eo select
+		addr_buff_v2f_o	<= buffer_stat_i.s_addrDir 		when	ADDR_BUFF,	
+									'1'									when	DATA_BUFF,
+									buffer_stat_i.s_addrDir			when  DATA_ADDR_BUFF;
+
+	with buffer_stat_i.s_buffer_eo select
+		addr_buff_f2v_o	<= not buffer_stat_i.s_addrDir	when	ADDR_BUFF,	
+									'1'									when	DATA_BUFF,
+									not buffer_stat_i.s_addrDir	when  DATA_ADDR_BUFF;
+	
+	with buffer_stat_i.s_buffer_eo select
+		data_buff_v2f_o	<= '1'									when	ADDR_BUFF,	
+									buffer_stat_i.s_dataDir			when	DATA_BUFF,
+									buffer_stat_i.s_dataDir			when  DATA_ADDR_BUFF;	
+								
+	with buffer_stat_i.s_buffer_eo select
+		data_buff_f2v_o	<= '1'									when	ADDR_BUFF,	
+									not buffer_stat_i.s_dataDir	when	DATA_BUFF,
+									not buffer_stat_i.s_dataDir	when  DATA_ADDR_BUFF;
+
+   with g_bus_mode   select
+      latch_buff_o   <= '1'   when  LATCHED,
+                        '0'   when  CLOCKED;
+
+--   dir_eo_buff_ctrl   :  process(clk_i, rst_i)
+--   begin
+--      if rising_edge(clk_i)   then
+--
+--         if rst_i=   '0'   then                  
+--            addr_buff_v2f_o    <= buffer_stat_i.s_addrDir;
+--            addr_buff_f2v_o    <= not buffer_stat_i.s_addrDir;
+--
+--            data_buff_v2f_o    <= '1';
+--            data_buff_f2v_o    <= '1';
+--
+--         else
+--
+--
+--            case buffer_stat_i.s_buffer_eo is
+--
+--               when ADDR_BUFF       =>
+--                  addr_buff_v2f_o    <= buffer_stat_i.s_addrDir;
+--                  addr_buff_f2v_o    <= not buffer_stat_i.s_addrDir;
+--
+--                  data_buff_v2f_o    <= '1';
+--                  data_buff_f2v_o    <= '1';
+--
+--               when DATA_BUFF       =>
+--                  addr_buff_v2f_o    <= '1'; 
+--                  addr_buff_f2v_o    <= '1';
+--
+--                  data_buff_v2f_o    <= buffer_stat_i.s_dataDir;
+--                  data_buff_f2v_o    <= not buffer_stat_i.s_dataDir;
+--               when DATA_ADDR_BUFF  =>
+--                  addr_buff_v2f_o    <= buffer_stat_i.s_addrDir;
+--                  addr_buff_f2v_o    <= not buffer_stat_i.s_addrDir;
+--
+--                  data_buff_v2f_o    <= buffer_stat_i.s_dataDir;
+--                  data_buff_f2v_o    <= not buffer_stat_i.s_dataDir;
+--            end case;
+--            
+--         end if;
+--      end if;
+--
+--   end process;
+   
+end architecture;
--- a/hdl/VME_Buffer_pack.vhd
+++ b/hdl/VME_Buffer_pack.vhd
+--_______________________________________________________________________________________
+--                             VME TO WB INTERFACE
+--
+--                                CERN,BE/CO-HT 
+--______________________________________________________________________________________
+-- File:                          VME_BUFFER_pack.vhd
+--______________________________________________________________________________________
+-- Description: Buffer functionality 
+--______________________________________________________________________________________
+-- Authors:                                       
+--              Cesar Prados <c.prados@gsi.de>
+-- Date         02/2013           
+-- Version      v0.01 
+--______________________________________________________________________________________
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                
+--                              ------------------------------------    
+-- Copyright (c) 2009 - 2011 CERN                           
+-- This source file is free software; you can redistribute it and/or modify it 
+-- under the terms of the GNU Lesser General Public License as published by the 
+-- Free Software Foundation; either version 2.1 of the License, or (at your option) 
+-- any later version. This source is distributed in the hope that it will be useful, 
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for 
+-- more details. You should have received a copy of the GNU Lesser General Public 
+-- License along with this source; if not, download it from 
+-- http://www.gnu.org/licenses/lgpl-2.1.html                     
+---------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.numeric_std.all;
+
+use work.xvme64x_pack.all;
+
+package VME_Buffer_pack is
+
+   function buffer_function ( fsm          : t_mainFSMstates;
+                              is_d64       : std_logic;
+                              vme_write    : std_logic)
+                            return t_VME_BUFFER;
+                            
+   type bus_mode is (  LATCHED,
+                       CLOCKED);
+							  
+   component VME_Buffer_ctrl  is
+		generic(
+			g_bus_mode        : bus_mode  := LATCHED); -- CLOCK 
+		port( 
+         clk_i            : in  std_logic;
+         rst_i            : in  std_logic;
+         buffer_stat_i    : in  t_VME_BUFFER;
+         buffer_clk_o     : out std_logic;
+
+         data_buff_v2f_o  : out std_logic;
+         data_buff_f2v_o  : out std_logic;
+
+         addr_buff_v2f_o  : out std_logic;
+         addr_buff_f2v_o  : out std_logic;
+
+         latch_buff_o     : out std_logic
+      );
+   end component VME_Buffer_ctrl;
+	
+	constant VME2FPGA		: std_logic :=	'0';
+	constant FPGA2VME		: std_logic :=	'1';
+	constant WRITE_C		: std_logic :=	'0';
+	constant READ_C		: std_logic := '1'; 
+
+end VME_Buffer_pack;
+
+package body VME_Buffer_pack is
+
+-- Buffer direction
+-- VME to FPGA -> _v2f_ in schematics ab, negative logic e.g READ Cycle  in Data 
+-- FPGA to VME -> _f2v_ in schematics ba, negative logic e.g WRITE Cycle in Data
+
+   function buffer_function ( fsm          : t_mainFSMstates;
+                              is_d64       : std_logic;
+                              vme_write    : std_logic)
+                            return t_VME_BUFFER is
+
+        variable vme_buff       : t_VME_BUFFER  := c_buffer_default;
+
+    begin
+
+        case fsm is
+
+            when IDLE => 
+
+               vme_buff.s_addrDir	:= VME2FPGA;
+					vme_buff.s_dataDir 	:= VME2FPGA;
+               vme_buff.s_buffer_eo := ADDR_BUFF;
+               vme_buff.s_clk 		:= '1';
+
+            when DECODE_ACCESS  =>
+ 
+               vme_buff.s_addrDir	:= VME2FPGA;
+					vme_buff.s_dataDir 	:= VME2FPGA;
+               vme_buff.s_buffer_eo := ADDR_BUFF;
+					vme_buff.s_clk       := '0';                   
+				
+				when	WAIT_FOR_DS | LATCH_DS1 | LATCH_DS2
+				     | LATCH_DS3 | LATCH_DS4 =>
+					
+					if('1' = is_d64) then
+						vme_buff.s_buffer_eo    := DATA_ADDR_BUFF;
+					else
+						vme_buff.s_buffer_eo    := DATA_BUFF;
+					end if;
+					
+					if	vme_write = WRITE_C then 		  
+						vme_buff.s_addrDir 	:= VME2FPGA;
+						vme_buff.s_dataDir 	:= VME2FPGA;
+					else -- READ_C
+						vme_buff.s_addrDir 	:= FPGA2VME;
+						vme_buff.s_dataDir 	:= FPGA2VME;  
+					end if;
+						
+					vme_buff.s_clk          := '0';
+					
+				when CHECK_TRANSFER_TYPE | MEMORY_REQ =>
+						
+					if('1' = is_d64) then
+						vme_buff.s_buffer_eo    := DATA_ADDR_BUFF;
+					else
+						vme_buff.s_buffer_eo    := DATA_BUFF;
+					end if;
+					
+					if	vme_write = WRITE_C then 		  
+						vme_buff.s_addrDir 	:= VME2FPGA;
+						vme_buff.s_dataDir 	:= VME2FPGA;
+					else -- READ_C
+						vme_buff.s_addrDir 	:= FPGA2VME;
+						vme_buff.s_dataDir 	:= FPGA2VME;  
+					end if;
+						
+					vme_buff.s_clk          := '0';	
+
+            when DATA_TO_BUS | DTACK_LOW | DECIDE_NEXT_CYCLE =>
+
+					if('1' = is_d64) then
+						vme_buff.s_buffer_eo    := DATA_ADDR_BUFF;
+					else
+						vme_buff.s_buffer_eo    := DATA_BUFF;
+					end if;
+					
+					if	vme_write = WRITE_C then 		  
+						vme_buff.s_addrDir 	:= VME2FPGA;
+						vme_buff.s_dataDir 	:= VME2FPGA;
+					else -- READ_C
+						vme_buff.s_addrDir 	:= FPGA2VME;
+						vme_buff.s_dataDir 	:= FPGA2VME;  
+					end if;
+						
+					vme_buff.s_clk          := '1';
+
+				when INCREMENT_ADDR | SET_DATA_PHASE  =>
+				
+					if('1' = is_d64) then
+						vme_buff.s_buffer_eo    := DATA_ADDR_BUFF;
+					else
+						vme_buff.s_buffer_eo    := DATA_BUFF;
+					end if;
+					
+					if	vme_write = WRITE_C then 		  
+						vme_buff.s_addrDir 	:= VME2FPGA;
+						vme_buff.s_dataDir 	:= VME2FPGA;
+					else -- READ_C
+						vme_buff.s_addrDir 	:= FPGA2VME;
+						vme_buff.s_dataDir 	:= FPGA2VME;  
+					end if;
+						
+					vme_buff.s_clk          := '0';
+					
+				when others =>		
+					vme_buff.s_addrDir 	:= VME2FPGA;
+					vme_buff.s_dataDir 	:= VME2FPGA;
+               vme_buff.s_buffer_eo := ADDR_BUFF;
+					vme_buff.s_clk       := '0'; 
+					
+			end case;
+
+      return vme_buff;
+
+   end buffer_function;
+
+end VME_Buffer_pack;
+
--- a/hdl/VME_CRAM.vhd
+++ b/hdl/VME_CRAM.vhd
+--______________________________________________________________________________|
+--                             VME TO WB INTERFACE                              |
+--                                                                              |
+--                                CERN,BE/CO-HT                                 |
+--______________________________________________________________________________|
+-- File:                        VME_CRAM.vhd                                  |
+--______________________________________________________________________________|
+-- Description: RAM memory
+--______________________________________________________________________________
+-- Authors:                                      
+--               Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)                             
+--               Davide Pedretti       (Davide.Pedretti@cern.ch)  
+-- Date         11/2012                                                                           
+-- Version      v0.03  
+--______________________________________________________________________________
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                
+--                              ------------------------------------    
+-- Copyright (c) 2009 - 2011 CERN                           
+-- This source file is free software; you can redistribute it and/or modify it under the terms of 
+-- the GNU Lesser General Public License as published by the Free Software Foundation; either     
+-- version 2.1 of the License, or (at your option) any later version.                             
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       
+-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.     
+-- See the GNU Lesser General Public License for more details.                                    
+-- You should have received a copy of the GNU Lesser General Public License along with this       
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     
+---------------------------------------------------------------------------------------
+                                                               
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.xvme64x_pack.all;
+--===========================================================================
+-- Entity declaration
+--===========================================================================
+ entity VME_CRAM is
+ generic (dl : integer; 		
+ 			 al : integer := f_log2_size(c_CRAM_SIZE) 		
+			 );    
+ port (clk  : in std_logic; 			
+ 	we   : in std_logic; 				
+ 	aw    : in std_logic_vector(al - 1 downto 0); 	 
+ 	di   : in std_logic_vector(dl - 1 downto 0); 
+ 	dw  : out std_logic_vector(dl - 1 downto 0)
+	);   	 
+ end VME_CRAM; 
+ 												
+--===========================================================================
+-- Architecture declaration
+--===========================================================================
+ architecture syn of VME_CRAM is 
+ 
+ type ram_type is array (2**al - 1 downto 0) of std_logic_vector (dl - 1 downto 0); 
+ signal CRAM : ram_type; 
+
+--===========================================================================
+-- Architecture begin
+--===========================================================================
+begin 
+
+ process (clk) 
+ begin 
+ 	if (clk'event and clk = '1') then  
+ 		if (we = '1') then 
+ 			CRAM(conv_integer(aw)) <= di; 
+ 		end if; 
+		dw <= CRAM(conv_integer(aw));
+ 	end if; 
+ end process; 
+ 
+ end syn;
+--===========================================================================
+-- Architecture end
+--===========================================================================
+ 
--- a/hdl/VME_CR_CSR_Space.vhd
+++ b/hdl/VME_CR_CSR_Space.vhd
--- a/hdl/VME_CR_pack.vhd
+++ b/hdl/VME_CR_pack.vhd
--- a/hdl/VME_CSR_pack.vhd
+++ b/hdl/VME_CSR_pack.vhd
+--________________________________________________________________________________________________
+--                             VME TO WB INTERFACE
+--
+--                                CERN,BE/CO-HT 
+--________________________________________________________________________________________________
+-- File:                         VME_CSR_pack.vhd
+--________________________________________________________________________________________________
+-- Description: This file defines the default configuration of the CSR space after power-up or 
+-- software reset.
+--______________________________________________________________________________
+-- Authors:                                      
+--               Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)                             
+--               Davide Pedretti       (Davide.Pedretti@cern.ch)  
+-- Date         06/2012                                                                           
+-- Version      v0.02  
+--______________________________________________________________________________
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                
+--                              ------------------------------------    
+-- Copyright (c) 2009 - 2011 CERN                           
+-- This source file is free software; you can redistribute it and/or modify it 
+-- under the terms of the GNU Lesser General Public License as published by the 
+-- Free Software Foundation; either version 2.1 of the License, or (at your option) 
+-- any later version. This source is distributed in the hope that it will be useful, 
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for 
+-- more details. You should have received a copy of the GNU Lesser General Public 
+-- License along with this source; if not, download it from 
+-- http://www.gnu.org/licenses/lgpl-2.1.html                     
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.numeric_std.all;
+
+use work.xvme64x_pack.all;
+package VME_CSR_pack is
+
+constant c_csr_array : 	t_CSRarray :=
+(
+BAR  => x"00", --CR/CSR BAR
+BIT_SET_CLR_REG  => x"00", --Bit set register -- 0x10=module enable
+USR_BIT_SET_CLR_REG  => x"00", --Bit clear register
+CRAM_OWNER  => x"00", --CRAM_OWNER
+
+FUNC0_ADER_0 =>x"00",  --A32_S   "24"
+FUNC0_ADER_1 =>x"00",  --        "00"
+FUNC0_ADER_2 =>x"00",  --        "00"
+FUNC0_ADER_3 =>x"00",  --        "c0"
+
+FUNC1_ADER_0 =>x"00",  --A24_S   "e4"
+FUNC1_ADER_1 =>x"00",  --        "00"
+FUNC1_ADER_2 =>x"00",  --        "c0" 
+FUNC1_ADER_3 =>x"00",  --        "00"  
+
+FUNC2_ADER_0 =>x"00",   --A16_S  "a4"
+FUNC2_ADER_1 =>x"00",  --        "c0"
+FUNC2_ADER_2 =>x"00",  --        "00"
+FUNC2_ADER_3 =>x"00",  --        "00"
+
+FUNC3_ADER_0 =>x"00",   --A64_S  "04"
+FUNC3_ADER_1 =>x"00",
+FUNC3_ADER_2 =>x"00",
+FUNC3_ADER_3 =>x"00",
+
+FUNC4_ADER_0 =>x"00",   --used for decoding the FUNC3
+FUNC4_ADER_1 =>x"00",   --used for decoding the FUNC3
+FUNC4_ADER_2 =>x"00",   --used for decoding the FUNC3
+FUNC4_ADER_3 =>x"00",   --used for decoding the FUNC3 "c0"
+
+FUNC5_ADER_0 =>x"00",
+FUNC5_ADER_1 =>x"00",
+FUNC5_ADER_2 =>x"00",
+FUNC5_ADER_3 =>x"00",
+
+FUNC6_ADER_0 =>x"00",
+FUNC6_ADER_1 =>x"00",
+FUNC6_ADER_2 =>x"00",
+FUNC6_ADER_3 =>x"00",
+
+IRQ_Vector   =>x"00",  --"00" because each Slot has a different IRQ Vector
+                       -- and the VME Master should set this value
+IRQ_level    =>x"02",
+WB32bits     =>x"01",  -- 32 bit WB of default
+others => (others => '0'));
+end VME_CSR_pack;                                                                
+
+
+
+
+
+
+
+ 
+
+
+
+
+
+
+
+
+
+
+
+
--- a/hdl/VME_Funct_Match.vhd
+++ b/hdl/VME_Funct_Match.vhd
--- a/hdl/VME_IRQ_Controller.vhd
+++ b/hdl/VME_IRQ_Controller.vhd
--- a/hdl/VME_Init.vhd
+++ b/hdl/VME_Init.vhd
--- a/hdl/VME_SharedComps.vhd
+++ b/hdl/VME_SharedComps.vhd
+--_______________________________________________________________________________________
+--                             VME TO WB INTERFACE
+--
+--                                CERN,BE/CO-HT 
+--_______________________________________________________________________________________
+-- File:                       VME_SharedComps.vhd
+--_______________________________________________________________________________________
+-- Description: This component implements the rising and falling edge detection and the 
+-- tripple and double sample entities
+--_______________________________________________________________________________________
+-- Authors:                                     
+--               Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)                             
+--               Davide Pedretti       (Davide.Pedretti@cern.ch)  
+-- Date         11/2012                                                                           
+-- Version      v0.03  
+--_______________________________________________________________________________________
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                
+--                              ------------------------------------    
+-- Copyright (c) 2009 - 2011 CERN                           
+-- This source file is free software; you can redistribute it and/or modify it 
+-- under the terms of the GNU Lesser General Public License as published by the 
+-- Free Software Foundation; either version 2.1 of the License, or (at your option) 
+-- any later version. This source is distributed in the hope that it will be useful, 
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for 
+-- more details. You should have received a copy of the GNU Lesser General Public 
+-- License along with this source; if not, download it from 
+-- http://www.gnu.org/licenses/lgpl-2.1.html                     
+----------------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- tripple sample sig_i signals to avoid metastable states
+entity SigInputSample is
+	port (
+		sig_i, clk_i: in std_logic;
+		sig_o: out std_logic );
+end SigInputSample;
+
+architecture RTL of SigInputSample is
+	signal s_1: std_logic;
+	signal s_2: std_logic;
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			s_1   <= sig_i;
+			s_2   <= s_1;
+			sig_o <= s_2;
+		end if;
+	end process;
+end RTL;
+
+-- *************************************************** 
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- double sample sig_i signals to avoid metastable states
+entity DoubleSigInputSample is
+	port (
+		sig_i, clk_i: in std_logic;
+		sig_o: out std_logic );
+end DoubleSigInputSample;
+
+architecture RTL of DoubleSigInputSample is
+	signal s_1: std_logic;
+--	signal s_2: std_logic;
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			s_1     <= sig_i;
+			sig_o   <= s_1;
+		end if;
+	end process;
+end RTL;
+--***************************************************
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity SingleRegInputSample is 
+	generic(
+		width: natural:=8
+		);
+	port (
+		reg_i: in std_logic_vector(width-1 downto 0);
+		reg_o: out std_logic_vector(width-1 downto 0);
+		clk_i: in std_logic 
+		);
+end SingleRegInputSample;
+
+architecture RTL of SingleRegInputSample is
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			reg_o <= reg_i;		 
+		end if;
+	end process;
+end RTL;
+-- ***************************************************
+--FlipFlopD
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+entity FlipFlopD is
+	port (
+		reset, sig_i, clk_i, enable: in std_logic;
+		sig_o: out std_logic );
+end FlipFlopD;
+
+architecture RTL of FlipFlopD is
+--	signal s_1: std_logic;
+--	signal s_2: std_logic;
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+		   if reset = '1' then
+			   sig_o <= '0';
+			elsif enable = '1' then	
+			sig_o     <= sig_i;
+			--sig_o   <= s_1;
+		   end if;
+		end if;	
+	end process;
+end RTL;
+--Register 32 bits
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+entity Reg32bit is
+	port (
+		reset, clk_i, enable: in std_logic;
+		di : in std_logic_vector(31 downto 0);
+		do: out std_logic_vector(31 downto 0)
+		);
+end Reg32bit;
+architecture RTL of Reg32bit is
+--signal s_reg : std_logic_vector(31 downto 0);
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+		   if reset = '0' then 
+			     do <= (others => '0');
+				  --s_reg <= (others => '0');
+			elsif enable = '1' then	
+			     do <= di;
+			--s_reg <= di;
+			end if;
+		end if;	
+		--do <= s_reg;
+	end process;
+end RTL;
+
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- detect rising edge
+entity RisEdgeDetection is
+	port (
+		sig_i, clk_i: in std_logic;
+		RisEdge_o: out std_logic );
+end RisEdgeDetection;
+
+architecture RTL of RisEdgeDetection is
+	signal s_1: std_logic;
+	constant delay_c :integer := 4;
+	signal cnt :integer:=0;
+	type state_type is (idle,delay); 
+	signal next_s : state_type :=idle; 
+	
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+		
+		s_1 <= sig_i;
+		
+--		case  next_s	is
+--			when idle =>
+--				if s_1 = '0' and sig_i = '1' then
+--					cnt <= 0;
+--					--RisEdge_o <= '1';
+--					next_s <= delay;
+--				else
+--					RisEdge_o <= '0';
+--				end if;
+--				
+--			when delay =>
+--				
+--				if(cnt = delay_c) then
+--					RisEdge_o <= '1';
+--					next_s <= idle;
+--				else
+--					cnt <= cnt +1;
+--				end if;
+--			end case;
+			if s_1 = '0' and sig_i = '1' then
+				RisEdge_o <= '1';
+			else
+				RisEdge_o <= '0';
+			end if;
+			
+		end if;
+	end process;
+end RTL;   
+
+-- ***************************************************   
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- detect falling edge
+entity FallingEdgeDetection is
+	port (
+		sig_i, clk_i: in std_logic;
+		FallEdge_o: out std_logic );
+end FallingEdgeDetection;
+
+architecture RTL of FallingEdgeDetection is
+	signal s_1: std_logic;
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			
+			s_1 <= sig_i;
+			
+			if s_1 = '1' and sig_i = '0' then
+				FallEdge_o <= '1';
+			else
+				FallEdge_o <= '0';
+			end if;
+			
+		end if;
+	end process;
+end RTL;
+
+-- ***************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- give pulse (sigEdge_o) at rising and falling edge
+entity EdgeDetection is
+	port (
+		sig_i, 
+		clk_i: in std_logic;
+		sigEdge_o: out std_logic
+		);
+end EdgeDetection;
+
+architecture RTL of EdgeDetection is
+	signal s_1: std_logic;
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			
+			s_1 <= sig_i;
+			
+			if (s_1 = '0' and sig_i = '1') or (s_1 = '1' and sig_i = '0') then
+				sigEdge_o <= '1';
+			else
+				sigEdge_o <= '0';
+			end if;
+			
+		end if;
+	end process;
+end RTL;
+
+-- ***************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- triple sample input register reg_i to avoid metastable states
+-- and catching of transition values
+entity RegInputSample is 
+	generic(
+		width: natural:=8
+		);
+	port (
+		reg_i: in std_logic_vector(width-1 downto 0);
+		reg_o: out std_logic_vector(width-1 downto 0);
+		clk_i: in std_logic 
+		);
+end RegInputSample;
+
+architecture RTL of RegInputSample is
+	signal reg_1, reg_2: std_logic_vector(width-1 downto 0);
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			reg_1 <= reg_i;
+			reg_2 <= reg_1;	
+			reg_o <= reg_2;	 
+
+		end if;
+	end process;
+end RTL;
+
+
+-- ***************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+-- triple sample input register reg_i to avoid metastable states
+-- and catching of transition values
+entity DoubleRegInputSample is 
+	generic(
+		width: natural:=8
+		);
+	port (
+		reg_i: in std_logic_vector(width-1 downto 0);
+		reg_o: out std_logic_vector(width-1 downto 0);
+		clk_i: in std_logic 
+		);
+end DoubleRegInputSample;
+
+architecture RTL of DoubleRegInputSample is
+	signal reg_1, reg_2: std_logic_vector(width-1 downto 0);
+begin
+	process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			reg_1 <= reg_i;
+			reg_o <= reg_1;		 
+
+		end if;
+	end process;
+end RTL;
\ No newline at end of file
--- a/hdl/VME_Wb_master.vhd
+++ b/hdl/VME_Wb_master.vhd
--- a/hdl/VME_bus.vhd
+++ b/hdl/VME_bus.vhd
--- a/hdl/VME_swapper.vhd
+++ b/hdl/VME_swapper.vhd
+--______________________________________________________________________________
+--                             VME TO WB INTERFACE
+--
+--                                CERN,BE/CO-HT 
+--______________________________________________________________________________
+-- File:                           VME_swapper.vhd
+--______________________________________________________________________________
+-- Description: 
+--sel= 00 --> No swap
+--sel= 01 --> Swap Byte            eg: 01234567 became 10325476
+--sel= 10 --> Swap Word            eg: 01234567 became 23016745
+--sel= 11 --> Swap Word+ Swap Byte eg: 01234567 became 32107654
+--______________________________________________________________________________
+-- Authors:                                                                    
+--               Davide Pedretti       (Davide.Pedretti@cern.ch)  
+-- Date         11/2012                                                                           
+-- Version      v0.03  
+--______________________________________________________________________________
+--                               GNU LESSER GENERAL PUBLIC LICENSE                                
+--                              ------------------------------------    
+-- Copyright (c) 2009 - 2011 CERN                           
+-- This source file is free software; you can redistribute it and/or modify it 
+-- under the terms of the GNU Lesser General Public License as published by the 
+-- Free Software Foundation; either version 2.1 of the License, or (at your option) 
+-- any later version. This source is distributed in the hope that it will be useful, 
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for 
+-- more details. You should have received a copy of the GNU Lesser General Public 
+-- License along with this source; if not, download it from 
+-- http://www.gnu.org/licenses/lgpl-2.1.html                     
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--===========================================================================
+-- Entity declaration
+--===========================================================================
+entity VME_swapper is
+    Port ( d_i : in  STD_LOGIC_VECTOR (63 downto 0);
+	        sel : in  STD_LOGIC_VECTOR (2 downto 0);
+           d_o : out  STD_LOGIC_VECTOR (63 downto 0));
+end VME_swapper;
+--===========================================================================
+-- Architecture declaration
+--===========================================================================
+architecture Behavioral of VME_swapper is
+signal Byte0_i : std_logic_vector(7 downto 0);
+signal Byte1_i : std_logic_vector(7 downto 0);
+signal Byte2_i : std_logic_vector(7 downto 0);
+signal Byte3_i : std_logic_vector(7 downto 0);
+signal Byte4_i : std_logic_vector(7 downto 0);
+signal Byte5_i : std_logic_vector(7 downto 0);
+signal Byte6_i : std_logic_vector(7 downto 0);
+signal Byte7_i : std_logic_vector(7 downto 0);
+signal Byte0_o : std_logic_vector(7 downto 0);
+signal Byte1_o : std_logic_vector(7 downto 0);
+signal Byte2_o : std_logic_vector(7 downto 0);
+signal Byte3_o : std_logic_vector(7 downto 0);
+signal Byte4_o : std_logic_vector(7 downto 0);
+signal Byte5_o : std_logic_vector(7 downto 0);
+signal Byte6_o : std_logic_vector(7 downto 0);
+signal Byte7_o : std_logic_vector(7 downto 0);
+--===========================================================================
+-- Architecture begin
+--===========================================================================
+begin
+
+process (sel,Byte0_i,Byte1_i,Byte2_i,Byte3_i,Byte7_i)
+begin
+   case sel is
+      when "000"  => Byte0_o <= Byte0_i;
+      when "001"  => Byte0_o <= Byte1_i;
+      when "010"  => Byte0_o <= Byte2_i;
+      when "011"  => Byte0_o <= Byte3_i;
+		when "100"  => Byte0_o <= Byte7_i;
+      when others => Byte0_o <= Byte0_i;
+   end case;
+end process;
+
+process (sel,Byte0_i,Byte1_i,Byte2_i,Byte3_i,Byte6_i)
+begin
+   case sel is
+      when "000"  => Byte1_o <= Byte1_i;
+      when "001"  => Byte1_o <= Byte0_i;
+      when "010"  => Byte1_o <= Byte3_i;
+      when "011"  => Byte1_o <= Byte2_i;
+		when "100"  => Byte1_o <= Byte6_i;
+      when others => Byte1_o <= Byte1_i;
+   end case;
+end process;
+
+process (sel,Byte0_i,Byte1_i,Byte2_i,Byte3_i,Byte5_i)
+begin
+   case sel is
+      when "000"   => Byte2_o   <= Byte2_i;
+      when "001"   => Byte2_o   <= Byte3_i;
+      when "010"   => Byte2_o   <= Byte0_i;
+      when "011"   => Byte2_o   <= Byte1_i;
+		when "100"   => Byte2_o   <= Byte5_i;
+      when others  => Byte2_o   <= Byte2_i;
+   end case;
+end process;
+
+process (sel,Byte0_i,Byte1_i,Byte2_i,Byte3_i,Byte4_i)
+begin
+   case sel is
+      when "000"  => Byte3_o <= Byte3_i;
+      when "001"  => Byte3_o <= Byte2_i;
+      when "010"  => Byte3_o <= Byte1_i;
+      when "011"  => Byte3_o <= Byte0_i;
+		when "100"  => Byte3_o <= Byte4_i;
+      when others => Byte3_o <= Byte3_i;
+   end case;
+end process;
+
+process (sel,Byte4_i,Byte5_i,Byte6_i,Byte7_i,Byte3_i)
+begin
+   case sel is
+      when "000"  => Byte4_o <= Byte4_i;
+      when "001"  => Byte4_o <= Byte5_i;
+      when "010"  => Byte4_o <= Byte6_i;
+      when "011"  => Byte4_o <= Byte7_i;
+		when "100"  => Byte4_o <= Byte3_i;
+      when others => Byte4_o <= Byte4_i;
+   end case;
+end process;
+
+process (sel,Byte4_i,Byte5_i,Byte6_i,Byte7_i,Byte2_i)
+begin
+   case sel is
+      when "000"  => Byte5_o <= Byte5_i;
+      when "001"  => Byte5_o <= Byte4_i;
+      when "010"  => Byte5_o <= Byte7_i;
+      when "011"  => Byte5_o <= Byte6_i;
+		when "100"  => Byte5_o <= Byte2_i;
+      when others => Byte5_o <= Byte5_i;
+   end case;
+end process;
+
+process (sel,Byte4_i,Byte5_i,Byte6_i,Byte7_i,Byte1_i)
+begin
+   case sel is
+      when "000"  => Byte6_o <= Byte6_i;
+      when "001"  => Byte6_o <= Byte7_i;
+      when "010"  => Byte6_o <= Byte4_i;
+      when "011"  => Byte6_o <= Byte5_i;
+		when "100"  => Byte6_o <= Byte1_i;
+      when others => Byte6_o <= Byte6_i;
+   end case;
+end process;
+
+process (sel,Byte4_i,Byte5_i,Byte6_i,Byte7_i,Byte0_i)
+begin
+   case sel is
+      when "000"  => Byte7_o <= Byte7_i;
+      when "001"  => Byte7_o <= Byte6_i;
+      when "010"  => Byte7_o <= Byte5_i;
+      when "011"  => Byte7_o <= Byte4_i;
+		when "100"  => Byte7_o <= Byte0_i;
+      when others => Byte7_o <= Byte7_i;
+   end case;
+end process;
+
+Byte0_i           <= d_i(7 downto 0);
+Byte1_i           <= d_i(15 downto 8);
+Byte2_i           <= d_i(23 downto 16);
+Byte3_i           <= d_i(31 downto 24);
+Byte4_i           <= d_i(39 downto 32);
+Byte5_i           <= d_i(47 downto 40);
+Byte6_i           <= d_i(55 downto 48);
+Byte7_i           <= d_i(63 downto 56);
+d_o(7 downto 0)   <= Byte0_o;
+d_o(15 downto 8)  <= Byte1_o;
+d_o(23 downto 16) <= Byte2_o;
+d_o(31 downto 24) <= Byte3_o;
+d_o(39 downto 32) <= Byte4_o;
+d_o(47 downto 40) <= Byte5_o;
+d_o(55 downto 48) <= Byte6_o;
+d_o(63 downto 56) <= Byte7_o;
+
+end Behavioral;
+--===========================================================================
+-- Architecture end
+--===========================================================================
--- a/hdl/vme64x_pack.vhd
+++ b/hdl/vme64x_pack.vhd
--- a/hdl/xVME64xCore_Top.vhd
+++ b/hdl/xVME64xCore_Top.vhd
--- a/hdl/xvme64x_pack.vhd
+++ b/hdl/xvme64x_pack.vhd