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legacy-vme64x-core
Commit 6b9861ee authored by Cesar Prados's avatar Cesar Prados
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sdb: add sdb to wishbone mater

parent a850aab9
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Showing with 31 additions and 20 deletions
hdl/VME_Wb_master.vhd
View file @ 6b9861ee
......@@ -59,14 +59,17 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.xvme64x_pack.all;
use work.wishbone_pkg.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity VME_Wb_master is
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
g_wb_addr_width : integer := c_addr_width;
g_family : string := "Arria II VME-WB";
g_sdb_addr : t_wishbone_address := c_sdb_address);
Port ( memReq_i : in std_logic;
clk_i : in std_logic;
cardSel_i : in std_logic;
......
hdl/VME_bus.vhd
View file @ 6b9861ee
......@@ -74,6 +74,7 @@ use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.VME_Buffer_pack.all;
use work.xvme64x_pack.all;
use work.wishbone_pkg.all;
--===========================================================================
-- Entity declaration
--===========================================================================
......@@ -81,7 +82,8 @@ entity VME_bus is
generic(g_clock : integer := c_clk_period;
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_cram_size : integer := c_CRAM_SIZE
g_cram_size : integer := c_CRAM_SIZE;
g_sdb_addr : t_wishbone_address := c_sdb_address
);
port(
clk_i : in std_logic; -- 125 Mhz
......@@ -1185,7 +1187,8 @@ with s_addressingType select
Inst_Wb_master: VME_Wb_master
generic map(
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width
g_wb_addr_width => g_wb_addr_width,
g_sdb_addr => g_sdb_addr
)
port map(
memReq_i => s_memReq,
......
hdl/vme64x_pack.vhd
View file @ 6b9861ee
......@@ -206,10 +206,6 @@ package vme64x_pack is
constant BYTES1 : integer := FUNC0_ADER_3 -11;
constant WB32bits : integer := FUNC0_ADER_3 -12;
constant Endian : integer := FUNC0_ADER_3 -4;
constant SDB_ADDR_0 : integer := 200;
constant SDB_ADDR_1 : integer := SDB_ADDR_1 -1;
constant SDB_ADDR_2 : integer := SDB_ADDR_1 -2;
constant SDB_ADDR_3 : integer := SDB_ADDR_1 -3;
-- Initialization CR:
constant BEG_USER_CR : integer := 1;
......@@ -332,8 +328,6 @@ package vme64x_pack is
constant c_BYTES1_addr : unsigned(19 downto 0) := x"7FF37";
constant c_WB32bits_addr : unsigned(19 downto 0) := x"7FF33";
constant c_Endian_addr : unsigned(19 downto 0) := x"7FF53"; -- VME64x reserved CSR
-- USER CSR address:
constant c_SDB_ADDR : unsigned(19 downto 0) := x"7A00B";
--___________________________________________________________________________________________
-- TYPE:
type t_typeOfDataTransfer is ( D08_0,
......@@ -463,7 +457,9 @@ function f_latchDS (clk_period : integer) return integer;
g_ManufacturerID : integer := c_CERN_ID; -- 0x00080030
g_RevisionID : integer := c_RevisionID; -- 0x00000001
g_ProgramID : integer := 96; -- 0x00000060
g_base_addr : base_addr := MECHANICALLY
g_base_addr : base_addr := MECHANICALLY;
g_sdb_addr : t_wishbone_address := c_sdb_address
);
port(
-- VME signals:
......@@ -753,7 +749,8 @@ function f_latchDS (clk_period : integer) return integer;
component VME_Wb_master is
generic(
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
g_wb_addr_width : integer := c_addr_width;
g_sdb_addr : t_wishbone_address := c_sdb_address
);
port(
memReq_i : in std_logic;
......
hdl/xVME64xCore_Top.vhd
View file @ 6b9861ee
......@@ -60,7 +60,9 @@
-- loc: 0x7f CR space
g_ProgramID : integer := 90; -- 1 byte : 0x5a
-- VME base address setting
g_base_addr : base_addr := GEOGRAPHICAL_ADDR -- MECHANICALLY or , legacy
g_base_addr : base_addr := GEOGRAPHICAL_ADDR; -- MECHANICALLY or , legacy
-- SDB address
g_sdb_addr : t_wishbone_address := c_sdb_address -- 0x00300000
);
port(
clk_i : in std_logic;
......@@ -266,7 +268,8 @@ begin
g_clock => g_clock,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_cram_size => g_cram_size
g_cram_size => g_cram_size,
g_sdb_addr => c_sdb_address
)
port map(
clk_i => clk_i,
......
hdl/xvme64x_pack.vhd
View file @ 6b9861ee
......@@ -89,8 +89,10 @@ package xvme64x_pack is
end record;
--_______________________________________________________________________________
-- Constants:
--WB data width:
-- Constants:
--SDB address
constant c_sdb_address : t_wishbone_address := x"00300000";
--WB data width:
constant c_width : integer := 32; --must be 32 or 64!
--CRAM size in the CR/CSR space (bytes):
constant c_CRAM_SIZE : integer := 1024;
......@@ -455,7 +457,8 @@ function f_latchDS (clk_period : integer) return integer;
g_ManufacturerID : integer := c_CERN_ID; -- 0x00080030
g_RevisionID : integer := c_RevisionID; -- 0x00000001
g_ProgramID : integer := 96; -- 0x00000060
g_base_addr : base_addr := MECHANICALLY
g_base_addr : base_addr := MECHANICALLY;
g_sdb_addr : t_wishbone_address := c_sdb_address
);
port(
-- VME signals:
......@@ -502,7 +505,8 @@ function f_latchDS (clk_period : integer) return integer;
generic( g_clock : integer := c_clk_period;
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_cram_size : integer := c_CRAM_SIZE
g_cram_size : integer := c_CRAM_SIZE;
g_sdb_addr : t_wishbone_address := c_sdb_address
);
port(
clk_i : in std_logic;
......@@ -737,8 +741,9 @@ function f_latchDS (clk_period : integer) return integer;
component VME_Wb_master is
generic(
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
g_wb_addr_width : integer := c_addr_width;
g_family : string := "Arria II VME-WB";
g_sdb_addr : t_wishbone_address := c_sdb_address);
port(
memReq_i : in std_logic;
clk_i : in std_logic;
......
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