Adapted RT Firmware to Federico's code:

- moved to applications/wrtd/rt - removed references to LIST project, replacing with WRTD - replaced "bins" with "frac"-tional field in the WR timestamp to avoid misleading connotations with ACAM's TDC timestamp format used in the TDC mezzanine. NOTE This commit has been created by `git subtree` on the Mock Turtle repository on tag mock-turtle-2.0 This commit will not compile

Adapted RT Firmware to Federico's code:
- moved to applications/wrtd/rt - removed references to LIST project, replacing with WRTD - replaced "bins" with "frac"-tional field in the WR timestamp to avoid misleading connotations with ACAM's TDC timestamp format used in the TDC mezzanine. NOTE This commit has been created by `git subtree` on the Mock Turtle repository on tag mock-turtle-2.0 This commit will not compile
53dae492 · Tomasz Wlostowski · b3e299c0 · 53dae492 · 53dae492 · 53dae492
Commit 53dae492 authored Dec 14, 2014 by Tomasz Wlostowski
32 changed files
--- a/include/hw/mqueue.h
+++ b/include/hw/mqueue.h
+/*
+ * This work is part of the White Rabbit Node Core project.
+ *
+ * Copyright (C) 2013-2014 CERN (www.cern.ch)
+ * Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+ *
+ * Released according to the GNU GPL, version 2 or any later version.
+ */
+
+/*.
+ * White Rabbit Node Core
+ *
+ * mqueue.h: MQ register definitions (Host side)
+ */
+
+#ifndef __MQUEUE_H
+#define __MQUEUE_H
+
+// Nax number of supported incoming/outgoing slots
+#define MAX_MQUEUE_SLOTS 16
+
+// HMQ base address (wrs to the base addr of the WR Node Core)
+#define BASE_HMQ        0x00000
+
+// Global Control Registers base address, relative to BASE_HMQ (SLOT_COUNT, SLOT_STATUS, interrupt control, etc). 
+// Common for all incoming/outgoing slots in the queue
+#define MQUEUE_BASE_GCR       (0x0)
+// Incoming slot base address, relative to BASE_HMQ
+#define MQUEUE_BASE_IN(slot)  (0x4000 + (slot) * 0x400)
+// Outgoung slot base address, relative to BASE_HMQ
+#define MQUEUE_BASE_OUT(slot) (0x8000 + (slot) * 0x400)
+
+
+// MQ slot registers, relative to the base address of each slot: MQUEUE_BASE_IN(slot_no) or MQUEUE_BASE_OUT(slot_no)
+#define MQUEUE_SLOT_COMMAND 0
+// Status register
+#define MQUEUE_SLOT_STATUS 4
+// Start of data block
+#define MQUEUE_SLOT_DATA_START 8
+
+// Layout of MQUEUE_SLOT_COMMAND register:
+
+// Claim: prepares a slot to send a message (w/o)
+#define MQUEUE_CMD_CLAIM (1<<24)
+
+// Purge: erases all messages from a slot (w/o)
+#define MQUEUE_CMD_PURGE (1<<25)
+
+// Ready: pushes the message to the queue. (w/o)
+#define MQUEUE_CMD_READY (1<<26)
+
+// Discard: removes last message from the queue, advancing to the next one (w/o)
+#define MQUEUE_CMD_DISCARD (1<<27)
+
+// Size of the message to be sent, in words (w/o). Must be written together with the
+// READY command, e.g.:
+// writel (MQUEUE_CMD_READY | 10, MQUEUE_SLOT_COMMAND);
+#define MQUEUE_CMD_MSG_SIZE_MASK 0xff
+#define MQUEUE_CMD_MSG_SIZE_SHIFT 0
+
+// Layout of MQUEUE_SLOT_STATUS register:
+
+// [0] Slot is full
+#define MQUEUE_SLOT_STATUS_FULL (1<<0)
+// [1] Slot is empty
+#define MQUEUE_SLOT_STATUS_EMPTY (1<<1)
+
+// [15:8] Number of occupied entries 
+#define MQUEUE_SLOT_STATUS_OCCUPIED_SHIFT 8
+#define MQUEUE_SLOT_STATUS_OCCUPIED_MASK  0xff00
+
+// [23:16] Number of transferred words in the message currently on top of the slot
+#define MQUEUE_SLOT_STATUS_MSG_SIZE_SHIFT 16
+#define MQUEUE_SLOT_STATUS_MSG_SIZE_MASK  0xff0000
+
+// [31:28] log2(number of words in the slot).
+#define MQUEUE_SLOT_STATUS_LOG2_WIDTH_SHIFT 28
+#define MQUEUE_SLOT_STATUS_LOG2_WIDTH_MASK  0xf0000000
+
+// [7:2] log2(number of entries in the slot).
+#define MQUEUE_SLOT_STATUS_LOG2_ENTRIES_SHIFT 2
+#define MQUEUE_SLOT_STATUS_LOG2_ENTRIES_MASK  0xfc
+
+//
+// MQ Global Control Registers.Adresses relative to MQUEUE_BASE_GCR:
+//
+#define MQUEUE_GCR_INCOMING_STATUS_MASK (0x0000ffff)
+
+// Number of slots in this implementation of HMQ
+#define MQUEUE_GCR_SLOT_COUNT 0
+// EMPTY bits of all slots in a single register (for polling/IRQ status)
+#define MQUEUE_GCR_SLOT_STATUS 4
+// Interrupt mask (Outgoing: EMPTY, Incoming: not EMPTY)
+#define MQUEUE_GCR_IRQ_MASK 8
+// IRQ Coalescing register (reserved for future use)
+#define MQUEUE_GCR_IRQ_COALESCE 12
+
+// Layout of SLOT_COUNT register
+
+// [7:0] Number of Incoming slots
+#define MQUEUE_GCR_SLOT_COUNT_N_IN_SHIFT 0
+#define MQUEUE_GCR_SLOT_COUNT_N_IN_MASK 0xff
+
+// [15:8] Number of Outgoing slots
+#define MQUEUE_GCR_SLOT_COUNT_N_OUT_SHIFT 8
+#define MQUEUE_GCR_SLOT_COUNT_N_OUT_MASK 0xff00
+
+// Layout of SLOT_STATUS register
+
+// [15:0] Outgoing slots status. Each bit indicates a NOT EMPTY status of the corresponding outgoing slot
+#define MQUEUE_GCR_SLOT_STATUS_OUT_SHIFT 0
+#define MQUEUE_GCR_SLOT_STATUS_OUT_MASK 0xffff
+
+// [31:16] Incoming slots status. Each bit indicates an EMPTY status of the corresponding incoming slot
+#define MQUEUE_GCR_SLOT_STATUS_IN_SHIFT 16
+#define MQUEUE_GCR_SLOT_STATUS_IN_MASK 0xffff0000
+
+// Layout of IRQ_MASK register
+
+// [15:0] Outgoing slots status interrupt mask. Each bit enables generation of interrupt on NOT EMPTY status of the corresponding outgoing slot.
+#define MQUEUE_GCR_IRQ_MASK_OUT_SHIFT 0
+#define MQUEUE_GCR_IRQ_MASK_OUT_MASK 0xffff
+
+// [31:16] Incoming slots status interrupt mask. Each bit enables generation of interrupt on EMPTY status of the corresponding incoming slot.
+#define MQUEUE_GCR_IRQ_MASK_IN_SHIFT 16
+#define MQUEUE_GCR_IRQ_MASK_IN_MASK 0xffff0000
+
+// Layout of IRQ_COALSESCE register
+// The register is left for future IRQ coalescing support (if ever needed)
+
+#endif
--- a/include/hw/wrn_cpu_csr.h
+++ b/include/hw/wrn_cpu_csr.h
+/*
+  Register definitions for slave core: WR Node CPU Control/Status registers block
+
+  * File           : wrn_cpu_csr.h
+  * Author         : auto-generated by wbgen2 from wrn_cpu_csr.wb
+  * Created        : Wed Apr 30 14:41:11 2014
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrn_cpu_csr.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_WRN_CPU_CSR_WB
+#define __WBGEN2_REGDEFS_WRN_CPU_CSR_WB
+
+#include <stdint.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Application ID Register */
+
+/* definitions for register: CPU Reset Register */
+
+/* definitions for register: CPU Enable Register */
+
+/* definitions for register: CPU Upload Address Register */
+
+/* definitions for field: Address in reg: CPU Upload Address Register */
+#define WRN_CPU_CSR_UADDR_ADDR_MASK           WBGEN2_GEN_MASK(0, 20)
+#define WRN_CPU_CSR_UADDR_ADDR_SHIFT          0
+#define WRN_CPU_CSR_UADDR_ADDR_W(value)       WBGEN2_GEN_WRITE(value, 0, 20)
+#define WRN_CPU_CSR_UADDR_ADDR_R(reg)         WBGEN2_GEN_READ(reg, 0, 20)
+
+/* definitions for register: Core Select Register */
+
+/* definitions for register: Core Count Register */
+
+/* definitions for register: Core Memory Size */
+
+/* definitions for register: CPU Upload Data Register */
+
+/* definitions for register: CPU Debug Register */
+
+/* definitions for field: JTAG data in reg: CPU Debug Register */
+#define WRN_CPU_CSR_DEBUG_JDATA_MASK          WBGEN2_GEN_MASK(0, 8)
+#define WRN_CPU_CSR_DEBUG_JDATA_SHIFT         0
+#define WRN_CPU_CSR_DEBUG_JDATA_W(value)      WBGEN2_GEN_WRITE(value, 0, 8)
+#define WRN_CPU_CSR_DEBUG_JDATA_R(reg)        WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for field: JTAG address in reg: CPU Debug Register */
+#define WRN_CPU_CSR_DEBUG_JADDR_MASK          WBGEN2_GEN_MASK(8, 3)
+#define WRN_CPU_CSR_DEBUG_JADDR_SHIFT         8
+#define WRN_CPU_CSR_DEBUG_JADDR_W(value)      WBGEN2_GEN_WRITE(value, 8, 3)
+#define WRN_CPU_CSR_DEBUG_JADDR_R(reg)        WBGEN2_GEN_READ(reg, 8, 3)
+
+/* definitions for field: JTAG reset in reg: CPU Debug Register */
+#define WRN_CPU_CSR_DEBUG_RSTN                WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: JTAG TCK in reg: CPU Debug Register */
+#define WRN_CPU_CSR_DEBUG_TCK                 WBGEN2_GEN_MASK(17, 1)
+
+/* definitions for field: JTAG Update in reg: CPU Debug Register */
+#define WRN_CPU_CSR_DEBUG_UPDATE              WBGEN2_GEN_MASK(18, 1)
+/* [0x0]: REG Application ID Register */
+#define WRN_CPU_CSR_REG_APP_ID 0x00000000
+/* [0x4]: REG CPU Reset Register */
+#define WRN_CPU_CSR_REG_RESET 0x00000004
+/* [0x8]: REG CPU Enable Register */
+#define WRN_CPU_CSR_REG_ENABLE 0x00000008
+/* [0xc]: REG CPU Upload Address Register */
+#define WRN_CPU_CSR_REG_UADDR 0x0000000c
+/* [0x10]: REG Core Select Register */
+#define WRN_CPU_CSR_REG_CORE_SEL 0x00000010
+/* [0x14]: REG Core Count Register */
+#define WRN_CPU_CSR_REG_CORE_COUNT 0x00000014
+/* [0x18]: REG Core Memory Size */
+#define WRN_CPU_CSR_REG_CORE_MEMSIZE 0x00000018
+/* [0x1c]: REG CPU Upload Data Register */
+#define WRN_CPU_CSR_REG_UDATA 0x0000001c
+/* [0x20]: REG CPU Debug Register */
+#define WRN_CPU_CSR_REG_DEBUG 0x00000020
+#endif
--- a/include/hw/wrn_cpu_lr.h
+++ b/include/hw/wrn_cpu_lr.h
+/*
+  Register definitions for slave core: WR Node CPU Local Registers
+
+  * File           : wrn_cpu_lr.h
+  * Author         : auto-generated by wbgen2 from wrn_cpu_lr.wb
+  * Created        : Wed Apr 30 14:41:11 2014
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrn_cpu_lr.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_WRN_CPU_LR_WB
+#define __WBGEN2_REGDEFS_WRN_CPU_LR_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: CPU Polling Register */
+
+/* definitions for field: HMQ Slot Status in reg: CPU Polling Register */
+#define WRN_CPU_LR_POLL_HMQ_MASK              WBGEN2_GEN_MASK(0, 16)
+#define WRN_CPU_LR_POLL_HMQ_SHIFT             0
+#define WRN_CPU_LR_POLL_HMQ_W(value)          WBGEN2_GEN_WRITE(value, 0, 16)
+#define WRN_CPU_LR_POLL_HMQ_R(reg)            WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: RMQ Slot Status in reg: CPU Polling Register */
+#define WRN_CPU_LR_POLL_RMQ_MASK              WBGEN2_GEN_MASK(16, 16)
+#define WRN_CPU_LR_POLL_RMQ_SHIFT             16
+#define WRN_CPU_LR_POLL_RMQ_W(value)          WBGEN2_GEN_WRITE(value, 16, 16)
+#define WRN_CPU_LR_POLL_RMQ_R(reg)            WBGEN2_GEN_READ(reg, 16, 16)
+
+/* definitions for register: CPU Status Register */
+
+/* definitions for field: WR Link Up in reg: CPU Status Register */
+#define WRN_CPU_LR_STAT_WR_LINK               WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: WR Time OK in reg: CPU Status Register */
+#define WRN_CPU_LR_STAT_WR_TIME_OK            WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for register: TAI Cycles */
+
+/* definitions for register: TAI Seconds */
+
+/* definitions for register: Test */
+/* [0x0]: REG CPU Polling Register */
+#define WRN_CPU_LR_REG_POLL 0x00000000
+/* [0x4]: REG CPU Status Register */
+#define WRN_CPU_LR_REG_STAT 0x00000004
+/* [0x8]: REG TAI Cycles */
+#define WRN_CPU_LR_REG_TAI_CYCLES 0x00000008
+/* [0xc]: REG TAI Seconds */
+#define WRN_CPU_LR_REG_TAI_SEC 0x0000000c
+/* [0x10]: REG GPIO Input */
+#define WRN_CPU_LR_REG_GPIO_IN 0x00000010
+/* [0x14]: REG GPIO Set */
+#define WRN_CPU_LR_REG_GPIO_SET 0x00000014
+/* [0x18]: REG GPIO Clear */
+#define WRN_CPU_LR_REG_GPIO_CLEAR 0x00000018
+
+#endif
--- a/include/pp-printf.h
+++ b/include/pp-printf.h
+/*
+ * This work is part of the White Rabbit Node Core project.
+ *
+ * Copyright (C) 2013-2014 CERN (www.cern.ch)
+ * Author: Alessandro Rubini <rubini@gnudd.com>
+ *
+ * Released according to the GNU GPL, version 2 or any later version.
+ */
+
+#ifndef __PP_PRINTF_H
+#define __PP_PRINTF_H
+
+#include <stdarg.h>
+
+#define CONFIG_PRINT_BUFSIZE 128
+
+extern int pp_printf(const char *fmt, ...)
+        __attribute__((format(printf,1,2)));
+
+extern int pp_sprintf(char *s, const char *fmt, ...)
+        __attribute__((format(printf,2,3)));
+
+extern int pp_vprintf(const char *fmt, va_list args);
+
+extern int pp_vsprintf(char *buf, const char *, va_list)
+        __attribute__ ((format (printf, 2, 0)));
+
+/* This is what we rely on for output */
+extern int puts(const char *s);
+
+#endif
--- a/include/rt-common.h
+++ b/include/rt-common.h
+/*
+ * This work is part of the White Rabbit Node Core project.
+ *
+ * Copyright (C) 2013-2014 CERN (www.cern.ch)
+ * Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+ *
+ * Released according to the GNU GPL, version 2 or any later version.
+ */
+
+
+/*.
+ * White Rabbit Node Core
+ *
+ * rt-common.h: common WRN CPU definitions and routines
+ */
+
+#ifndef __RT_COMMON_H
+#define __RT_COMMON_H
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include "hw/wrn_cpu_lr.h"
+
+/* Dedicated Peripheral base */
+#define CPU_DP_BASE 0x200000
+
+/* CPU Local Registers base */
+#define CPU_LR_BASE 0x100000
+
+void rt_set_debug_slot(int slot);
+
+static inline uint32_t dp_readl ( uint32_t reg )
+{
+  return *(volatile uint32_t *) ( reg + CPU_DP_BASE );
+}
+
+static inline void dp_writel ( uint32_t value, uint32_t reg )
+{
+     *(volatile uint32_t *) ( reg + CPU_DP_BASE ) = value;
+}
+
+static inline uint32_t lr_readl ( uint32_t reg )
+{
+  return *(volatile uint32_t *) ( reg + CPU_LR_BASE );
+}
+
+static inline uint32_t lr_writel ( uint32_t value, uint32_t reg )
+{
+  *(volatile uint32_t *) ( reg + CPU_LR_BASE ) = value;
+}
+
+static inline void gpio_set ( int pin )
+{
+    lr_writel ( (1<<pin), WRN_CPU_LR_REG_GPIO_SET );
+}
+
+static inline void gpio_clear ( int pin )
+{
+    lr_writel ( (1<<pin), WRN_CPU_LR_REG_GPIO_CLEAR );
+}
+
+/* fixme: use Timing Unit */
+static inline void delay(int n)
+{
+    int i;
+    for(i=0;i<n;i++) asm volatile("nop");
+}
+
+#endif
--- a/include/rt-mqueue.h
+++ b/include/rt-mqueue.h
+/*
+ * This work is part of the White Rabbit Node Core project.
+ *
+ * Copyright (C) 2013-2014 CERN (www.cern.ch)
+ * Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+ *
+ * Released according to the GNU GPL, version 2 or any later version.
+ */
+
+
+/*.
+ * White Rabbit Node Core
+ *
+ * rt-mqueue.h: Message Queues definitions and functions
+ */
+
+#ifndef __RT_MQUEUE_H
+#define __RT_MQUEUE_H
+
+#define REG_LR_POLL    0x100000
+
+/* MQ Base addresses */
+#define HMQ_BASE           0x40010000
+#define RMQ_BASE           0x40020000
+
+/* MQ Slot offsets */
+#define MQ_GCR       (0x0)
+#define MQ_IN(slot)  (0x4000 + (slot) * 0x400)
+#define MQ_OUT(slot) (0x8000 + (slot) * 0x400)
+
+/* MQ Commands */
+#define MQ_CMD_CLAIM (1 << 24)
+#define MQ_CMD_PURGE (1 << 25)
+#define MQ_CMD_READY (1 << 26)
+#define MQ_CMD_DISCARD (1 << 27)
+
+/* MQ Registers */
+#define MQ_SLOT_COMMAND 0
+#define MQ_SLOT_STATUS 4
+#define MQ_SLOT_DATA_START 8
+
+struct rmq_message_addr {
+    uint32_t target_ip;
+    uint32_t target_port;
+    uint32_t target_offset;
+};
+
+static inline void mq_writel( int remote, uint32_t val, uint32_t reg )
+{
+  if(remote)
+    * (volatile uint32_t * ) (RMQ_BASE + reg) = val ;
+  else
+    * (volatile uint32_t * ) (HMQ_BASE + reg) = val ;
+}
+
+static inline void mq_claim (int remote, int slot)
+{
+  mq_writel ( remote, MQ_CMD_CLAIM, MQ_OUT(slot) + MQ_SLOT_COMMAND );
+}
+
+static inline void mq_send( int remote, int slot, int count)
+{
+  mq_writel ( remote, MQ_CMD_READY | count, MQ_OUT(slot) + MQ_SLOT_COMMAND );
+}
+
+static inline void mq_discard (int remote, int slot)
+{
+  mq_writel ( remote, MQ_CMD_DISCARD, MQ_IN(slot) );
+}
+
+static void *mq_map_out_buffer(int remote, int slot)
+{
+  uint32_t base = remote ? RMQ_BASE : HMQ_BASE;
+  return (void *) (base + MQ_OUT (slot) + MQ_SLOT_DATA_START );
+}
+
+static void *mq_map_in_buffer(int remote, int slot)
+{
+  uint32_t base = remote ? RMQ_BASE : HMQ_BASE;
+  return (void *) (base + MQ_IN (slot) + MQ_SLOT_DATA_START );
+}
+
+static inline uint32_t mq_poll()
+{
+  return *(volatile uint32_t *) ( REG_LR_POLL );
+}
+
+static inline uint32_t rmq_poll(int slot)
+{
+  return *(volatile uint32_t *) ( REG_LR_POLL ) & ( 1<< (16 + slot ));
+}
+
+#endif
--- a/include/rt-smem.h
+++ b/include/rt-smem.h
+/*
+ * This work is part of the White Rabbit Node Core project.
+ *
+ * Copyright (C) 2013-2014 CERN (www.cern.ch)
+ * Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+ *
+ * Released according to the GNU GPL, version 2 or any later version.
+ */
+
+/*.
+ * White Rabbit Node Core
+ *
+ * rt-smem.h: Shared Memory definitions & API
+ */
+
+#ifndef __WRNODE_SMEM_H
+#define __WRNODE_SMEM_H
+
+#define SMEM_RANGE_ADD 0x2000
+#define SMEM_RANGE_SUB 0x4000
+#define SMEM_RANGE_SET 0x6000
+#define SMEM_RANGE_CLEAR 0x8000
+#define SMEM_RANGE_FLIP 0xa000
+
+#define SMEM __attribute__((section(".smem")))
+
+static inline void smem_atomic_add(int *p, int x)
+{
+  *(volatile int *)(p + (SMEM_RANGE_ADD >> 2)) = x;
+}
+
+static inline void smem_atomic_sub(int *p, int x)
+{
+  *(volatile int *)(p + (SMEM_RANGE_SUB >> 2)) = x;
+}
+
+#endif
--- a/include/rt.h
+++ b/include/rt.h
+/*
+ * This work is part of the White Rabbit Node Core project.
+ *
+ * Copyright (C) 2013-2014 CERN (www.cern.ch)
+ * Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+ *
+ * Released according to the GNU GPL, version 2 or any later version.
+ */
+
+
+/*.
+ * White Rabbit Node Core
+ *
+ * rt.h: all common stuff in a single header
+ */
+
+#ifndef __WRN_RT_H
+#define __WRN_RT_H
+
+#include <stdint.h>
+
+#include "rt-mqueue.h"
+#include "rt-common.h"
+#include "rt-smem.h"
+
+#include "pp-printf.h"
+
+#endif
+
+
+
--- a/common/wrtd-common.h
+++ b/common/wrtd-common.h
@@ -10,8 +10,9 @@
 #ifndef __WRTD_COMMON_H
 #define __WRTD_COMMON_H

-#define WRTD_CPU_TDC 0
-#define WRTD_CPU_FD 1
+/* WR Node CPU Core indices */
+#define WRTD_CPU_TDC 0			/* Core 0 controls the TDC mezzanine */
+#define WRTD_CPU_FD 1			/* Core 0 controls the FD mezzanine */

 #define WRTD_IN_MAX		2
 #define WRTD_IN_TDC_CONTROL	0
@@ -23,6 +24,14 @@
 #define WRTD_OUT_TDC_LOGGING	2
 #define WRTD_OUT_FD_LOGGING	3

+
+#define WRTD_REMOTE_IN_MAX	1
+#define WRTD_REMOTE_IN_FD	0
+
+#define WRTD_REMOTE_OUT_MAX	1
+#define WRTD_REMOTE_OUT_TDC	0
+
+
 /* Command and log message IDs */
 #define WRTD_LOG_RAW_INPUT	  	 0x1
 #define WRTD_LOG_SENT_TRIGGER 	 0x2
@@ -126,7 +135,7 @@ enum wrtd_log_level {
 struct wr_timestamp {
 	uint64_t seconds;
 	uint64_t ticks;
-	uint64_t bins;
+	uint64_t frac;
 };

 struct wrtd_trig_id {
@@ -169,14 +178,14 @@ static inline void ts_add(struct wr_timestamp *a, const struct wr_timestamp *b)
    if(a->frac >= 4096)
    {
    	a->frac -= 4096;
-    	a->cycles ++;
+    	a->ticks ++;
    }

-    a->cycles += b->cycles;
+    a->ticks += b->ticks;

-    if(a->cycles >= 125000000)
+    if(a->ticks >= 125000000)
    {
-    	a->cycles -= 125000000;
+    	a->ticks -= 125000000;
    	a->seconds++;
    }

@@ -190,14 +199,14 @@ static inline void ts_sub(struct wr_timestamp *a, const struct wr_timestamp *b)
    if(a->frac < 0)
    {
    	a->frac += 4096;
-    	a->cycles --;
+    	a->ticks --;
    }

-    a->cycles -= b->cycles;
+    a->ticks -= b->ticks;

-    if(a->cycles < 0)
+    if(a->ticks < 0)
    {
-    	a->cycles += 125000000;
+    	a->ticks += 125000000;
    	a->seconds--;
    }

@@ -206,7 +215,7 @@ static inline void ts_sub(struct wr_timestamp *a, const struct wr_timestamp *b)
    if(a->seconds == -1)
    {
      a->seconds = 0;
-      a->cycles -= 125000000;
+      a->ticks -= 125000000;
    }
 }
 #endif

--- a/lib/Makefile
+++ b/lib/Makefile
@@ -12,7 +12,7 @@ LOBJ += libwrtd-input.o
 LOBJ += libwrtd-output.o
 LOBJ += $(WRNC)/lib/libwrnc.o

-CFLAGS += -Wall -ggdb -O2 -I. -I../common -I$(WRNC)/lib -I$(WRNC)/kernel $(EXTRACFLAGS)
+CFLAGS += -Wall -ggdb -O2 -I. -I../include -I$(WRNC)/lib -I$(WRNC)/kernel $(EXTRACFLAGS)
 LDLIBS += -L. -lwrtd



--- a/lib/libwrtd-input.c
+++ b/lib/libwrtd-input.c
@@ -92,7 +92,7 @@ int wrtd_in_state_get(struct wrtd_node *dev, unsigned int input,
 	state->tagged_pulses = msg.data[18];
 	state->sent_triggers = msg.data[19];
 	state->dead_time.seconds = 0;
-	state->dead_time.bins = 0;
+	state->dead_time.frac = 0;
 	state->dead_time.ticks = msg.data[20] * 2;

 	state->assigned_id.system = msg.data[3];
@@ -400,7 +400,7 @@ int wrtd_in_delay_set(struct wrtd_node *dev, unsigned int input,
 	msg.data[2] = input;
 	msg.data[3] = t.seconds;
 	msg.data[4] = t.ticks;
-	msg.data[5] = t.bins;
+	msg.data[5] = t.frac;

 	/* Send the message and get answer */
 	err = wrtd_in_send_and_receive_sync(wrtd, &msg);
@@ -440,7 +440,7 @@ int wrtd_in_timebase_offset_set(struct wrtd_node *dev, unsigned int input,
 	msg.data[2] = input;
 	msg.data[3] = t.seconds;
 	msg.data[4] = t.ticks;
-	msg.data[5] = t.bins;
+	msg.data[5] = t.frac;

 	/* Send the message and get answer */
 	err = wrtd_in_send_and_receive_sync(wrtd, &msg);
@@ -554,7 +554,7 @@ int wrtd_in_read_log(struct wrtd_node *dev, struct wrtd_log_entry *log,
    			cur->id.trigger = msg->data[5];
    			cur->ts.seconds = msg->data[6];
    			cur->ts.ticks = msg->data[7];
-    			cur->ts.bins = msg->data[8];
+    			cur->ts.frac = msg->data[8];

    			remaining--;
 			n_read++;

--- a/lib/libwrtd-internal.c
+++ b/lib/libwrtd-internal.c
@@ -40,7 +40,7 @@ struct wr_timestamp picos_to_ts(uint64_t p)
 	p %= (1000ULL * 1000ULL * 1000ULL * 1000ULL);
 	t.ticks = p / 8000;
 	p %= 8000;
-	t.bins = p * 4096 / 8000;
+	t.frac = p * 4096 / 8000;

 	return t;
 }
@@ -57,5 +57,5 @@ void unbag_ts(uint32_t *buf, int offset, struct wr_timestamp *ts)
 {
    ts->seconds = buf[offset];
    ts->ticks = buf[offset + 1];
-    ts->bins = buf[offset + 2];
+    ts->frac = buf[offset + 2];
 }
--- a/lib/libwrtd-output.c
+++ b/lib/libwrtd-output.c
@@ -90,7 +90,7 @@ static int wrtd_out_trig_get(struct wrtd_node *dev, unsigned int output,
 	trigger->trigger.trigger = msg.data[5];
 	trigger->delay_trig.seconds = 0;
 	trigger->delay_trig.ticks = msg.data[6];
-	trigger->delay_trig.bins = msg.data[7];
+	trigger->delay_trig.frac = msg.data[7];
 	trigger->is_conditional = 0;
 	trigger->worst_latency_us = (msg.data[17] + 124) / 125;

@@ -101,7 +101,7 @@ static int wrtd_out_trig_get(struct wrtd_node *dev, unsigned int output,
 		trigger->condition.trigger = msg.data[13];
 		trigger->delay_cond.seconds = 0;
 		trigger->delay_cond.ticks = msg.data[14];
-		trigger->delay_cond.bins = msg.data[15];
+		trigger->delay_cond.frac = msg.data[15];
 	}

 	trigger->enabled = (state & HASH_ENT_DISABLED) ? 0 : 1;
@@ -380,7 +380,7 @@ int wrtd_out_trig_delay_set(struct wrtd_node *dev,
 	msg.data[2] = handle->channel;
 	msg.data[3] = handle->ptr_trig;
 	msg.data[4] = t.ticks;
-	msg.data[5] = t.bins;
+	msg.data[5] = t.frac;

 	/* Send the message and get answer */
 	err = wrtd_out_send_and_receive_sync(wrtd, &msg);

--- a/rt/common/loop-queue.c
+++ b/rt/common/loop-queue.c
+#include "rt.h"
+#include "wrtd-common.h"
+
+#define LOOP_QUEUE_SIZE 16
+
+static SMEM int head, tail, count;
+static SMEM struct wrtd_trigger_entry buf[16];
+
+void loop_queue_init()
+{
+    head = tail = count = 0;
+}
+
+void loop_queue_push(struct wrtd_trig_id *id, uint32_t seq, struct wr_timestamp *ts)
+{
+    if(count == LOOP_QUEUE_SIZE)
+	return;
+	
+    buf[head].id = *id;
+    buf[head].seq = seq;
+    buf[head].ts = *ts;
+    
+    head++;
+    
+    if(head == LOOP_QUEUE_SIZE)
+	head = 0;
+    count++;
+}
+
+struct wrtd_trigger_entry *loop_queue_pop()
+{
+    if(!count)
+        return NULL;
+    
+    struct wrtd_trigger_entry *rv = &buf[tail];
+    
+    tail++;
+    if(tail == LOOP_QUEUE_SIZE)
+	tail = 0;
+    count--;
+    
+    return rv;
+}
\ No newline at end of file
--- a/rt/common/loop-queue.h
+++ b/rt/common/loop-queue.h
+#ifndef __LOOP_QUEUE_H
+#define __LOOP_QUEUE_H
+
+#include "rt.h"
+#include "wrtd-common.h"
+
+#define LOOP_QUEUE_SIZE 16
+
+void loop_queue_init();
+void loop_queue_push(struct wrtd_trig_id *id, uint32_t seq, struct wr_timestamp *ts);
+struct wrtd_trigger_entry *loop_queue_pop();
+
+#endif
+
--- a/rt/common/printf.c
+++ b/rt/common/printf.c
+/*
+ * Basic printf based on vprintf based on vsprintf
+ *
+ * Alessandro Rubini for CERN, 2011 -- public domain
+ * (please note that the vsprintf is not public domain but GPL)
+ */
+#include <stdarg.h>
+#include <pp-printf.h>
+
+static char print_buf[CONFIG_PRINT_BUFSIZE];
+
+int pp_vprintf(const char *fmt, va_list args)
+{
+	int ret;
+
+	ret = pp_vsprintf(print_buf, fmt, args);
+	puts(print_buf);
+	return ret;
+}
+
+int pp_sprintf(char *s, const char *fmt, ...)
+{
+	va_list args;
+	int ret;
+
+	va_start(args, fmt);
+	ret = pp_vsprintf(s, fmt, args);
+	va_end(args);
+	return ret;
+}
+
+
+int pp_printf(const char *fmt, ...)
+{
+	va_list args;
+	int ret;
+
+	va_start(args, fmt);
+	ret = pp_vprintf(fmt, args);
+	va_end(args);
+
+	return ret;
+}
--- a/rt/common/rt-common.c
+++ b/rt/common/rt-common.c
+/*
+ * This work is part of the White Rabbit Node Core project.
+ *
+ * Copyright (C) 2013-2014 CERN (www.cern.ch)
+ * Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+ *
+ * Released according to the GNU GPL, version 2 or any later version.
+ */
+
+/*.
+ * White Rabbit Node Core
+ *
+ * rt-common.c: common RT CPU functions
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+
+#include "rt-mqueue.h"
+#include "rt-common.h"
+
+static int debug_slot;
+
+void rt_set_debug_slot(int slot)
+{
+    debug_slot = slot;
+}
+
+int puts(const char *p)
+{
+    int i;
+    volatile uint32_t *buf = mq_map_out_buffer(0, debug_slot);
+    
+    mq_claim(0, debug_slot);
+    
+    buf[0] = 0xdeadbeef;
+    for(i=0;i<127;i++,p++)
+      {
+  	   if(*p)
+	       buf[i+1] = *p;
+	     else
+	       break;
+      }
+
+    mq_send(0, debug_slot, i + 1);
+    return i;
+}
+
--- a/rt/common/vsprintf-xint.c
+++ b/rt/common/vsprintf-xint.c
+/*
+ *  vsprintf-xint: a possible free-software replacement for mprintf
+ *
+ *  public domain
+ */
+#include <stdarg.h>
+#include <stdint.h>
+
+static const char hex[] = "0123456789abcdef";
+
+static int number(char *out, unsigned value, int base, int lead, int wid)
+{
+	char tmp[16];
+	int i = 16, ret, negative = 0;
+
+	/* No error checking at all: it is as ugly as possible */
+	if ((signed)value < 0 && base == 10) {
+		negative = 1;
+		value = -value;
+	}
+	while (value && i) {
+		tmp[--i] = hex[value % base];
+		value /= base;
+	}
+	if (i == 16)
+		tmp[--i] = '0';
+	if (negative && lead == ' ') {
+		tmp[--i] = '-';
+		negative = 0;
+	}
+	while (i > 16 - wid + negative)
+		tmp[--i] = lead;
+	if (negative)
+		tmp[--i] = '-';
+	ret = 16 - i;
+	while (i < 16)
+		*(out++) = tmp[i++];
+	return ret;
+}
+
+int pp_vsprintf(char *buf, const char *fmt, va_list args)
+{
+	char *s, *str = buf;
+	int base, lead, wid;
+
+	for (; *fmt ; ++fmt) {
+		if (*fmt != '%') {
+			*str++ = *fmt;
+			continue;
+		}
+
+		base = 10;
+		lead = ' ';
+		wid = 1;
+	repeat:
+		fmt++;		/* Skip '%' initially, other stuff later */
+		switch(*fmt) {
+		case '\0':
+			goto ret;
+		case '0':
+			lead = '0';
+			goto repeat;
+
+		case '*':
+			/* should be precision, just eat it */
+			base = va_arg(args, int);
+			/* fall through: discard unknown stuff */
+		default:
+			if (*fmt >= '1' && *fmt <= '9')
+				wid = *fmt - '0';
+			goto repeat;
+
+			/* Special cases for conversions */
+
+		case 'c': /* char: supported */
+			*str++ = (unsigned char) va_arg(args, int);
+			break;
+		case 's': /* string: supported */
+			s = va_arg(args, char *);
+			while (*s)
+				*str++ = *s++;
+			break;
+		case 'n': /* number-thus-far: not supported */
+			break;
+		case '%': /* supported */
+			*str++ = '%';
+			break;
+
+			/* integers are more or less printed */
+		case 'p':
+		case 'x':
+		case 'X':
+			base = 16;
+		case 'o':
+			if (base == 10) /* yet unchaged */
+				base = 8;
+		case 'd':
+		case 'i':
+		case 'u':
+			str += number(str, va_arg(args, int), base, lead, wid);
+			break;
+		}
+	}
+ ret:
+	*str = '\0';
+	return str - buf;
+
+
+}
--- a/rt/common/wrn-crt0.S
+++ b/rt/common/wrn-crt0.S
+/****************************************************************************
+**
+**  Name: crt0ram.S
+**
+**  Description:
+**        Implements boot-code that calls LatticeDDInit (that calls main())
+**        Implements exception handlers (actually, redirectors)
+**
+**  $Revision: $
+**
+** Disclaimer:
+**
+**   This source code is intended as a design reference which
+**   illustrates how these types of functions can be implemented.  It
+**   is the user's responsibility to verify their design for
+**   consistency and functionality through the use of formal
+**   verification methods.  Lattice Semiconductor provides no warranty
+**   regarding the use or functionality of this code.
+**
+** --------------------------------------------------------------------
+**
+**                     Lattice Semiconductor Corporation
+**                     5555 NE Moore Court
+**                     Hillsboro, OR 97214
+**                     U.S.A
+**
+**                     TEL: 1-800-Lattice (USA and Canada)
+**                          (503)268-8001 (other locations)
+**
+**                     web:   http://www.latticesemi.com
+**                     email: techsupport@latticesemi.com
+**
+** --------------------------------------------------------------------------
+**
+**  Change History (Latest changes on top)
+**
+**  Ver    Date        Description
+** --------------------------------------------------------------------------
+**  3.8   Apr-15-2011  Added __MICO_USER_<handler>_HANDLER__ preprocessor to 
+**                     allow customers to implement their own handlers for:
+**                     DATA_ABORT, INST_ABORT
+**  
+**  3.1   Jun-18-2008  Added __MICO_NO_INTERRUPTS__ preprocessor
+**                     option to exclude invoking MicoISRHandler
+**                     to reduce code-size in apps that don't use
+**                     interrupts
+**
+**  3.0   Mar-25-2008  Added Header
+**
+**---------------------------------------------------------------------------
+*****************************************************************************/
+
+/*
+ * LatticeMico32 C startup code.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/* From include/sys/signal.h */  
+#define SIGINT  2   /* interrupt */
+#define SIGTRAP 5   /* trace trap */
+#define SIGFPE  8   /* arithmetic exception */
+#define SIGSEGV 11  /* segmentation violation */
+
+//#define MICO32_FULL_CONTEXT_SAVE_RESTORE
+
+
+/* Exception handlers - Must be 32 bytes long. */
+        .section    .boot, "ax", @progbits
+	
+        .global	_start  
+_start: 
+	   
+        .global _reset_handler
+        .type 	_reset_handler, @function
+_reset_handler:
+    xor r0, r0, r0
+    wcsr    IE, r0
+    wcsr    IM, r0
+    mvhi    r1, hi(_reset_handler)
+    ori     r1, r1, lo(_reset_handler)
+    wcsr    EBA, r1
+    calli   _crt0
+    nop
+        .size	_reset_handler, .-_reset_handler
+	
+.extern _irq_entry
+.org 0xc0
+        .global _interrupt_handler
+        .type 	_interrupt_handler, @function
+_interrupt_handler:
+		nop
+		
+.org 0x100
+        .global _crt0
+        .type 	_crt0, @function
+_crt0:
+    /* Clear r0 */
+    xor     r0, r0, r0
+    xor     r1, r1, r1
+    xor     r2, r2, r2
+    xor     r3, r3, r3
+
+    /* Setup stack and global pointer */
+    mvhi    sp, hi(_fstack)
+    ori     sp, sp, lo(_fstack)
+    mvhi    gp, hi(_gp)
+    ori     gp, gp, lo(_gp)
+	
+    mvhi    r1, hi(_fbss)
+    ori     r1, r1, lo(_fbss)
+    mvi     r2, 0
+    mvhi    r3, hi(_ebss)
+    ori     r3, r3, lo(_ebss)
+    sub     r3, r3, r1
+/*    calli   memset */
+    mvi     r1, 0
+    mvi     r2, 0
+    mvi     r3, 0
+    calli   main
+
+loopf:
+	bi loopf
+
+
--- a/rt/common/wrnode.ld
+++ b/rt/common/wrnode.ld
+OUTPUT_FORMAT("elf32-lm32")
+ENTRY(_start)
+MEMORY
+{
+    ram :
+ ORIGIN = 0x00000000,
+ LENGTH = 32768 - 2048
+    stack :
+ ORIGIN = 32768 - 2048,
+ LENGTH = 2048
+    smem :
+ ORIGIN = 0x40000000,
+ LENGTH = 8192
+}
+
+SECTIONS
+{
+ .boot : { *(.boot) } > ram
+ .text : { *(.text .text.*) } > ram =0
+ .rodata : { *(.rodata .rodata.*) } > ram
+ .data : {
+  *(.data .data.*)
+  _gp = ALIGN(16) + 0x7ff0;
+ } > ram
+ .bss : {
+  _fbss = .;
+  *(.bss .bss.*)
+  *(COMMON)
+  _ebss = .;
+ } > ram
+
+ .smem : { *(.smem) } > smem
+
+ PROVIDE(_endram = ORIGIN(stack));
+ PROVIDE(_fstack = ORIGIN(stack) + LENGTH(stack) - 4);
+}
+PROVIDE(mprintf = pp_printf);
--- a/rt/common/wrnode.mk
+++ b/rt/common/wrnode.mk
+# and don't touch the rest unless you know what you're doing.
+CROSS_COMPILE ?= lm32-elf-
+INSTALL_PREFIX ?= .
+
+CC =		$(CROSS_COMPILE)gcc
+LD =		$(CROSS_COMPILE)ld
+OBJDUMP =	$(CROSS_COMPILE)objdump
+OBJCOPY =	$(CROSS_COMPILE)objcopy
+SIZE =		$(CROSS_COMPILE)size
+
+CFLAGS = -DWRNODE_RT -g -O3 -I. -I../common -I../../include -mmultiply-enabled -mbarrel-shift-enabled
+OBJS += ../common/wrn-crt0.o ../common/vsprintf-xint.o ../common/printf.o ../common/rt-common.o ../common/loop-queue.o
+LDSCRIPT = ../common/wrnode.ld
+
+all:	$(OUTPUT)
+
+$(OUTPUT): $(LDSCRIPT) $(OBJS)
+	${CC} -o $(OUTPUT).elf -nostartfiles $(OBJS) -T $(LDSCRIPT) -lgcc -lc
+	${OBJCOPY} --remove-section .smem -O binary $(OUTPUT).elf $(OUTPUT).bin
+	${OBJDUMP} -S $(OUTPUT).elf  > disasm.S
+	$(SIZE) $(OUTPUT).elf
+
+clean:
+	rm -f $(OBJS) $(OUTPUT).bin
+	
+install:
+	cp $(OUTPUT).bin $(INSTALL_PREFIX)
\ No newline at end of file
--- a/rt/fd/Makefile
+++ b/rt/fd/Makefile
+OBJS = rt-fd.o hash.o
+OUTPUT = rt-fd
+
+include ../common/wrnode.mk
--- a/rt/fd/hash.c
+++ b/rt/fd/hash.c
+/*
+ * This work is part of the White Rabbit Node Core project.
+ *
+ * Copyright (C) 2013-2014 CERN (www.cern.ch)
+ * Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+ *
+ * Released according to the GNU GPL, version 2 or any later version.
+ */
+
+
+/*.
+ * LHC Instability Trigger Distribution (LIST) Firmware.
+ *
+ * hash.c: Trigger Output hash table implementation
+ */
+
+#include <string.h>
+
+#include "hash.h"
+
+/* constant sized block memory pool, providing constant time allocation and freeing */
+struct blockpool {
+    int blk_size;
+    int blk_count;
+    uint16_t *fq;
+    int fq_head, fq_tail, fq_count;
+    void *pool;
+};
+
+static uint32_t hash_pool_mem [ FD_HASH_ENTRIES * sizeof(struct lrt_hash_entry) / 4 ];
+static uint16_t hash_pool_queue [ FD_HASH_ENTRIES +1 ];
+static struct blockpool hash_blockpool;
+
+struct lrt_hash_entry* htab [ FD_HASH_ENTRIES ];
+
+void blockpool_init( struct blockpool *bp, int blk_size, int blk_count, void *data, void *queue )
+{
+    int i;
+
+    bp->pool = data;
+    bp->fq = queue;
+    bp->blk_count = blk_count;
+    bp->blk_size = blk_size;
+    bp->fq_head = blk_count;
+    bp->fq_tail = 0;
+    bp->fq_count = blk_count;
+
+    for(i=0;i<bp->blk_count;i++)
+	bp->fq[i] = i;
+}
+
+void *blockpool_alloc( struct  blockpool *bp )
+{
+    if(bp->fq_head == bp->fq_tail)
+    {
+	return NULL;
+    }
+
+    void *blk = bp->pool + bp->blk_size * (int)bp->fq[bp->fq_tail];
+    if(bp->fq_tail == bp->blk_count)
+	bp->fq_tail = 0;
+    else
+	bp->fq_tail++;
+
+    bp->fq_count--;
+
+    
+
+    return blk;
+}
+
+void blockpool_free( struct blockpool *bp, void *ptr )
+{
+    int blk_id = (ptr - bp->pool) / bp->blk_size;
+    bp->fq[bp->fq_head] = blk_id;
+
+    if(bp->fq_head == bp->blk_count)
+	bp->fq_head = 0;
+    else
+	bp->fq_head++;
+    bp->fq_count++;
+}
+
+
+void hash_init()
+{
+    blockpool_init(&hash_blockpool, sizeof(struct lrt_hash_entry), FD_HASH_ENTRIES, hash_pool_mem, hash_pool_queue);
+    memset(&htab, 0, sizeof(htab) );
+}
+
+struct lrt_hash_entry *hash_alloc( int pos )
+{
+    struct lrt_hash_entry *prev = NULL, *current = htab[pos];
+    
+    while(current)
+    {
+	prev = current;
+	current = current->next;
+    }
+	
+    current = blockpool_alloc(&hash_blockpool);
+
+    if(!prev)
+        htab[pos] = current;
+    else
+       	prev->next = current;
+
+    current->next = NULL;
+    return current;
+}
+
+struct lrt_hash_entry *hash_add ( struct wrtd_trig_id *id, int output, struct lrt_output_rule *rule )
+{
+    int pos;
+    struct lrt_hash_entry *ent = hash_search( id, &pos );
+
+    if(!ent)
+	   ent = hash_alloc( pos );
+
+    if(!ent)
+       return NULL;
+
+    rule->worst_latency = 0;
+
+    ent->id = *id;
+    ent->ocfg[output] = *rule;
+    return ent;
+}
+
+int hash_remove ( struct lrt_hash_entry *ent, int output )
+{
+    int pos, i;
+    ent->ocfg[output].state = HASH_ENT_EMPTY;
+
+    for(i = 0; i < FD_NUM_CHANNELS; i++)
+        if(ent->ocfg[i].state != HASH_ENT_EMPTY) // the same ID is assigned to another output
+            return 0;
+
+    if (ent == htab[pos])
+        htab[pos] = ent->next;
+    else {
+        struct lrt_hash_entry *tmp = htab[pos]->next;
+        htab[pos]->next = ent->next;
+        ent->next = tmp;
+    }
+
+    blockpool_free(&hash_blockpool, ent);
+    return 0;
+}
+
+struct lrt_hash_entry *hash_get_entry (int bucket, int pos)
+{
+    int i;
+    if(bucket < 0 || bucket >= FD_HASH_ENTRIES)
+	return NULL;
+
+    struct lrt_hash_entry *l = htab[bucket];
+
+    for(i = 0; l != NULL && i < pos; i++, l=l->next)
+	if(!l)
+	    return NULL;
+
+    return l;
+}
+
+int hash_free_count()
+{
+    return hash_blockpool.fq_count;
+}
--- a/rt/fd/hash.h
+++ b/rt/fd/hash.h
+/*
+ * This work is part of the White Rabbit Node Core project.
+ *
+ * Copyright (C) 2013-2014 CERN (www.cern.ch)
+ * Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+ *
+ * Released according to the GNU GPL, version 2 or any later version.
+ */
+
+
+/* 
+ * LHC Instability Trigger Distribution (LIST) Firmware 
+ *
+ * hash.h: Trigger Output hash table
+ */
+
+#ifndef __LIST_HASH_H
+#define __LIST_HASH_H
+
+#include "rt.h"
+#include "wrtd-common.h"
+
+struct lrt_output_rule {
+    uint32_t delay_cycles;
+    uint16_t delay_frac;
+    uint16_t state;
+    struct lrt_output_rule *cond_ptr;
+    int worst_latency;
+};
+
+
+struct lrt_hash_entry {
+    struct wrtd_trig_id id;					
+    struct lrt_output_rule ocfg [FD_NUM_CHANNELS];	
+    struct lrt_hash_entry *next;			
+};
+
+extern struct lrt_hash_entry* htab [ FD_HASH_ENTRIES ];
+
+void hash_init();
+struct lrt_hash_entry *hash_add ( struct wrtd_trig_id *id, int output, struct lrt_output_rule *rule );
+int hash_remove ( struct lrt_hash_entry *ent, int output );
+int hash_free_count();
+struct lrt_hash_entry *hash_get_entry (int bucket, int pos);
+
+static inline int hash_func( struct wrtd_trig_id *id )
+{
+    int h = 0;
+    h += id->system * 10291;
+    h += id->source_port * 10017;
+    h += id->trigger * 3111;
+    return h & (FD_HASH_ENTRIES - 1); // hash table size must be a power of 2
+}
+
+static inline struct lrt_hash_entry *hash_search( struct wrtd_trig_id *id, int *pos )
+{
+    int p = hash_func( id );
+
+    struct lrt_hash_entry *ent = htab[ p ];
+    if(pos)
+        *pos = p;
+    
+    
+    while (ent)
+    {
+        if(ent->id.system == id->system &&
+       ent->id.source_port == id->source_port &&
+           ent->id.trigger == id->trigger)
+            return ent;
+    
+    ent = ent->next;
+    }
+    return NULL;
+};
+
+#endif
+
--- a/rt/fd/hw/fd_channel_regs.h
+++ b/rt/fd/hw/fd_channel_regs.h
+/*
+  Register definitions for slave core: Fine Delay Channel WB Slave
+
+  * File           : fd_channel_regs.h
+  * Author         : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
+  * Created        : Fri Feb 15 12:07:17 2013
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_FD_CHANNEL_WISHBONE_SLAVE_WB
+#define __WBGEN2_REGDEFS_FD_CHANNEL_WISHBONE_SLAVE_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Delay Control Register */
+
+/* definitions for field: Enable channel in reg: Delay Control Register */
+#define FD_DCR_ENABLE                         WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: Delay mode select in reg: Delay Control Register */
+#define FD_DCR_MODE                           WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for field: Pulse generator arm in reg: Delay Control Register */
+#define FD_DCR_PG_ARM                         WBGEN2_GEN_MASK(2, 1)
+
+/* definitions for field: Pulse generator triggered in reg: Delay Control Register */
+#define FD_DCR_PG_TRIG                        WBGEN2_GEN_MASK(3, 1)
+
+/* definitions for field: Start Delay Update in reg: Delay Control Register */
+#define FD_DCR_UPDATE                         WBGEN2_GEN_MASK(4, 1)
+
+/* definitions for field: Delay Update Done in reg: Delay Control Register */
+#define FD_DCR_UPD_DONE                       WBGEN2_GEN_MASK(5, 1)
+
+/* definitions for field: Force Calibration Delay in reg: Delay Control Register */
+#define FD_DCR_FORCE_DLY                      WBGEN2_GEN_MASK(6, 1)
+
+/* definitions for field: Disable Fine Part update in reg: Delay Control Register */
+#define FD_DCR_NO_FINE                        WBGEN2_GEN_MASK(7, 1)
+
+/* definitions for field: Force Output High in reg: Delay Control Register */
+#define FD_DCR_FORCE_HI                       WBGEN2_GEN_MASK(8, 1)
+
+/* definitions for register: Fine Range Register */
+
+/* definitions for register: Pulse start time / offset (MSB TAI seconds) */
+
+/* definitions for register: Pulse start time / offset (LSB TAI seconds) */
+
+/* definitions for register: Pulse start time / offset (8 ns cycles) */
+
+/* definitions for register: Pulse start time / offset (sub-cycle fine part) */
+
+/* definitions for register: Pulse end time / offset (MSB TAI seconds) */
+
+/* definitions for register: Pulse end time / offset (LSB TAI seconds) */
+
+/* definitions for register: Pulse end time / offset (8 ns cycles) */
+
+/* definitions for register: Pulse end time / offset (sub-cycle fine part) */
+
+/* definitions for register: Pulse spacing (TAI seconds) */
+
+/* definitions for register: Pulse spacing (8 ns cycles) */
+
+/* definitions for register: Pulse spacing (sub-cycle fine part) */
+
+/* definitions for register: Repeat Count Register */
+
+/* definitions for field: Repeat Count in reg: Repeat Count Register */
+#define FD_RCR_REP_CNT_MASK                   WBGEN2_GEN_MASK(0, 16)
+#define FD_RCR_REP_CNT_SHIFT                  0
+#define FD_RCR_REP_CNT_W(value)               WBGEN2_GEN_WRITE(value, 0, 16)
+#define FD_RCR_REP_CNT_R(reg)                 WBGEN2_GEN_READ(reg, 0, 16)
+
+/* definitions for field: Continuous Waveform Mode in reg: Repeat Count Register */
+#define FD_RCR_CONT                           WBGEN2_GEN_MASK(16, 1)
+/* [0x0]: REG Delay Control Register */
+#define FD_REG_DCR 0x00000000
+/* [0x4]: REG Fine Range Register */
+#define FD_REG_FRR 0x00000004
+/* [0x8]: REG Pulse start time / offset (MSB TAI seconds) */
+#define FD_REG_U_STARTH 0x00000008
+/* [0xc]: REG Pulse start time / offset (LSB TAI seconds) */
+#define FD_REG_U_STARTL 0x0000000c
+/* [0x10]: REG Pulse start time / offset (8 ns cycles) */
+#define FD_REG_C_START 0x00000010
+/* [0x14]: REG Pulse start time / offset (sub-cycle fine part) */
+#define FD_REG_F_START 0x00000014
+/* [0x18]: REG Pulse end time / offset (MSB TAI seconds) */
+#define FD_REG_U_ENDH 0x00000018
+/* [0x1c]: REG Pulse end time / offset (LSB TAI seconds) */
+#define FD_REG_U_ENDL 0x0000001c
+/* [0x20]: REG Pulse end time / offset (8 ns cycles) */
+#define FD_REG_C_END 0x00000020
+/* [0x24]: REG Pulse end time / offset (sub-cycle fine part) */
+#define FD_REG_F_END 0x00000024
+/* [0x28]: REG Pulse spacing (TAI seconds) */
+#define FD_REG_U_DELTA 0x00000028
+/* [0x2c]: REG Pulse spacing (8 ns cycles) */
+#define FD_REG_C_DELTA 0x0000002c
+/* [0x30]: REG Pulse spacing (sub-cycle fine part) */
+#define FD_REG_F_DELTA 0x00000030
+/* [0x34]: REG Repeat Count Register */
+#define FD_REG_RCR 0x00000034
+#endif
--- a/rt/fd/rt-fd.c
+++ b/rt/fd/rt-fd.c
--- a/rt/tdc/Makefile
+++ b/rt/tdc/Makefile
+OBJS = rt-tdc.o
+OUTPUT = rt-tdc
+
+include ../common/wrnode.mk
--- a/rt/tdc/hw/fmctdc-direct.h
+++ b/rt/tdc/hw/fmctdc-direct.h
+/*
+  Register definitions for slave core: TDC Direct Readout WB Slave
+
+  * File           : fmctdc-direct.h
+  * Author         : auto-generated by wbgen2 from fmc_tdc_direct_readout_slave.wb
+  * Created        : Thu May 15 14:23:14 2014
+  * Standard       : ANSI C
+
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_tdc_direct_readout_slave.wb
+    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_FMC_TDC_DIRECT_READOUT_SLAVE_WB
+#define __WBGEN2_REGDEFS_FMC_TDC_DIRECT_READOUT_SLAVE_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+
+/* definitions for register: Channel Enable Register */
+
+/* definitions for register: Dead Time Register */
+
+/* definitions for register: FIFO 'Readout FIFO' data output register 0 */
+
+/* definitions for field: Seconds in reg: FIFO 'Readout FIFO' data output register 0 */
+#define DR_FIFO_R0_SECONDS_MASK               WBGEN2_GEN_MASK(0, 32)
+#define DR_FIFO_R0_SECONDS_SHIFT              0
+#define DR_FIFO_R0_SECONDS_W(value)           WBGEN2_GEN_WRITE(value, 0, 32)
+#define DR_FIFO_R0_SECONDS_R(reg)             WBGEN2_GEN_READ(reg, 0, 32)
+
+/* definitions for register: FIFO 'Readout FIFO' data output register 1 */
+
+/* definitions for field: Cycles in reg: FIFO 'Readout FIFO' data output register 1 */
+#define DR_FIFO_R1_CYCLES_MASK                WBGEN2_GEN_MASK(0, 32)
+#define DR_FIFO_R1_CYCLES_SHIFT               0
+#define DR_FIFO_R1_CYCLES_W(value)            WBGEN2_GEN_WRITE(value, 0, 32)
+#define DR_FIFO_R1_CYCLES_R(reg)              WBGEN2_GEN_READ(reg, 0, 32)
+
+/* definitions for register: FIFO 'Readout FIFO' data output register 2 */
+
+/* definitions for field: Bins in reg: FIFO 'Readout FIFO' data output register 2 */
+#define DR_FIFO_R2_BINS_MASK                  WBGEN2_GEN_MASK(0, 18)
+#define DR_FIFO_R2_BINS_SHIFT                 0
+#define DR_FIFO_R2_BINS_W(value)              WBGEN2_GEN_WRITE(value, 0, 18)
+#define DR_FIFO_R2_BINS_R(reg)                WBGEN2_GEN_READ(reg, 0, 18)
+
+/* definitions for field: Edge in reg: FIFO 'Readout FIFO' data output register 2 */
+#define DR_FIFO_R2_EDGE                       WBGEN2_GEN_MASK(18, 1)
+
+/* definitions for field: Channel in reg: FIFO 'Readout FIFO' data output register 2 */
+#define DR_FIFO_R2_CHANNEL_MASK               WBGEN2_GEN_MASK(19, 4)
+#define DR_FIFO_R2_CHANNEL_SHIFT              19
+#define DR_FIFO_R2_CHANNEL_W(value)           WBGEN2_GEN_WRITE(value, 19, 4)
+#define DR_FIFO_R2_CHANNEL_R(reg)             WBGEN2_GEN_READ(reg, 19, 4)
+
+/* definitions for register: FIFO 'Readout FIFO' control/status register */
+
+/* definitions for field: FIFO full flag in reg: FIFO 'Readout FIFO' control/status register */
+#define DR_FIFO_CSR_FULL                      WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: FIFO empty flag in reg: FIFO 'Readout FIFO' control/status register */
+#define DR_FIFO_CSR_EMPTY                     WBGEN2_GEN_MASK(17, 1)
+
+/* definitions for field: FIFO counter in reg: FIFO 'Readout FIFO' control/status register */
+#define DR_FIFO_CSR_USEDW_MASK                WBGEN2_GEN_MASK(0, 8)
+#define DR_FIFO_CSR_USEDW_SHIFT               0
+#define DR_FIFO_CSR_USEDW_W(value)            WBGEN2_GEN_WRITE(value, 0, 8)
+#define DR_FIFO_CSR_USEDW_R(reg)              WBGEN2_GEN_READ(reg, 0, 8)
+/* [0x0]: REG Channel Enable Register */
+#define DR_REG_CHAN_ENABLE 0x00000000
+/* [0x4]: REG Dead Time Register */
+#define DR_REG_DEAD_TIME 0x00000004
+/* [0x8]: REG FIFO 'Readout FIFO' data output register 0 */
+#define DR_REG_FIFO_R0 0x00000008
+/* [0xc]: REG FIFO 'Readout FIFO' data output register 1 */
+#define DR_REG_FIFO_R1 0x0000000c
+/* [0x10]: REG FIFO 'Readout FIFO' data output register 2 */
+#define DR_REG_FIFO_R2 0x00000010
+/* [0x14]: REG FIFO 'Readout FIFO' control/status register */
+#define DR_REG_FIFO_CSR 0x00000014
+#endif
--- a/rt/tdc/rt-tdc.c
+++ b/rt/tdc/rt-tdc.c
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -6,7 +6,7 @@
 DESTDIR ?= /usr/local

 WRNC ?= ../../../
-CFLAGS += -Wall -ggdb -I. -I../common -I$(WRNC)/lib -I$(WRNC)/kernel -I../lib $(EXTRACFLAGS)
+CFLAGS += -Wall -ggdb -I. -I../include -I$(WRNC)/lib -I$(WRNC)/kernel -I../lib $(EXTRACFLAGS)
 LDLIBS += -L../lib -lwrtd -L$(WRNC)/lib -lwrnc

 PROGS := wrtd-boot

--- a/tools/wrtd-in-config.c
+++ b/tools/wrtd-in-config.c
@@ -257,7 +257,7 @@ static int wrtd_cmd_sw_trigger(struct wrtd_node *wrtd, int input,
 	} else {
 		ent.ts.seconds = 0;
 		ent.ts.ticks = 100000000000ULL / 8000ULL; /* 100ms */
-		ent.ts.bins = 0;
+		ent.ts.frac = 0;
 	}

 	return wrtd_in_trigger_software(wrtd, &ent);

--- a/tools/wrtd-inout-common.c
+++ b/tools/wrtd-inout-common.c
@@ -74,7 +74,7 @@ void decode_log_level(char *buf, uint32_t flags)

 void format_ts(char *buf, struct wr_timestamp ts, int with_seconds)
 {
-    uint64_t picoseconds = (uint64_t) ts.ticks * 8000 + (uint64_t)ts.bins * 8000ULL / 4096ULL;
+    uint64_t picoseconds = (uint64_t) ts.ticks * 8000 + (uint64_t)ts.frac * 8000ULL / 4096ULL;


    if(with_seconds)
@@ -103,7 +103,7 @@ uint64_t ts_to_picos(struct wr_timestamp ts)
 {
    return (uint64_t) ts.seconds * 1000LL * 1000 * 1000 * 1000
            + (uint64_t) ts.ticks * 8000ULL +
-            + (uint64_t) ts.bins * 8000LL / 4096LL;
+            + (uint64_t) ts.frac * 8000LL / 4096LL;
 }

 int parse_delay(char *dly, uint64_t *delay_ps)