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Commit 940a1034 authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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Delete old FPGA files

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FPGA/repo/foo/latch-registers.vhdl deleted 100644 → 0
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--------------------------------------------------------------------------------
-- Title : Top
-- Project : TimIQ
--------------------------------------------------------------------------------
-- Description : Top sheet
--------------------------------------------------------------------------------
-- File : latch_registers.vhd
-- Revision : x.x.x
-- Created : August 02, 2016
-- Updated : March 06, 2018
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil - MAX IV Laboratory
-- Web : http://www.synchrotron-soleil.fr - https://www.maxiv.lu.se
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2015 - 2018 Synchrotron Soleil - MAX IV Laboratory
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
-- Version 1.0.0 ; August 2, 2016 ; Jean-Paul Ricaud
-- * First draft
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library unisim;
use unisim.vcomponents.all;
library xil_defaultlib;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity latch_registers is
port (
-- Clock inputs
p_CLK_SR : in std_logic; -- Storage ring clock
p_data_ready : in std_logic;
p_data_ack : out std_logic;
p_reg_delay_counter0 : in std_logic_vector(31 downto 0);
p_reg_ratio_counter0 : in std_logic_vector(31 downto 0);
p_reg_value_counter0 : in std_logic_vector(31 downto 0);
p_reg_delay_counter1 : in std_logic_vector(31 downto 0);
p_reg_ratio_counter1 : in std_logic_vector(31 downto 0);
p_reg_value_counter1 : in std_logic_vector(31 downto 0);
p_reg_delay_counter2 : in std_logic_vector(31 downto 0);
p_reg_ratio_counter2 : in std_logic_vector(31 downto 0);
p_reg_value_counter2 : in std_logic_vector(31 downto 0);
p_reg_delay_counter3 : in std_logic_vector(31 downto 0);
p_reg_ratio_counter3 : in std_logic_vector(31 downto 0);
p_reg_value_counter3 : in std_logic_vector(31 downto 0);
p_sync_delay_counter0 : out std_logic_vector(31 downto 0);
p_sync_ratio_counter0 : out std_logic_vector(31 downto 0);
p_sync_value_counter0 : out std_logic_vector(31 downto 0);
p_sync_delay_counter1 : out std_logic_vector(31 downto 0);
p_sync_ratio_counter1 : out std_logic_vector(31 downto 0);
p_sync_value_counter1 : out std_logic_vector(31 downto 0);
p_sync_delay_counter2 : out std_logic_vector(31 downto 0);
p_sync_ratio_counter2 : out std_logic_vector(31 downto 0);
p_sync_value_counter2 : out std_logic_vector(31 downto 0);
p_sync_delay_counter3 : out std_logic_vector(31 downto 0);
p_sync_ratio_counter3 : out std_logic_vector(31 downto 0);
p_sync_value_counter3 : out std_logic_vector(31 downto 0)
);
end entity latch_registers;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_latch_registers of latch_registers is
------------------------------------------------------------------------------
-- component
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_data_ready : std_logic := '0';
------------------------------------------------------------------------------
-- Attributes
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
------------------------------------------------------------------------------
-- Synchronize the SR clock to the sys clock
synchronizer : entity xil_defaultlib.synchronizer (rtl_synchronizer)
generic map (
g_size => 3 )
port map (
p_clkin => p_CLK_SR,
p_in => p_data_ready,
p_rising_edge => open,
p_falling_edge => open,
p_out => s_data_ready
);
------------------------------------------------------------------------------
-- latch_registers CPU
process (p_CLK_SR)
begin
if rising_edge(p_CLK_SR) then
if (s_data_ready = '1') then
p_sync_delay_counter0 <= p_reg_delay_counter0;
p_sync_ratio_counter0 <= p_reg_ratio_counter0;
p_sync_value_counter0 <= p_reg_value_counter0;
p_sync_delay_counter1 <= p_reg_delay_counter1;
p_sync_ratio_counter1 <= p_reg_ratio_counter1;
p_sync_value_counter1 <= p_reg_value_counter1;
p_sync_delay_counter2 <= p_reg_delay_counter2;
p_sync_ratio_counter2 <= p_reg_ratio_counter2;
p_sync_value_counter2 <= p_reg_value_counter2;
p_sync_delay_counter3 <= p_reg_delay_counter3;
p_sync_ratio_counter3 <= p_reg_ratio_counter3;
p_sync_value_counter3 <= p_reg_value_counter3;
p_data_ack <= '1';
else
p_data_ack <= '0';
end if;
end if;
end process;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
end architecture rtl_latch_registers;
FPGA/repo/src_Freqdividers/frequency_divider.vhdl deleted 100644 → 0
View file @ a1f0ed18
--------------------------------------------------------------------------------
-- Title : Divider
-- Project : TimBEL_V2
--------------------------------------------------------------------------------
-- Description : Divide the main power by an user specified ratio.
-- The main power supply (230V ; 50Hz) frequency is multiplied by
-- 2 at the FPGA's input (100Hz). This frequency is divided by this
-- block by a user specified ration ratio between 1 - 255. The
-- default ratio is 34 for an 2.94Hz output (equivalent to 50Hz/17).
--------------------------------------------------------------------------------
-- File : divider.vhd
-- Revision : x.x.x
-- Created : Juin 30, 2021
-- Updated : Juin 30, 2021
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2021 - 2021 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library xil_defaultlib;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity divider is
generic (
-- Width of S_AXI data bus
g_default_delay : unsigned (31 downto 0);
g_default_ratio : unsigned (31 downto 0);
g_default_division : unsigned (31 downto 0);
g_S_AXI_DATA_WIDTH : integer := 32
);
port (
p_CLK_RF : in std_logic; -- RF CLK
p_divider_reset : in std_logic; -- reset and idle the divider
p_delay_register : in std_logic_vector ((g_S_AXI_DATA_WIDTH - 1) downto 0); -- delay time
p_ratio_register : in std_logic_vector ((g_S_AXI_DATA_WIDTH - 1) downto 0); -- division ratio
p_value_register : in std_logic_vector ((g_S_AXI_DATA_WIDTH - 1) downto 0); -- division value
p_freq_out : out std_logic -- main signal output after frequency division
);
end entity divider;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_divider of divider is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_out : std_logic := '0';
signal s_cnt : unsigned (31 downto 0) := (OTHERS => '0'); -- counter
signal s_cntmax : unsigned (31 downto 0) := g_default_division;
signal s_cnt_delay : unsigned (31 downto 0) := (OTHERS => '0'); -- counter
signal s_cntmax_delay : unsigned (31 downto 0) := g_default_division;
signal s_inhibit : std_logic := '0';
------------------------------------------------------------------------------
-- Attributes
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
------------------------------------------------------------------------------
-- Delay clock
clk_delay : process (p_CLK_RF)
begin
if (falling_edge(p_CLK_RF)) then
if (p_divider_reset = '1') then
s_cntmax_delay <= unsigned(p_delay_register(31 downto 0)) - 1;
s_inhibit <= '1';
else
if (s_cnt_delay = s_cntmax_delay) then
s_cnt_delay <= (OTHERS => '0');
s_cntmax_delay <= unsigned(p_delay_register(31 downto 0)) - 1;
s_inhibit <= '1';
else
s_cnt_delay <= s_cnt_delay + 1;
s_inhibit <= '0';
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Divide clock
clk_divider : process (p_CLK_RF)
begin
if (falling_edge(p_CLK_RF)) then
if (s_cntmax = 0 or s_inhibit = '1') then
s_cntmax <= unsigned(p_value_register(31 downto 0)) - 1;
else
if (s_cnt = s_cntmax) then
s_cnt <= (OTHERS => '0');
s_cntmax <= unsigned(p_value_register(31 downto 0)) - 1;
else
s_cnt <= s_cnt + 1;
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Signal ratio
clk_ratio : process (p_CLK_RF)
begin
if (falling_edge(p_CLK_RF)) then
if (s_inhibit = '1') then
s_out <= '0';
else
if (s_cnt > unsigned(p_ratio_register)) then
s_out <= '1';
else
s_out <= '0';
end if;
end if;
end if;
end process;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
p_freq_out <= s_out;
end architecture rtl_divider;
FPGA/repo/src_lib/synchronizer.vhdl deleted 100644 → 0
View file @ a1f0ed18
--------------------------------------------------------------------------------
-- Title : synchronizer
-- Project : TimPO_v2
--------------------------------------------------------------------------------
-- Description : Synchonize an asynchrone signal to the system clock.
--------------------------------------------------------------------------------
-- File : synchronizer.vhd
-- Revision : x.x.x
-- Created : Juin 30, 2021
-- Updated : Juin 30, 2021
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2021 - 2021 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity synchronizer is
generic (
g_size : integer := 3
);
port (
p_clkin : in std_logic; -- clock
p_in : in std_logic; -- input signal (asynchronou)
p_rising_edge : out std_logic; -- output rising edge detector
p_falling_edge : out std_logic; -- output falling edge detector
p_out : out std_logic -- output resynchonized signal
);
end synchronizer;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_synchronizer of synchronizer is
signal s_buffer : std_logic_vector (g_size downto 0) := (others => '0');
-- To avoid the FFs being replaced by SRL
attribute ASYNC_REG : string;
attribute ASYNC_REG of s_buffer : signal is "TRUE";
signal s_rising : std_logic := '0';
signal s_falling : std_logic := '0';
begin
process (p_clkin)
begin
if (rising_edge(p_clkin)) then
s_buffer(0) <= p_in;
for I in 1 to g_size loop
s_buffer(I) <= s_buffer(I - 1);
end loop;
s_rising <= s_buffer(g_size - 1) and (not s_buffer(g_size));
s_falling <= s_buffer(g_size) and (not s_buffer(g_size - 1));
end if;
end process;
p_rising_edge <= s_rising;
p_falling_edge <= s_falling;
p_out <= s_buffer(g_size);
end rtl_synchronizer;
FPGA/repo/top.vhdl deleted 100644 → 0
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README.md deleted 100644 → 0
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# Macbeth
The Macbeth (MAChine / BEamline Timing Hardware) system is aimed to synchronize the beamlines experimental devices (pump-probe, laser, …) with the accelerator beam with a high accuracy
\ No newline at end of file
readme.md deleted 100644 → 0
View file @ a1f0ed18
# Macbeth
The Macbeth (MAChine / BEamline Timing Hardware) system is aimed to synchronize the beamlines experimental devices (pump-probe, laser, …) with the accelerator beam with a high accuracy
\ No newline at end of file
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