Skip to content

S
Scalable MAROC Charge Sensitive Readout
Commit 3df8f56d authored by David Cussans's avatar David Cussans
Browse files
Options

Added external trigger on GPIO. Tidied up firmware. Still doesn't meet timing constraints :-( 

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@44 e1591323-3689-4d5a-aa31-d1a7cbdc5706
parent 4608124b
Hide whitespace changes
Inline Side-by-side
Showing with 440 additions and 118 deletions
firmware/hdl/fallingEdgeDetect_rtl.vhd
View file @ 3df8f56d
......@@ -16,7 +16,8 @@ end entity fallingEdgeDetect;
architecture rtl of fallingEdgeDetect is
signal level_d1 , level_d2 : std_logic := '0'; -- delayed version of input
signal pulse , pulse_d1 : std_logic := '0'; -- register output.
begin -- architecture rtl
p_levelDetect: process (clk_i) is
......@@ -25,10 +26,13 @@ begin -- architecture rtl
level_d1 <= level_i;
level_d2 <= level_d1;
if (( level_d2 = '1' ) and ( level_d1 = '0')) then
pulse_o <= '1';
pulse <= '1';
else
pulse_o <= '0';
pulse <= '0';
end if;
pulse_d1 <= pulse;
pulse_o <= pulse_d1;
end if;
end process p_levelDetect;
......
firmware/hdl/ipbusMarocTriggerGenerator_rtl.vhd
View file @ 3df8f56d
......@@ -90,7 +90,7 @@ end ipbusMarocTriggerGenerator;
architecture rtl of ipbusMarocTriggerGenerator is
signal s_internalTrigger_p : std_logic;
signal s_internalTrigger_p ,s_internalTrigger_p_d1 : std_logic;
signal s_triggerSourceSelect : std_logic_vector(3 downto 0) := (others => '0');
signal s_hold1Delay , s_hold2Delay : std_logic_vector(4 downto 0);
......@@ -178,6 +178,9 @@ begin
s_internalTrigger_p <= '0';
ctest_o <= ( others => '0');
end if;
s_internalTrigger_p_d1 <= s_internalTrigger_p;
end if;
end process p_internalTrigger;
......@@ -215,7 +218,7 @@ begin
reset_i => s_counter_reset,
-- conversion_counter_o => s_conversion_counter,
externalTrigger_a_i => externalTrigger_a_i ,
internalTrigger_i => s_internalTrigger_p,
internalTrigger_i => s_internalTrigger_p_d1,
triggerSourceSelect_i=> s_triggerSourceSelect,
hold1Delay_i => s_hold1Delay,
hold2Delay_i => s_hold2Delay,
......
firmware/hdl/ipbus_ver.vhd
View file @ 3df8f56d
......@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is
begin
ipbus_out.ipb_rdata <= X"a625" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_rdata <= X"a627" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
......
firmware/hdl/marocADCFSM_rtl.vhd
View file @ 3df8f56d
......@@ -56,6 +56,7 @@ entity marocADCFSM is
adc_dav_i : in std_logic; --! "Transmitting data" signal from MAROC
reset_sr_o : out std_logic; --! reset ADC and internal shift reg.
start_adc_n_o : out std_logic; --! Goes low during conversion.
end_of_sequence_o : out std_logic; --! Goes high for one clock cycle immediately after DAV goes low
status_o : out std_logic --! Zero when FSM is idle , one otherwise
);
end marocADCFSM;
......@@ -66,8 +67,10 @@ end marocADCFSM;
architecture rtl of marocADCFSM is
--! Define an enumerated type corresponding to FSM states
type t_state_type is (IDLE , RESETTING , WAIT_FOR_DAV_HIGH , WAIT_FOR_DAV_LOW );
type t_state_type is (IDLE , RESETTING , WAIT_FOR_DAV_HIGH , WAIT_FOR_DAV_LOW , END_OF_READOUT );
signal s_state , s_next_state : t_state_type := IDLE ;
signal s_end_of_sequence , s_status , s_start_adc_n, s_reset_sr: std_logic := '0';
--============================================================================
-- architecture begin
......@@ -88,6 +91,12 @@ begin -- rtl
else
s_state <= s_next_state;
end if;
end_of_sequence_o <= s_end_of_sequence;
status_o <= s_status;
start_adc_n_o <= s_start_adc_n;
reset_sr_o <= s_reset_sr;
end if;
end process p_state_register;
......@@ -119,11 +128,14 @@ begin -- rtl
when WAIT_FOR_DAV_LOW =>
if (adc_dav_i = '0') then
s_next_state <= IDLE;
s_next_state <= END_OF_READOUT;
else
s_next_state <= WAIT_FOR_DAV_LOW;
end if;
when END_OF_READOUT =>
s_next_state <= IDLE;
when others =>
s_next_state <= IDLE;
......@@ -135,12 +147,14 @@ begin -- rtl
--==========================================================================
--! reset goes high-when state=resetting
reset_sr_o <= '1' when s_state = RESETTING else '0';
s_reset_sr <= '1' when s_state = RESETTING else '0';
--! start_adc_n_o goes low during conversion
start_adc_n_o <= '0' when (s_state = WAIT_FOR_DAV_HIGH) or (s_state = WAIT_FOR_DAV_LOW ) else '1';
s_start_adc_n <= '0' when (s_state = WAIT_FOR_DAV_HIGH) or (s_state = WAIT_FOR_DAV_LOW ) else '1';
status_o <= '0' when s_state = IDLE else '1';
s_status <= '0' when s_state = IDLE else '1';
s_end_of_sequence <= '1' when s_state = END_OF_READOUT else '0';
end rtl;
--============================================================================
......
firmware/hdl/marocADC_rtl.vhd
View file @ 3df8f56d
......@@ -133,15 +133,14 @@ begin
--==========================================================================
-- purpose: Shift register to deserialize data from MAROC
-- type : combinational
-- inputs : clk_i , out_adc_i
-- inputs : clk_i , reset_i , out_adc_i
-- outputs: s_shiftReg
--==========================================================================
p_shiftReg: process (clk_i , out_adc_i)
p_shiftReg: process (clk_i , reset_i, out_adc_i)
begin -- process p_shiftReg
if rising_edge(clk_i) then
if (reset_i = '1') then
s_writeAddr <= (others => '0');
s_shiftRegCounter <= (others => '0');
elsif (s_reset_sr='1') then
s_shiftRegCounter <= (others => '0');
......@@ -150,23 +149,30 @@ begin
s_shiftRegCounter <= s_shiftRegCounter + 1;
end if;
-- Increment write address if a complete word has been shifted or if end
-- of ADC readout has been reached.
s_shiftRegFull_d1 <= s_shiftRegFull;
if (s_wen = '1') then
s_writeAddr <= s_writeAddr + 1;
end if;
--! Delay reset shift-reg signal to act as flag for
--! writing timestamp into DPR.
s_reset_sr_d1 <= s_reset_sr;
s_shiftRegFull_d1 <= s_shiftRegFull;
end if; -- rising_edge(clk_i)
end process p_shiftReg;
p_writeAddrControl: process(clk_i , s_wen , reset_i )
begin
if rising_edge(clk_i) then
if (reset_i = '1') then
s_writeAddr <= (others => '0');
elsif (s_wen = '1') then
-- Increment write address if a complete word has been shifted or if end
-- of ADC readout has been reached.
s_writeAddr <= s_writeAddr + 1;
end if;
end if;
end process p_writeAddrControl;
--! Generate write enable for DPRAM ( also increments write address
s_shiftRegFull <= '1' when (s_shiftRegCounter(4 downto 0) = "11111" ) else '0';
......@@ -187,6 +193,7 @@ begin
adc_dav_i => adc_dav_i,
reset_sr_o => s_reset_sr,
start_adc_n_o => start_adc_n_o,
end_of_sequence_o => open,
status_o => status_o
);
......
firmware/hdl/marocTriggerGenerator_rtl.vhd
View file @ 3df8f56d
......@@ -131,7 +131,9 @@ ARCHITECTURE rtl OF marocTriggerGenerator IS
--from output port...
signal s_hold1_d1 : std_logic; --!
signal s_hold1_d2 : std_logic; --!
signal s_hold1_d3 : std_logic; --!
signal s_hold1_d3 : std_logic; --!
signal s_hold1_d4 : std_logic; --!
signal s_hold1_d5 : std_logic; --!
BEGIN
......@@ -226,6 +228,15 @@ BEGIN
D => s_hold1 -- SRL data input
); -- End of SRLC32E_inst instantiation
-- Having timing closure problems with this signal. Put in some more registers....
p_RegisterHold1: process (clk_fast_i, s_hold1)
begin -- process p_RegisterHold1
if rising_edge(clk_fast_i) then -- rising clock edge
s_hold1_d1 <= s_hold1;
s_hold1_d2 <= s_hold1_d1;
end if;
end process p_RegisterHold1;
-- purpose: registers s_hold1 onto system (slow) clock and detect rising edge to form adcConversionStart_o
-- type : sequential
......@@ -235,11 +246,11 @@ BEGIN
begin -- process p_GenerateADCStart
if rising_edge(clk_sys_i) then -- rising clock edge
s_hold1_d1 <= s_hold1;
s_hold1_d2 <= s_hold1_d1;
s_hold1_d3 <= s_hold1_d2;
s_hold1_d4 <= s_hold1_d3;
s_hold1_d5 <= s_hold1_d4;
s_adcConversionStart <= (not s_hold1_d2) and s_hold1_d3 ;
s_adcConversionStart <= (not s_hold1_d4) and s_hold1_d5 ;
end if;
end process p_GenerateADCStart;
......
firmware/sim/hdl/pc049a_demo_tb.vhd 0 → 100644
View file @ 3df8f56d
-- Test bench for pc049a_top firmware for single MAROC Evaluation board.
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity pc049a_top_tb is
end;
architecture bench of pc049a_top_tb is
signal clk_20m_vcxo_i: std_logic := '0' ;
signal clk_125m_pllref_p_i , clk_125m_pllref_n_i: std_logic := '0';
signal fpga_pll_ref_clk_101_p_i , fpga_pll_ref_clk_101_n_i: std_logic := '0';
signal fpga_pll_ref_clk_123_p_i , fpga_pll_ref_clk_123_n_i: std_logic := '0';
signal si57x_clk_p_i , si57x_clk_n_i: std_logic := '0';
signal si57x_oe_o: std_logic := '1';
signal GPIO: std_logic_vector(7 downto 0);
signal button1_i: std_logic := 'H';
signal button2_i: std_logic := 'H';
signal leds_o: std_logic_vector(4 downto 0);
signal dip_switch_i: std_logic_vector(3 downto 0);
signal pll25dac_sclk_o: std_logic := '0';
signal pll25dac_din_o: std_logic := '0';
signal pll25dac1_sync_n_o: std_logic := '1';
signal pll25dac2_sync_n_o: std_logic := '1';
signal fpga_scl_b: std_logic;
signal fpga_sda_b: std_logic;
signal one_wire_b: std_logic;
signal sfp_txp_o: std_logic_vector(1 downto 0);
signal sfp_txn_o: std_logic_vector(1 downto 0);
signal sfp_rxp_i: std_logic_vector(1 downto 0);
signal sfp_rxn_i: std_logic_vector(1 downto 0);
signal sfp_mod_def0_b: std_logic_vector(1 downto 0);
signal sfp_mod_def1_b: std_logic_vector(1 downto 0);
signal sfp_mod_def2_b: std_logic_vector(1 downto 0);
signal sfp_rate_select_b: std_logic_vector(1 downto 0);
signal sfp_tx_fault_i: std_logic_vector(1 downto 0);
signal sfp_tx_disable_o: std_logic_vector(1 downto 0);
signal sfp_los_i: std_logic_vector(1 downto 0);
signal sata_txp_o: std_logic_vector(1 downto 0);
signal sata_txn_o: std_logic_vector(1 downto 0);
signal sata_rxp_i: std_logic_vector(1 downto 0);
signal sata_rxn_i: std_logic_vector(1 downto 0);
signal CK_40M_P_O,CK_40M_N_O: STD_LOGIC;
signal HOLD2_O: STD_LOGIC;
signal HOLD1_O: STD_LOGIC;
signal OR_I: STD_LOGIC_VECTOR(1 downto 0);
signal MAROC_TRIGGER_I: std_logic_vector(63 downto 0);
signal EN_OTAQ_O: STD_LOGIC;
signal CTEST_O: STD_LOGIC_VECTOR(5 downto 0);
signal ADC_DAV_I: STD_LOGIC;
signal OUT_ADC_I: STD_LOGIC;
signal START_ADC_N_O: STD_LOGIC;
signal RST_ADC_N_O: STD_LOGIC;
signal RST_SC_N_O: STD_LOGIC;
signal Q_SC_I: STD_LOGIC;
signal D_SC_O: STD_LOGIC;
signal RST_R_N_O: STD_LOGIC;
signal Q_R_I: STD_LOGIC;
signal D_R_O: STD_LOGIC;
signal CK_R_O: STD_LOGIC;
signal CK_SC_O: STD_LOGIC;
signal lvds_left_data_p_b, lvds_left_data_n_b: std_logic_vector(15 downto 0);
signal lvds_left_clk_p_b,lvds_left_clk_n_b: std_logic;
signal lvds_right_data_p_b,lvds_right_data_n_b: std_logic_vector(15 downto 0);
signal lvds_right_clk_p_b,lvds_right_clk_n_b: std_logic;
signal lvds_globaltrig_from_fpga_p_o: std_logic;
signal lvds_globaltrig_from_fpga_n_o: std_logic;
signal enable_globaltrig_drive_o: std_logic;
signal lvds_globaltrig_to_fpga_p_i: std_logic;
signal lvds_globaltrig_to_fpga_n_i: std_logic;
signal lvds_otrig_from_fpga_p_o: std_logic;
signal lvds_otrig_from_fpga_n_o: std_logic;
signal lvds_otrig_to_fpga_p_i: std_logic;
signal lvds_otrig_to_fpga_n_i: std_logic;
signal lvds_gclk_from_fpga_p_o: std_logic;
signal lvds_gclk_from_fpga_n_o: std_logic;
signal enable_gclk_drive_o: std_logic;
signal lvds_gclk_to_fpga_p_i: std_logic;
signal lvds_gclk_to_fpga_n_i: std_logic ;
begin
dip_switch_i <= "0001"; -- Set address to 192.168.200.16
uut: entity work.pc049a_top
generic map ( BUILD_WHITERABBIT => 0,
BUILD_SIMULATED_ETHERNET => 1 )
port map ( clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
fpga_pll_ref_clk_101_p_i => fpga_pll_ref_clk_101_p_i,
fpga_pll_ref_clk_101_n_i => fpga_pll_ref_clk_101_n_i,
fpga_pll_ref_clk_123_p_i => fpga_pll_ref_clk_123_p_i,
fpga_pll_ref_clk_123_n_i => fpga_pll_ref_clk_123_n_i,
si57x_clk_p_i => si57x_clk_p_i,
si57x_clk_n_i => si57x_clk_n_i,
si57x_oe_o => si57x_oe_o,
GPIO => GPIO,
button1_i => button1_i,
button2_i => button2_i,
leds_o => leds_o,
dip_switch_i => dip_switch_i,
pll25dac_sclk_o => pll25dac_sclk_o,
pll25dac_din_o => pll25dac_din_o,
pll25dac1_sync_n_o => pll25dac1_sync_n_o,
pll25dac2_sync_n_o => pll25dac2_sync_n_o,
fpga_scl_b => fpga_scl_b,
fpga_sda_b => fpga_sda_b,
one_wire_b => one_wire_b,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_b => sfp_mod_def0_b,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_b => sfp_rate_select_b,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
sata_txp_o => sata_txp_o,
sata_txn_o => sata_txn_o,
sata_rxp_i => sata_rxp_i,
sata_rxn_i => sata_rxn_i,
CK_40M_P_O => CK_40M_P_O,
CK_40M_N_O => CK_40M_N_O,
HOLD2_O => HOLD2_O,
HOLD1_O => HOLD1_O,
OR_I => OR_I,
MAROC_TRIGGER_I => MAROC_TRIGGER_I,
EN_OTAQ_O => EN_OTAQ_O,
CTEST_O => CTEST_O,
ADC_DAV_I => ADC_DAV_I,
OUT_ADC_I => OUT_ADC_I,
START_ADC_N_O => START_ADC_N_O,
RST_ADC_N_O => RST_ADC_N_O,
RST_SC_N_O => RST_SC_N_O,
Q_SC_I => Q_SC_I,
D_SC_O => D_SC_O,
RST_R_N_O => RST_R_N_O,
Q_R_I => Q_R_I,
D_R_O => D_R_O,
CK_R_O => CK_R_O,
CK_SC_O => CK_SC_O,
lvds_left_data_p_b => lvds_left_data_p_b,
lvds_left_data_n_b => lvds_left_data_n_b,
lvds_left_clk_p_b => lvds_left_clk_p_b,
lvds_left_clk_n_b => lvds_left_clk_n_b,
lvds_right_data_p_b => lvds_right_data_p_b,
lvds_right_data_n_b => lvds_right_data_n_b,
lvds_right_clk_p_b => lvds_right_clk_p_b,
lvds_right_clk_n_b => lvds_right_clk_n_b,
lvds_globaltrig_from_fpga_p_o => lvds_globaltrig_from_fpga_p_o,
lvds_globaltrig_from_fpga_n_o => lvds_globaltrig_from_fpga_n_o,
enable_globaltrig_drive_o => enable_globaltrig_drive_o,
lvds_globaltrig_to_fpga_p_i => lvds_globaltrig_to_fpga_p_i,
lvds_globaltrig_to_fpga_n_i => lvds_globaltrig_to_fpga_n_i,
lvds_otrig_from_fpga_p_o => lvds_otrig_from_fpga_p_o,
lvds_otrig_from_fpga_n_o => lvds_otrig_from_fpga_n_o,
lvds_otrig_to_fpga_p_i => lvds_otrig_to_fpga_p_i,
lvds_otrig_to_fpga_n_i => lvds_otrig_to_fpga_n_i,
lvds_gclk_from_fpga_p_o => lvds_gclk_from_fpga_p_o,
lvds_gclk_from_fpga_n_o => lvds_gclk_from_fpga_n_o,
enable_gclk_drive_o => enable_gclk_drive_o,
lvds_gclk_to_fpga_p_i => lvds_gclk_to_fpga_p_i,
lvds_gclk_to_fpga_n_i => lvds_gclk_to_fpga_n_i );
-- dummy MAROC ADC
dummyADC: entity work.dummyMarocADC
port map (
clk_i => CK_40M_P_O,
reset_n_i => RST_ADC_N_O,
startadc_n_i => START_ADC_N_O,
adc_dav_o => ADC_DAV_I ,
adc_data_o => OUT_ADC_I
);
--clocks
clk_20m_vcxo_i <= not clk_20m_vcxo_i after 25 ns;
clk_125m_pllref_p_i <= not clk_125m_pllref_p_i after 4 ns;
clk_125m_pllref_n_i <= not clk_125m_pllref_p_i;
fpga_pll_ref_clk_101_p_i <= not fpga_pll_ref_clk_101_p_i after 4 ns;
fpga_pll_ref_clk_101_n_i <= not fpga_pll_ref_clk_101_p_i;
fpga_pll_ref_clk_123_p_i <= not fpga_pll_ref_clk_123_p_i after 4 ns;
fpga_pll_ref_clk_123_n_i <= not fpga_pll_ref_clk_123_p_i;
si57x_clk_p_i <= not si57x_clk_p_i after 4 ns;
si57x_clk_n_i <= not si57x_clk_p_i;
stimulus: process
begin
-- Put initialisation code here
-- Put test bench stimulus code here
wait;
end process;
end;
firmware/top/pc049a/demo/pc049a_top.ucf
View file @ 3df8f56d
......@@ -14,8 +14,8 @@ CONFIG PROHIBIT = Y4;
CONFIG VCCAUX=2.5;
INST "cmp_gtp_dedicated_clk_buf0" LOC = BUFDS_X2Y5;
INST "IPBusInterface_inst/eth/ibuf0" LOC = BUFDS_X1Y5;
INST "IPBusInterface_inst/eth/phy/transceiver_inst/GTP_1000X/tile0_s6_gtpwizard_i/gtpa1_dual_i" LOC = GTPA1_DUAL_X0Y1;
INST "IPBusInterface_inst/generate_physicalmac.eth/ibuf0" LOC = BUFDS_X1Y5;
INST "IPBusInterface_inst/generate_physicalmac.eth/phy/transceiver_inst/GTP_1000X/tile0_s6_gtpwizard_i/gtpa1_dual_i" LOC = GTPA1_DUAL_X0Y1;
# INST "U_GTP/U_GTP_TILE_INST/gtpa1_dual_i" LOC = GTPA1_DUAL_X1Y1;
NET "ADC_DAV_I" IOSTANDARD = SSTL2_I;
......@@ -142,6 +142,7 @@ NET "GPIO[6]" LOC = F1;
NET "GPIO[6]" SLEW = SLOW;
NET "GPIO[7]" IOSTANDARD = LVCMOS33;
NET "GPIO[7]" LOC = F5;
NET "GPIO[7]" PULLDOWN=true;
NET "HOLD1_O" DRIVE = 12;
NET "HOLD1_O" IOSTANDARD = LVCMOS33;
NET "HOLD1_O" LOC = Y2;
......@@ -464,10 +465,10 @@ NET "one_wire_b" DRIVE = 12;
NET "one_wire_b" IOSTANDARD = LVCMOS33;
NET "one_wire_b" LOC = T5;
NET "one_wire_b" SLEW = SLOW;
NET "OR_I[0]" IOSTANDARD = SSTL2_I;
NET "OR_I[0]" LOC = N6;
NET "OR_I[1]" IOSTANDARD = SSTL2_I;
NET "OR_I[1]" LOC = P6;
NET "OR_I[1]" LOC = N6;
NET "OR_I[2]" IOSTANDARD = SSTL2_I;
NET "OR_I[2]" LOC = P6;
NET "OUT_ADC_I" IOSTANDARD = SSTL2_I;
NET "OUT_ADC_I" LOC = W3;
NET "pll25dac1_sync_n_o" DRIVE = 12;
......@@ -486,10 +487,10 @@ NET "pll25dac_sclk_o" DRIVE = 12;
NET "pll25dac_sclk_o" IOSTANDARD = LVCMOS33;
NET "pll25dac_sclk_o" LOC = P1;
NET "pll25dac_sclk_o" SLEW = SLOW;
NET "Q_R_I_IBUF" IOSTANDARD = LVCMOS33;
#NET "Q_R_I_IBUF" IOSTANDARD = LVCMOS33;
NET "Q_R_I" IOSTANDARD = LVCMOS33;
NET "Q_R_I" LOC = U1;
NET "Q_SC_I_IBUF" IOSTANDARD = LVCMOS33;
#NET "Q_SC_I_IBUF" IOSTANDARD = LVCMOS33;
NET "Q_SC_I" IOSTANDARD = LVCMOS33;
NET "Q_SC_I" LOC = U3;
NET "RST_ADC_N_O" DRIVE = 12;
......@@ -499,12 +500,12 @@ NET "RST_ADC_N_O" SLEW = SLOW;
NET "RST_R_N_O" DRIVE = 12;
NET "RST_R_N_O" IOSTANDARD = LVCMOS33;
NET "RST_R_N_O" LOC = Y1;
NET "RST_R_N_O_OBUF" IOSTANDARD = LVCMOS33;
#NET "RST_R_N_O_OBUF" IOSTANDARD = LVCMOS33;
NET "RST_R_N_O" SLEW = SLOW;
NET "RST_SC_N_O" DRIVE = 12;
NET "RST_SC_N_O" IOSTANDARD = LVCMOS33;
NET "RST_SC_N_O" LOC = U4;
NET "RST_SC_N_O_OBUF" IOSTANDARD = LVCMOS33;
#NET "RST_SC_N_O_OBUF" IOSTANDARD = LVCMOS33;
NET "RST_SC_N_O" SLEW = SLOW;
NET "sata_rxp_i[0]" LOC = D13;
NET "sata_rxn_i[1]" LOC = C9;
......@@ -589,4 +590,15 @@ TIMESPEC TS_fpga_pll_ref_clk_123_p_i = PERIOD "fpga_pll_ref_clk_123_p_i" 125 MHz
TIMESPEC TS_lvds_left_clk_p_b = PERIOD "lvds_left_clk_p_b" 125 MHz HIGH 50 %;
TIMESPEC TS_lvds_right_clk_p_b = PERIOD "lvds_right_clk_p_b" 125 MHz HIGH 50 %;
NET "IPBusInterface_inst/clocks/rst" TIG;
\ No newline at end of file
# Don't care about the timing of these signals w.r.t. clock, since they are static during data acqusition
NET "*s_triggerSourceSelect*" TIG;
NET "*s_hold1Delay*" TIG;
NET "*s_hold2Delay*" TIG;
# Don't care about timing of reset signal
NET "IPBusInterface_inst/generate_physicalmac.clocks/rst*" TIG;
NET "maroc/slave2_trigger/s_counter_reset_ipb" TIG;
# Bodge, bodge
NET "maroc/slave5_triggerCounter/*reset*" TIG;
NET "maroc/slave5_triggerCounter/inst_sync_reg/*ring*" TIG;
NET "maroc/slave5_triggerCounter/inst_sync_reg/*data*" TIG;
\ No newline at end of file
firmware/top/pc049a/demo/pc049a_top.vhd
View file @ 3df8f56d
......@@ -149,7 +149,7 @@ entity pc049a_top is
HOLD2_O: out STD_LOGIC;
HOLD1_O: out STD_LOGIC;
OR_I: in STD_LOGIC_VECTOR(1 downto 0);
OR_I: in STD_LOGIC_VECTOR(2 downto 1);
MAROC_TRIGGER_I: in std_logic_vector(63 downto 0);
EN_OTAQ_O: out STD_LOGIC;
CTEST_O: out STD_LOGIC_VECTOR(5 downto 0); -- 4-bit R/2R DAC
......@@ -273,11 +273,18 @@ architecture rtl of pc049a_top is
signal dac_rst_n : std_logic;
signal led_divider : unsigned(23 downto 0);
signal wrc_scl_o : std_logic;
signal wrc_scl_i : std_logic;
--! I2C signals from white rabbit core.
signal wrc_scl_o : std_logic := '1'; --! By default, don't drive from WRC.
signal wrc_scl_i : std_logic := '1'; --! ... ie. set high.
signal wrc_sda_o : std_logic;
signal wrc_sda_i : std_logic;
--! I2C signals from IPBus.
signal ipb_scl_o : std_logic := '1'; --! By default, don't drive from IPBus
signal ipb_scl_i : std_logic := '1'; --! ... ie. set high.
signal ipb_sda_o : std_logic;
signal ipb_sda_i : std_logic;
signal sfp_scl_o : std_logic_vector(1 downto 0) := ( others => '0' );
signal sfp_scl_i : std_logic_vector(1 downto 0);
signal sfp_sda_o : std_logic_vector(1 downto 0);
......@@ -334,9 +341,9 @@ architecture rtl of pc049a_top is
signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out;
constant c_NMAROC_SLAVES : integer := 5;
-- expansion IO block has one IPBus slave.
constant c_NSLAVES : positive := c_NMAROC_SLAVES+1; -- number of IPBus slaves in system
constant c_NMAROC_SLAVES : integer := 6;
-- expansion IO block has one IPBus slave. I2C has another
constant c_NSLAVES : positive := c_NMAROC_SLAVES+2; -- number of IPBus slaves in system
signal s_ipb_clk : std_logic;
signal s_ipb_wbus : ipb_wbus_array(c_NSLAVES-1 downto 0);
signal s_ipb_rbus : ipb_rbus_array(c_NSLAVES-1 downto 0);
......@@ -348,10 +355,90 @@ architecture rtl of pc049a_top is
-- Signals that used to be connected at the top level...
signal uart_rxd , uart_txd : std_logic;
-- FIXME Move to separate process
signal s_ADC_DAV_d1, s_ADC_DAV_d2: STD_LOGIC;
signal s_OUT_ADC_d1, s_OUT_ADC_d2: STD_LOGIC;
attribute shreg_extract : string; -- Don't want synchronizer registers optimized to SRL16
attribute shreg_extract of s_ADC_DAV_d1: signal is "no";
attribute shreg_extract of s_ADC_DAV_d2: signal is "no";
attribute shreg_extract of s_OUT_ADC_d1: signal is "no";
attribute shreg_extract of s_OUT_ADC_d2: signal is "no";
-- trigger on GPIO connector
signal s_gpio_trigger: STD_LOGIC;
begin
cmp_sys_clk_pll : PLL_BASE
cmp_clk_vcxo : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
cmp_pllrefclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- Dedicated clock for GTP used for WhiteRabbit
------------------------------------------------------------------------------
cmp_gtp_dedicated_clk_buf0 : IBUFGDS
generic map(
DIFF_TERM => true,
IBUF_LOW_PWR => true,
IOSTANDARD => "DEFAULT")
port map (
O => gtp_dedicated_clk(0),
I => fpga_pll_ref_clk_101_p_i,
IB => fpga_pll_ref_clk_101_n_i
);
------------------------------------------------------------------------------
-- Active high reset
------------------------------------------------------------------------------
--process(clk_sys)
--begin
-- if rising_edge(clk_sys) then
-- led_divider <= led_divider + 1;
-- end if;
--end process;
-- The I2C lines can be driven from either the WhiteRabbit
-- or the IPBus controlled lines.
fpga_scl_b <= '0' when ((wrc_scl_o = '0') or (ipb_scl_o = '0') ) else 'Z';
fpga_sda_b <= '0' when ((wrc_sda_o = '0') or (ipb_sda_o = '0' )) else 'Z';
wrc_scl_i <= fpga_scl_b;
wrc_sda_i <= fpga_sda_b;
ipb_scl_i <= fpga_scl_b;
ipb_sda_i <= fpga_sda_b;
-- SFP control signals for White-Rabit SFP
sfp_mod_def1_b(0) <= '0' when sfp_scl_o(0) = '0' else 'Z';
sfp_mod_def2_b(0) <= '0' when sfp_sda_o(0) = '0' else 'Z';
sfp_scl_i(0) <= sfp_mod_def1_b(0);
sfp_sda_i(0) <= sfp_mod_def2_b(0);
sfp_tx_disable_o(0) <= '0';
one_wire_b <= '0' when owr_en(0) = '1' else 'Z';
owr_i(0) <= one_wire_b;
-- The White Rabbit cores use up space in the FPGA and consume power.
-- Don't build them unless we want them.
generate_whiterabbit: if ( BUILD_WHITERABBIT = 1 ) generate
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
......@@ -431,68 +518,6 @@ begin
O => clk_dmtd,
I => pllout_clk_dmtd);
cmp_clk_vcxo : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
cmp_pllrefclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- Dedicated clock for GTP used for WhiteRabbit
------------------------------------------------------------------------------
cmp_gtp_dedicated_clk_buf0 : IBUFGDS
generic map(
DIFF_TERM => true,
IBUF_LOW_PWR => true,
IOSTANDARD => "DEFAULT")
port map (
O => gtp_dedicated_clk(0),
I => fpga_pll_ref_clk_101_p_i,
IB => fpga_pll_ref_clk_101_n_i
);
------------------------------------------------------------------------------
-- Active high reset
------------------------------------------------------------------------------
process(clk_sys)
begin
if rising_edge(clk_sys) then
led_divider <= led_divider + 1;
end if;
end process;
fpga_scl_b <= '0' when wrc_scl_o = '0' else 'Z';
fpga_sda_b <= '0' when wrc_sda_o = '0' else 'Z';
wrc_scl_i <= fpga_scl_b;
wrc_sda_i <= fpga_sda_b;
-- SFP control signals for White-Rabit SFP
sfp_mod_def1_b(0) <= '0' when sfp_scl_o(0) = '0' else 'Z';
sfp_mod_def2_b(0) <= '0' when sfp_sda_o(0) = '0' else 'Z';
sfp_scl_i(0) <= sfp_mod_def1_b(0);
sfp_sda_i(0) <= sfp_mod_def2_b(0);
sfp_tx_disable_o(0) <= '0';
one_wire_b <= '0' when owr_en(0) = '1' else 'Z';
owr_i(0) <= one_wire_b;
-- The White Rabbit cores use up space in the FPGA and consume power.
-- Don't build them unless we want them.
generate_whiterabbit: if ( BUILD_WHITERABBIT = 1 ) generate
U_WR_CORE : xwr_core
generic map (
g_simulation => 0,
......@@ -643,8 +668,11 @@ begin
end generate generate_whiterabbit_leds;
-- for now always instantiate the White rabbit GTP + interface
-- MAP complains otherwise and I can't figure out why.
U_GTP : wr_gtp_phy_spartan6
-- MAP complains otherwise and I can't figure out how to stop it
-- if we are running in simulation and we don't want WhiteRabbit then
-- we can happily leave it out....
generate_whiterabbit_phy: if ( BUILD_SIMULATED_ETHERNET = 0 ) generate
U_GTP : entity work.wr_gtp_phy_spartan6
generic map (
g_enable_ch0 => 0,
g_enable_ch1 => 1,
......@@ -688,7 +716,7 @@ begin
pad_rxn1_i => sfp_rxn_i(0),
pad_rxp1_i => sfp_rxp_i(0)
);
end generate generate_whiterabbit_phy;
......@@ -711,6 +739,21 @@ begin
-------------------------------------------------------------------------
-- FIXME - s_ipb_rst should be connected to something sensible...
-- BODGE BODGE
p_register_adc_data: process (s_ipb_clk) is
begin -- process p_register_data
if falling_edge(s_ipb_clk) then -- falling clock edge
s_ADC_DAV_d1 <= ADC_DAV_I;
s_OUT_ADC_d1 <= OUT_ADC_I;
end if;
if rising_edge(s_ipb_clk) then -- rising clock edge
s_ADC_DAV_d2 <= s_ADC_DAV_d1;
s_OUT_ADC_d2 <= s_OUT_ADC_d1;
end if;
end process p_register_adc_data;
-- BODGE BODGE - put down in MAROC interface
maroc: entity work.marocInterface
generic map (
......@@ -727,6 +770,7 @@ begin
-- Trigger signals
external_Trigger_i => s_globaltrig_to_fpga,
gpio_Trigger_i => s_gpio_trigger,
trigger_o => s_globaltrig_from_fpga,
-- Pins connected to MAROC
......@@ -738,8 +782,8 @@ begin
MAROC_TRIGGER_I => MAROC_TRIGGER_I,
EN_OTAQ_O => EN_OTAQ_O,
CTEST_O => CTEST_O,
ADC_DAV_I => ADC_DAV_I,
OUT_ADC_I => OUT_ADC_I,
ADC_DAV_I => s_ADC_DAV_d2 , -- ADC_DAV_I,
OUT_ADC_I => s_OUT_ADC_d2 , -- OUT_ADC_I,
START_ADC_N_O => START_ADC_N_O,
RST_ADC_N_O => RST_ADC_N_O,
RST_SC_N_O => RST_SC_N_O,
......@@ -824,12 +868,18 @@ begin
enable_gclk_drive_o <= '1';
enable_globaltrig_drive_o <= '1';
-- FIXME - loop dip_switches to gpio to stop GPIO being optimized away
gpio(3 downto 0) <= dip_switch_i;
-- N.B. connect any GPIO disconnected, unused gpio pins to '0' to stop them being optimized away
gpio(0) <= ADC_DAV_I;
gpio(1) <= OUT_ADC_I;
gpio(2) <= s_ADC_DAV_d1;
gpio(3) <= s_OUT_ADC_d1;
gpio(4) <= si57x_clk;
gpio(5) <= '0';
gpio(6) <= uart_txd;
uart_rxd <= gpio(7);
-- gpio(6) <= uart_txd;
-- uart_rxd <= gpio(7);
gpio(6) <= '0';
s_gpio_trigger <= gpio(7);
-- FIXME - buffer input clock signal to avoid optimiziation
cmp_si57x_buffer : IBUFGDS
......@@ -852,7 +902,8 @@ begin
IPBusInterface_inst : entity work.IPBusInterfaceGTP
GENERIC MAP (
NUM_EXT_SLAVES => c_NMAROC_SLAVES+1 --! Total number of IPBus slave busses = number in MAROC plus one for External IO
NUM_EXT_SLAVES => c_NMAROC_SLAVES+2, --! Total number of IPBus slave busses = number in MAROC plus one for External IO
BUILD_SIMULATED_ETHERNET => BUILD_SIMULATED_ETHERNET
)
PORT MAP (
......@@ -924,7 +975,20 @@ begin
lvds_right_clk_n_b => lvds_right_clk_n_b
);
-----------------------------------------------------------------------------
-- I2C master
-----------------------------------------------------------------------------
i2cMaster_inst: entity work.i2c_master
PORT MAP (
i2c_scl_i => ipb_scl_i,
i2c_sda_i => ipb_sda_i,
ipbus_clk_i => s_ipb_clk,
ipbus_i => s_ipb_wbus(c_NMAROC_SLAVES+1),
ipbus_reset_i => s_ipb_rst,
i2c_scl_enb_o => ipb_scl_o,
i2c_sda_enb_o => ipb_sda_o,
ipbus_o => s_ipb_rbus(c_NMAROC_SLAVES+1)
);
end rtl;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment