Commit 3df8f56d authored by David Cussans's avatar David Cussans

Added external trigger on GPIO. Tidied up firmware. Still doesn't meet timing constraints :-(

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@44 e1591323-3689-4d5a-aa31-d1a7cbdc5706
parent 4608124b
......@@ -16,7 +16,8 @@ end entity fallingEdgeDetect;
architecture rtl of fallingEdgeDetect is
signal level_d1 , level_d2 : std_logic := '0'; -- delayed version of input
signal pulse , pulse_d1 : std_logic := '0'; -- register output.
begin -- architecture rtl
p_levelDetect: process (clk_i) is
......@@ -25,10 +26,13 @@ begin -- architecture rtl
level_d1 <= level_i;
level_d2 <= level_d1;
if (( level_d2 = '1' ) and ( level_d1 = '0')) then
pulse_o <= '1';
pulse <= '1';
else
pulse_o <= '0';
pulse <= '0';
end if;
pulse_d1 <= pulse;
pulse_o <= pulse_d1;
end if;
end process p_levelDetect;
......
......@@ -90,7 +90,7 @@ end ipbusMarocTriggerGenerator;
architecture rtl of ipbusMarocTriggerGenerator is
signal s_internalTrigger_p : std_logic;
signal s_internalTrigger_p ,s_internalTrigger_p_d1 : std_logic;
signal s_triggerSourceSelect : std_logic_vector(3 downto 0) := (others => '0');
signal s_hold1Delay , s_hold2Delay : std_logic_vector(4 downto 0);
......@@ -178,6 +178,9 @@ begin
s_internalTrigger_p <= '0';
ctest_o <= ( others => '0');
end if;
s_internalTrigger_p_d1 <= s_internalTrigger_p;
end if;
end process p_internalTrigger;
......@@ -215,7 +218,7 @@ begin
reset_i => s_counter_reset,
-- conversion_counter_o => s_conversion_counter,
externalTrigger_a_i => externalTrigger_a_i ,
internalTrigger_i => s_internalTrigger_p,
internalTrigger_i => s_internalTrigger_p_d1,
triggerSourceSelect_i=> s_triggerSourceSelect,
hold1Delay_i => s_hold1Delay,
hold2Delay_i => s_hold2Delay,
......
......@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is
begin
ipbus_out.ipb_rdata <= X"a625" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_rdata <= X"a627" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
......
......@@ -56,6 +56,7 @@ entity marocADCFSM is
adc_dav_i : in std_logic; --! "Transmitting data" signal from MAROC
reset_sr_o : out std_logic; --! reset ADC and internal shift reg.
start_adc_n_o : out std_logic; --! Goes low during conversion.
end_of_sequence_o : out std_logic; --! Goes high for one clock cycle immediately after DAV goes low
status_o : out std_logic --! Zero when FSM is idle , one otherwise
);
end marocADCFSM;
......@@ -66,8 +67,10 @@ end marocADCFSM;
architecture rtl of marocADCFSM is
--! Define an enumerated type corresponding to FSM states
type t_state_type is (IDLE , RESETTING , WAIT_FOR_DAV_HIGH , WAIT_FOR_DAV_LOW );
type t_state_type is (IDLE , RESETTING , WAIT_FOR_DAV_HIGH , WAIT_FOR_DAV_LOW , END_OF_READOUT );
signal s_state , s_next_state : t_state_type := IDLE ;
signal s_end_of_sequence , s_status , s_start_adc_n, s_reset_sr: std_logic := '0';
--============================================================================
-- architecture begin
......@@ -88,6 +91,12 @@ begin -- rtl
else
s_state <= s_next_state;
end if;
end_of_sequence_o <= s_end_of_sequence;
status_o <= s_status;
start_adc_n_o <= s_start_adc_n;
reset_sr_o <= s_reset_sr;
end if;
end process p_state_register;
......@@ -119,11 +128,14 @@ begin -- rtl
when WAIT_FOR_DAV_LOW =>
if (adc_dav_i = '0') then
s_next_state <= IDLE;
s_next_state <= END_OF_READOUT;
else
s_next_state <= WAIT_FOR_DAV_LOW;
end if;
when END_OF_READOUT =>
s_next_state <= IDLE;
when others =>
s_next_state <= IDLE;
......@@ -135,12 +147,14 @@ begin -- rtl
--==========================================================================
--! reset goes high-when state=resetting
reset_sr_o <= '1' when s_state = RESETTING else '0';
s_reset_sr <= '1' when s_state = RESETTING else '0';
--! start_adc_n_o goes low during conversion
start_adc_n_o <= '0' when (s_state = WAIT_FOR_DAV_HIGH) or (s_state = WAIT_FOR_DAV_LOW ) else '1';
s_start_adc_n <= '0' when (s_state = WAIT_FOR_DAV_HIGH) or (s_state = WAIT_FOR_DAV_LOW ) else '1';
status_o <= '0' when s_state = IDLE else '1';
s_status <= '0' when s_state = IDLE else '1';
s_end_of_sequence <= '1' when s_state = END_OF_READOUT else '0';
end rtl;
--============================================================================
......
......@@ -133,15 +133,14 @@ begin
--==========================================================================
-- purpose: Shift register to deserialize data from MAROC
-- type : combinational
-- inputs : clk_i , out_adc_i
-- inputs : clk_i , reset_i , out_adc_i
-- outputs: s_shiftReg
--==========================================================================
p_shiftReg: process (clk_i , out_adc_i)
p_shiftReg: process (clk_i , reset_i, out_adc_i)
begin -- process p_shiftReg
if rising_edge(clk_i) then
if (reset_i = '1') then
s_writeAddr <= (others => '0');
s_shiftRegCounter <= (others => '0');
elsif (s_reset_sr='1') then
s_shiftRegCounter <= (others => '0');
......@@ -150,23 +149,30 @@ begin
s_shiftRegCounter <= s_shiftRegCounter + 1;
end if;
-- Increment write address if a complete word has been shifted or if end
-- of ADC readout has been reached.
s_shiftRegFull_d1 <= s_shiftRegFull;
if (s_wen = '1') then
s_writeAddr <= s_writeAddr + 1;
end if;
--! Delay reset shift-reg signal to act as flag for
--! writing timestamp into DPR.
s_reset_sr_d1 <= s_reset_sr;
s_shiftRegFull_d1 <= s_shiftRegFull;
end if; -- rising_edge(clk_i)
end process p_shiftReg;
p_writeAddrControl: process(clk_i , s_wen , reset_i )
begin
if rising_edge(clk_i) then
if (reset_i = '1') then
s_writeAddr <= (others => '0');
elsif (s_wen = '1') then
-- Increment write address if a complete word has been shifted or if end
-- of ADC readout has been reached.
s_writeAddr <= s_writeAddr + 1;
end if;
end if;
end process p_writeAddrControl;
--! Generate write enable for DPRAM ( also increments write address
s_shiftRegFull <= '1' when (s_shiftRegCounter(4 downto 0) = "11111" ) else '0';
......@@ -187,6 +193,7 @@ begin
adc_dav_i => adc_dav_i,
reset_sr_o => s_reset_sr,
start_adc_n_o => start_adc_n_o,
end_of_sequence_o => open,
status_o => status_o
);
......
......@@ -131,7 +131,9 @@ ARCHITECTURE rtl OF marocTriggerGenerator IS
--from output port...
signal s_hold1_d1 : std_logic; --!
signal s_hold1_d2 : std_logic; --!
signal s_hold1_d3 : std_logic; --!
signal s_hold1_d3 : std_logic; --!
signal s_hold1_d4 : std_logic; --!
signal s_hold1_d5 : std_logic; --!
BEGIN
......@@ -226,6 +228,15 @@ BEGIN
D => s_hold1 -- SRL data input
); -- End of SRLC32E_inst instantiation
-- Having timing closure problems with this signal. Put in some more registers....
p_RegisterHold1: process (clk_fast_i, s_hold1)
begin -- process p_RegisterHold1
if rising_edge(clk_fast_i) then -- rising clock edge
s_hold1_d1 <= s_hold1;
s_hold1_d2 <= s_hold1_d1;
end if;
end process p_RegisterHold1;
-- purpose: registers s_hold1 onto system (slow) clock and detect rising edge to form adcConversionStart_o
-- type : sequential
......@@ -235,11 +246,11 @@ BEGIN
begin -- process p_GenerateADCStart
if rising_edge(clk_sys_i) then -- rising clock edge
s_hold1_d1 <= s_hold1;
s_hold1_d2 <= s_hold1_d1;
s_hold1_d3 <= s_hold1_d2;
s_hold1_d4 <= s_hold1_d3;
s_hold1_d5 <= s_hold1_d4;
s_adcConversionStart <= (not s_hold1_d2) and s_hold1_d3 ;
s_adcConversionStart <= (not s_hold1_d4) and s_hold1_d5 ;
end if;
end process p_GenerateADCStart;
......
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......@@ -14,8 +14,8 @@ CONFIG PROHIBIT = Y4;
CONFIG VCCAUX=2.5;
INST "cmp_gtp_dedicated_clk_buf0" LOC = BUFDS_X2Y5;
INST "IPBusInterface_inst/eth/ibuf0" LOC = BUFDS_X1Y5;
INST "IPBusInterface_inst/eth/phy/transceiver_inst/GTP_1000X/tile0_s6_gtpwizard_i/gtpa1_dual_i" LOC = GTPA1_DUAL_X0Y1;
INST "IPBusInterface_inst/generate_physicalmac.eth/ibuf0" LOC = BUFDS_X1Y5;
INST "IPBusInterface_inst/generate_physicalmac.eth/phy/transceiver_inst/GTP_1000X/tile0_s6_gtpwizard_i/gtpa1_dual_i" LOC = GTPA1_DUAL_X0Y1;
# INST "U_GTP/U_GTP_TILE_INST/gtpa1_dual_i" LOC = GTPA1_DUAL_X1Y1;
NET "ADC_DAV_I" IOSTANDARD = SSTL2_I;
......@@ -142,6 +142,7 @@ NET "GPIO[6]" LOC = F1;
NET "GPIO[6]" SLEW = SLOW;
NET "GPIO[7]" IOSTANDARD = LVCMOS33;
NET "GPIO[7]" LOC = F5;
NET "GPIO[7]" PULLDOWN=true;
NET "HOLD1_O" DRIVE = 12;
NET "HOLD1_O" IOSTANDARD = LVCMOS33;
NET "HOLD1_O" LOC = Y2;
......@@ -464,10 +465,10 @@ NET "one_wire_b" DRIVE = 12;
NET "one_wire_b" IOSTANDARD = LVCMOS33;
NET "one_wire_b" LOC = T5;
NET "one_wire_b" SLEW = SLOW;
NET "OR_I[0]" IOSTANDARD = SSTL2_I;
NET "OR_I[0]" LOC = N6;
NET "OR_I[1]" IOSTANDARD = SSTL2_I;
NET "OR_I[1]" LOC = P6;
NET "OR_I[1]" LOC = N6;
NET "OR_I[2]" IOSTANDARD = SSTL2_I;
NET "OR_I[2]" LOC = P6;
NET "OUT_ADC_I" IOSTANDARD = SSTL2_I;
NET "OUT_ADC_I" LOC = W3;
NET "pll25dac1_sync_n_o" DRIVE = 12;
......@@ -486,10 +487,10 @@ NET "pll25dac_sclk_o" DRIVE = 12;
NET "pll25dac_sclk_o" IOSTANDARD = LVCMOS33;
NET "pll25dac_sclk_o" LOC = P1;
NET "pll25dac_sclk_o" SLEW = SLOW;
NET "Q_R_I_IBUF" IOSTANDARD = LVCMOS33;
#NET "Q_R_I_IBUF" IOSTANDARD = LVCMOS33;
NET "Q_R_I" IOSTANDARD = LVCMOS33;
NET "Q_R_I" LOC = U1;
NET "Q_SC_I_IBUF" IOSTANDARD = LVCMOS33;
#NET "Q_SC_I_IBUF" IOSTANDARD = LVCMOS33;
NET "Q_SC_I" IOSTANDARD = LVCMOS33;
NET "Q_SC_I" LOC = U3;
NET "RST_ADC_N_O" DRIVE = 12;
......@@ -499,12 +500,12 @@ NET "RST_ADC_N_O" SLEW = SLOW;
NET "RST_R_N_O" DRIVE = 12;
NET "RST_R_N_O" IOSTANDARD = LVCMOS33;
NET "RST_R_N_O" LOC = Y1;
NET "RST_R_N_O_OBUF" IOSTANDARD = LVCMOS33;
#NET "RST_R_N_O_OBUF" IOSTANDARD = LVCMOS33;
NET "RST_R_N_O" SLEW = SLOW;
NET "RST_SC_N_O" DRIVE = 12;
NET "RST_SC_N_O" IOSTANDARD = LVCMOS33;
NET "RST_SC_N_O" LOC = U4;
NET "RST_SC_N_O_OBUF" IOSTANDARD = LVCMOS33;
#NET "RST_SC_N_O_OBUF" IOSTANDARD = LVCMOS33;
NET "RST_SC_N_O" SLEW = SLOW;
NET "sata_rxp_i[0]" LOC = D13;
NET "sata_rxn_i[1]" LOC = C9;
......@@ -589,4 +590,15 @@ TIMESPEC TS_fpga_pll_ref_clk_123_p_i = PERIOD "fpga_pll_ref_clk_123_p_i" 125 MHz
TIMESPEC TS_lvds_left_clk_p_b = PERIOD "lvds_left_clk_p_b" 125 MHz HIGH 50 %;
TIMESPEC TS_lvds_right_clk_p_b = PERIOD "lvds_right_clk_p_b" 125 MHz HIGH 50 %;
NET "IPBusInterface_inst/clocks/rst" TIG;
\ No newline at end of file
# Don't care about the timing of these signals w.r.t. clock, since they are static during data acqusition
NET "*s_triggerSourceSelect*" TIG;
NET "*s_hold1Delay*" TIG;
NET "*s_hold2Delay*" TIG;
# Don't care about timing of reset signal
NET "IPBusInterface_inst/generate_physicalmac.clocks/rst*" TIG;
NET "maroc/slave2_trigger/s_counter_reset_ipb" TIG;
# Bodge, bodge
NET "maroc/slave5_triggerCounter/*reset*" TIG;
NET "maroc/slave5_triggerCounter/inst_sync_reg/*ring*" TIG;
NET "maroc/slave5_triggerCounter/inst_sync_reg/*data*" TIG;
\ No newline at end of file
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