rx: is being reset during transmission

also small correction on the rx_regs

rx: is being reset during transmission
also small correction on the rx_regs
269d2738 · Evangelia Gousiou · 92060d6f · 269d2738 · 269d2738 · 269d2738
Commit 269d2738 authored Jul 22, 2015 by Evangelia Gousiou
5 changed files
--- a/rtl/fmc_masterFIP_core.vhd
+++ b/rtl/fmc_masterFIP_core.vhd
@@ -130,7 +130,7 @@ architecture rtl of fmc_masterFIP_core is
  signal tx_frame : tx_frame_t;
  signal tx_ctrl_byte : std_logic_vector (7 downto 0);
  -- rx
-  signal rx_pream_ok, rx_frame_ok_p : std_logic;
+  signal rx_pream_ok, rx_frame_ok_p, fd_txena : std_logic;
  signal rx_frame : rx_frame_t;
  signal rx_ctrl_byte : std_logic_vector (7 downto 0);
  
@@ -185,11 +185,11 @@ begin
    mf_rst_lock_o                        => core_sw_rstn_lock,
    mf_rst_lock_wr_o                     => core_sw_rst_p,
    -- config
-    mf_config_host_bitrate_o             => open,
+    mf_config_host_bitrate_o             => open,--host_bitrate_conf,
    mf_config_host_ext_sync_term_en_n_o  => open,
    mf_config_host_subs_o                => open,
-    mf_config_fmc_bitrate_i              => "01",
-    mf_config_fmc_bitrate_ok_i           => '1',
+    mf_config_fmc_bitrate_i              => "01",--fmc_bitrate_conf,
+    mf_config_fmc_bitrate_ok_i           => '1', --bitrate_ok,
    -- counters outputs
    mf_macrocyc_lgth_o                   => macrocyc_lgth,
    mf_macrocyc_start_o                  => macrocyc_sw_load,
@@ -420,7 +420,7 @@ begin
    core_rst_i            => core_rst,
    rate_i                => "01",
    fd_rxd_a_i            => fd_rxd_i,
-    rx_rst_i              => rx_rst,
+    rx_rst_i              => rx_rst or fd_txena,
  -------------------------------------------------------------
    rx_byte_index_o       => rx_byte_index, -- should have the amount of bytes
    rx_ctrl_byte_o        => rx_ctrl_byte,
@@ -450,10 +450,10 @@ begin
    tx_byte_index_o            => tx_byte_index,
    tx_completed_p_o           => tx_completed_p,
    tx_data_o                  => fd_txd_o,
-    tx_enable_o                => fd_txena_o,
+    tx_enable_o                => fd_txena,
    tx_clk_o                   => fd_txck_o);
  -------------------------------------------------------------
-
+fd_txena_o <= fd_txena;

 ---------------------------------------------------------------------------------------------------
 --                                              irqs                                             --

--- a/rtl/masterfip_rx.vhd
+++ b/rtl/masterfip_rx.vhd
@@ -146,7 +146,7 @@ architecture struc of masterfip_rx is
  signal byte0, byte1, byte2, byte3                              : std_logic_vector(7 downto 0);
  signal word32                                                  : std_logic_vector(31 downto 0);
  signal word32_num                                              : integer range 0 to 31;
-  signal rx_byte_index                                           : unsigned(7 downto 0);
+  signal rx_byte_index, rx_byte_index_d1                         : unsigned(7 downto 0);
  signal bytes_c_rst                                             : std_logic;


@@ -237,7 +237,7 @@ begin
    counter_o         => rx_byte_index);
    -------------------------------------------------------

-  bytes_c_rst  <= '1' when (core_rst_i = '1' or rx_rst_i = '1') else '0';
+  bytes_c_rst     <= '1' when (core_rst_i = '1' or rx_rst_i = '1') else '0';
  rx_byte_index_o <= std_logic_vector(rx_byte_index);

  
@@ -276,16 +276,31 @@ begin
 ---------------------------------------------------------------------------------------------------
 -- Synchronous process Data_Transfer_To_Regs: transfer 32bit words to the cons_frame registers

+  delay: process (uclk_i)
+  begin
+    if rising_edge (uclk_i) then
+      if core_rst_i = '1' or rx_rst_i = '1' then
+        rx_byte_index_d1   <= (others =>'0'); -- needed for synching
+      else
+        if rx_byte_ready_p = '1' then
+          rx_byte_index_d1       <= rx_byte_index; 
+        end if;
+      end if;
+    end if;
+  end process;
+
+
+
  data_transfer_to_regs: process (uclk_i)
  begin
    if rising_edge (uclk_i) then
      if core_rst_i = '1' or rx_rst_i = '1' then
-        word32_num      <= 0;
-        rx_frame_o      <= (others =>(others =>'0'));
+        word32_num         <= 0;
+        rx_frame_o         <= (others =>(others =>'0'));
        else
-        if rx_byte_ready_p = '1' and (rx_byte_index) > 0 and (rx_byte_index) mod 4 = 0 then
-          word32_num             <= word32_num + 1;
-          rx_frame_o(word32_num) <= word32;
+          if rx_byte_ready_p = '1' and (rx_byte_index_d1) > 0 and (rx_byte_index_d1) mod 4 = 0 then
+            word32_num             <= word32_num + 1;
+            rx_frame_o(word32_num) <= word32;
          end if;
      end if;
    end if;

--- a/sim/spec/data_vectors/masterFIP_test.vec
+++ b/sim/spec/data_vectors/masterFIP_test.vec
@@ -55,36 +55,40 @@ wr 0000000000050010 F 80007D00
 wait   %d20

 --------------- ID_DAT ---------------
-- control byte of id_dat
-wr 00000000000500C0 F 00000003
+tx_rst
+wr 000000000005002C F 00000001
+wait   %d10
+wr 000000000005002C F 00000000
 wait   %d20

-- data bytes varid = 0503 for agent to consume
-wr 00000000000500C4 F 00000305
+-- control byte of id_dat
+wr 00000000000500C4 F 00000003
 wait   %d20

-- rx_rst
-wr 0000000000050038 F 00000001
+-- data bytes varid = 0503 for agent to consume
+wr 00000000000500C8 F 00000305
 wait   %d20

 -- tx_start
 wr 000000000005002C F 00000202
 wait   %d20000

-- deactivate tx_start and reset tx
+
+--------------- RP_DAT ---------------
+tx_rst
 wr 000000000005002C F 00000001
+wait   %d10
+wr 000000000005002C F 00000000
 wait   %d20

-
--------------- RP_DAT ---------------
 -- control byte of rp_dat
 wr 00000000000500c4 F 00000002
 wait   %d20

 -- data bytes
-wr 00000000000500c8 F 02010F40
+wr 00000000000500c8 F BBAA0340
 wait   %d20
-wr 00000000000500cc F 06050403
+wr 00000000000500cc F EEDDCC05
 wait   %d20
 wr 00000000000500d0 F 0A090807
 wait   %d20
@@ -94,14 +98,17 @@ wr 00000000000500D8 F 06060605
 wait   %d20

 -- tx_start
-wr 000000000005002C F 00001102
+wr 000000000005002C F 00000502
 wait   %d40000

-- deactivate tx_start and reset tx
+
+--------------- ID_DAT ---------------
+tx_rst
 wr 000000000005002C F 00000001
+wait   %d10
+wr 000000000005002C F 00000000
 wait   %d20

--------------- ID_DAT ---------------
 -- control byte of id_dat
 wr 00000000000500c4 F 00000003
 wait   %d20

--- a/syn/spec/spec_masterFIP.xise
+++ b/syn/spec/spec_masterFIP.xise
@@ -872,6 +872,9 @@
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
    </file>
+    <file xil_pn:name="../../top/spec/spec_masterFIP.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
  </files>

  <properties>
@@ -1200,7 +1203,9 @@
    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
  </properties>

-  <bindings/>
+  <bindings>
+    <binding xil_pn:location="/spec_masterFIP" xil_pn:name="../../top/spec/spec_masterFIP.ucf"/>
+  </bindings>

  <libraries/>


--- a/top/spec/spec_masterFIP.ucf
+++ b/top/spec/spec_masterFIP.ucf
@@ -48,13 +48,13 @@ NET "fd_wdgn_i" IOSTANDARD = "LVCMOS25";
 NET "fd_txena_o" LOC = "Y10";
 NET "fd_txena_o" IOSTANDARD = "LVCMOS25";

-NET "mezz_onewire_b" LOC = "A19";
-NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
+#NET "mezz_onewire_b" LOC = "A19";
+#NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
 # <ucfgen_end>
-NET "mezz_sys_scl_b" LOC = "F7";
-NET "mezz_sys_scl_b" IOSTANDARD = "LVCMOS25";
-NET "mezz_sys_sda_b" LOC = "F8";
-NET "mezz_sys_sda_b" IOSTANDARD = "LVCMOS25";
+#NET "mezz_sys_scl_b" LOC = "F7";
+#NET "mezz_sys_scl_b" IOSTANDARD = "LVCMOS25";
+#NET "mezz_sys_sda_b" LOC = "F8";
+#NET "mezz_sys_sda_b" IOSTANDARD = "LVCMOS25";


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