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MasterFIP - Gateware
Commits
2d1384e2
Commit
2d1384e2
authored
Oct 06, 2015
by
Tomasz Wlostowski
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larger memory sizes for the CPUs, wider HMQ slots, new version of GN4124 core
parent
990531ec
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3 changed files
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53 additions
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50 deletions
+53
-50
wr-node-core
ip_cores/wr-node-core
+1
-1
spec_masterfip_wrnode.xise
syn/spec_wrnode/spec_masterfip_wrnode.xise
+42
-39
spec_top.vhd
top/spec_wrnode/spec_top.vhd
+10
-10
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wr-node-core
@
640255a3
Subproject commit
7e8e9c3f584e283ac5ac321e4730c35d5038ee82
Subproject commit
640255a327d240741ac0efdbd649b6b2fc7788e3
syn/spec_wrnode/spec_masterfip_wrnode.xise
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2d1384e2
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top/spec_wrnode/spec_top.vhd
View file @
2d1384e2
...
...
@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2015-
08-14
-- Last update: 2015-
10-06
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
...
...
@@ -153,16 +153,16 @@ architecture rtl of spec_top is
(
out_slot_count
=>
4
,
out_slot_config
=>
(
0
=>
(
width
=>
128
,
entries
=>
8
),
-- control CPU 0 (to host)
1
=>
(
width
=>
128
,
entries
=>
8
),
-- control CPU 1 (to host)
2
=>
(
width
=>
1
6
,
entries
=>
128
),
-- log CPU 0
3
=>
(
width
=>
1
6
,
entries
=>
128
),
-- log CPU 1
0
=>
(
width
=>
128
,
entries
=>
4
),
-- control CPU 0 (to host)
1
=>
(
width
=>
128
,
entries
=>
4
),
-- control CPU 1 (to host)
2
=>
(
width
=>
1
28
,
entries
=>
4
),
-- log CPU 0
3
=>
(
width
=>
1
28
,
entries
=>
4
),
-- log CPU 1
others
=>
(
0
,
0
)),
in_slot_count
=>
2
,
in_slot_config
=>
(
0
=>
(
width
=>
32
,
entries
=>
8
),
-- control CPU 0 (from host)
1
=>
(
width
=>
32
,
entries
=>
8
),
-- control CPU 1 (from host)
0
=>
(
width
=>
128
,
entries
=>
4
),
-- control CPU 0 (from host)
1
=>
(
width
=>
128
,
entries
=>
4
),
-- control CPU 1 (from host)
others
=>
(
0
,
0
)
)
);
...
...
@@ -176,12 +176,12 @@ architecture rtl of spec_top is
(
out_slot_count
=>
1
,
out_slot_config
=>
(
0
=>
(
width
=>
128
,
entries
=>
16
),
-- TDC remote out
0
=>
(
width
=>
128
,
entries
=>
4
),
-- TDC remote out
others
=>
(
0
,
0
)),
in_slot_count
=>
1
,
in_slot_config
=>
(
0
=>
(
width
=>
128
,
entries
=>
16
),
-- FD remote in
0
=>
(
width
=>
128
,
entries
=>
4
),
-- FD remote in
others
=>
(
0
,
0
)
)
...
...
@@ -191,7 +191,7 @@ architecture rtl of spec_top is
(
app_id
=>
x"0f1dc03e"
,
cpu_count
=>
2
,
cpu_memsizes
=>
(
32768
,
32768
,
0
,
0
,
0
,
0
,
0
,
0
),
cpu_memsizes
=>
(
65536
,
65536
,
0
,
0
,
0
,
0
,
0
,
0
),
hmq_config
=>
c_hmq_config
,
rmq_config
=>
c_rmq_config
,
shared_mem_size
=>
65536
...
...
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