Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
M
MasterFIP - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
MasterFIP - Gateware
Commits
34a46a24
Commit
34a46a24
authored
Oct 16, 2015
by
Evangelia Gousiou
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
WRNC and masterFIP_core at 40MHz
parent
ceb6ff76
Hide whitespace changes
Inline
Side-by-side
Showing
5 changed files
with
84 additions
and
84 deletions
+84
-84
wf_package.vhd
rtl/from_nanofip/wf_package.vhd
+2
-2
tb_masterFIP.vhd
sim/spec/testbench/tb_masterFIP.vhd
+1
-1
spec_masterFIP.xise
syn/spec/spec_masterFIP.xise
+78
-78
spec_masterFIP.vhd
top/spec/spec_masterFIP.vhd
+2
-2
spec_top.vhd
top/spec_wrnode/spec_top.vhd
+1
-1
No files found.
rtl/from_nanofip/wf_package.vhd
View file @
34a46a24
...
...
@@ -66,7 +66,7 @@ package wf_package is
-- Constant regarding the user clock --
---------------------------------------------------------------------------------------------------
constant
c_QUARTZ_PERIOD
:
real
:
=
10
.
0
;
----------***-----25
constant
c_QUARTZ_PERIOD
:
real
:
=
25
.
0
;
...
...
@@ -267,7 +267,7 @@ package wf_package is
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
constant
c_PERIODS_COUNTER_LGTH
:
natural
:
=
1
3
;
-- in the slowest bit rate (31.25kbps), the -------***---------- 11
constant
c_PERIODS_COUNTER_LGTH
:
natural
:
=
1
1
;
-- in the slowest bit rate (31.25kbps), the
-- period is 32000 ns and can be measured after
-- 1280 uclk ticks. Therefore a counter of 11
-- bits is the max needed for counting
...
...
sim/spec/testbench/tb_masterFIP.vhd
View file @
34a46a24
...
...
@@ -240,7 +240,7 @@ constant pll_clk_period : time:= 8 ns;
constant
g_width
:
integer
:
=
32
;
constant
g_span
:
integer
:
=
32
;
constant
spec_clk_period
:
time
:
=
50
ns
;
signal
nanoFIP_clk_period
:
time
:
=
10
ns
;
-------***-------- 25
signal
nanoFIP_clk_period
:
time
:
=
25
ns
;
constant
start_retrig_period
:
time
:
=
512
ns
;
-- Number of Models receiving commands
...
...
syn/spec/spec_masterFIP.xise
View file @
34a46a24
...
...
@@ -17,11 +17,11 @@
<files>
<file
xil_pn:name=
"../../rtl/carrier_info.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"72"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
51
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
72
"
/>
</file>
<file
xil_pn:name=
"../../rtl/decr_counter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"42"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
3
2"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
2"
/>
</file>
<file
xil_pn:name=
"../../rtl/free_counter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -61,7 +61,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"57"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
7"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
5
7"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -113,7 +113,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"12"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -121,43 +121,43 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"44"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
3
4"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
4"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"53"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
3"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
5
3"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"28"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
8
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"52"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
2"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
5
2"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"51"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
1"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
5
1"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"50"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
0"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
5
0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"49"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
3
9"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
9"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"75"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
54
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
75
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"56"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
6"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
5
6"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"55"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
5"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
5
5"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -181,19 +181,19 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"74"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
53
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
74
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
xil_pn:type=
"FILE_VERILOG"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"30"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
27
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
30
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"54"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
4"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
5
4"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"29"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
9
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -233,7 +233,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"11"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
1
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -301,7 +301,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"23"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
3
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -309,7 +309,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"43"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
3
3"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
3"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -329,7 +329,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"10"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
9
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
10
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -345,7 +345,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"22"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
19
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
22
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -481,7 +481,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"21"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
18
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
21
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -629,39 +629,39 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"24"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
4
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"73"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
52
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
73
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"27"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
7
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"48"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
3
8"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
8"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"47"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
3
7"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
7"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"46"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
3
6"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
6"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"45"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
3
5"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
5"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"26"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
6
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"25"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
5
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc"
xil_pn:type=
"FILE_NGC"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
...
...
@@ -671,23 +671,23 @@
</file>
<file
xil_pn:name=
"../../top/spec/spec_reset_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"59"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
9"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
5
9"
/>
</file>
<file
xil_pn:name=
"../../top/spec/synthesis_descriptor.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"58"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
8"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
5
8"
/>
</file>
<file
xil_pn:name=
"../../rtl/fmc_masterFIP_core.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"71"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
50
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
71
"
/>
</file>
<file
xil_pn:name=
"../../rtl/masterFIP_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"15"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
2
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
5
"
/>
</file>
<file
xil_pn:name=
"../../top/spec/spec_masterFIP.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"76"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
55
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
76
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -699,47 +699,47 @@
</file>
<file
xil_pn:name=
"../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"31"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
28
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
31
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/tb_masterFIP.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"80"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
8
0"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/gnum_model/util.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"14"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
14
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/gnum_model/cmd_router.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"79"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
79
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/gnum_model/gn412x_bfm.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"78"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
78
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/gnum_model/mem_model.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"69"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
69
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/gnum_model/textutil.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"38"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
38
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/dualram_512x8.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"6"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
6
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/nanofip.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"77"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
77
"
/>
</file>
<file
xil_pn:name=
"../../rtl/fmc_masterfip_csr.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"41"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
3
1"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
1"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/gnum_model/cmd_router1.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"70"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
7
0"
/>
</file>
<file
xil_pn:name=
"../../rtl/fmc_masterfip_eic.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -747,47 +747,47 @@
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_wb_controller.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"60"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
6
0"
/>
</file>
<file
xil_pn:name=
"../../rtl/from_nanofip/wf_crc.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"9"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
8
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
9
"
/>
</file>
<file
xil_pn:name=
"../../rtl/from_nanofip/wf_decr_counter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"8"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
7
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
8
"
/>
</file>
<file
xil_pn:name=
"../../rtl/from_nanofip/wf_incr_counter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"7"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
7
"
/>
</file>
<file
xil_pn:name=
"../../rtl/from_nanofip/wf_rx_deglitcher.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"20"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
17
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
20
"
/>
</file>
<file
xil_pn:name=
"../../rtl/from_nanofip/wf_rx_osc.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"18"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
5
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
8
"
/>
</file>
<file
xil_pn:name=
"../../rtl/from_nanofip/wf_tx_osc.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"17"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
4
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
7
"
/>
</file>
<file
xil_pn:name=
"../../rtl/masterfip_tx.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"39"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
2
9"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
3
9"
/>
</file>
<file
xil_pn:name=
"../../rtl/from_nanofip/wf_rx_deserializer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"19"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
6
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
9
"
/>
</file>
<file
xil_pn:name=
"../../rtl/from_nanofip/wf_tx_serializer.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"16"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
3
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"1
6
"
/>
</file>
<file
xil_pn:name=
"../../rtl/masterfip_rx.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"40"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
3
0"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
4
0"
/>
</file>
<file
xil_pn:name=
"../../rtl/from_nanofip/wf_package.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"2"
/>
...
...
@@ -795,63 +795,63 @@
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_cons_bytes_processor.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"37"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
37
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_cons_outcome.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"36"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
36
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_consumption.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"68"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
68
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_dualram_512x8_clka_rd_clkb_wr.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"13"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
13
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_engine_control.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"67"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
67
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_fd_receiver.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"66"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
66
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_fd_transmitter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"65"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
65
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_jtag_controller.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"64"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
64
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_model_constr_decoder.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"63"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
63
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_prod_bytes_retriever.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"35"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
35
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_prod_data_lgth_calc.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"34"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
34
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_prod_permit.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"33"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
33
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_production.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"62"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
62
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_reset_unit.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"61"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
61
"
/>
</file>
<file
xil_pn:name=
"../../sim/spec/testbench/nanoFIP/wf_status_bytes_gen.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"32"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
0
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
32
"
/>
</file>
<file
xil_pn:name=
"../../top/spec/spec_masterFIP.ucf"
xil_pn:type=
"FILE_UCF"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
...
...
@@ -1132,8 +1132,8 @@
<property
xil_pn:name=
"Run for Specified Time Translate"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Safe Implementation"
xil_pn:value=
"No"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Security"
xil_pn:value=
"Enable Readback and Reconfiguration"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Module Instance Name"
xil_pn:value=
"/tb_masterFIP
/dut
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Behavioral"
xil_pn:value=
"work.
spec
_masterFIP"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Module Instance Name"
xil_pn:value=
"/tb_masterFIP"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Behavioral"
xil_pn:value=
"work.
tb
_masterFIP"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Route"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Translate"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
...
...
@@ -1151,7 +1151,7 @@
<property
xil_pn:name=
"Simulator"
xil_pn:value=
"ISim (VHDL/Verilog)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Slice Utilization Ratio"
xil_pn:value=
"100"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify 'define Macro Name and Value"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Behavioral"
xil_pn:value=
"work.
spec
_masterFIP"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Behavioral"
xil_pn:value=
"work.
tb
_masterFIP"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Map"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Route"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Translate"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
...
...
top/spec/spec_masterFIP.vhd
View file @
34a46a24
...
...
@@ -281,10 +281,10 @@ begin
DIVCLK_DIVIDE
=>
1
,
CLKFBOUT_MULT
=>
50
,
CLKFBOUT_PHASE
=>
0
.
000
,
CLKOUT0_DIVIDE
=>
10
,
-- 40 MHz ----***---- 25
CLKOUT0_DIVIDE
=>
25
,
-- 40 MHz
CLKOUT0_PHASE
=>
0
.
000
,
CLKOUT0_DUTY_CYCLE
=>
0
.
500
,
CLKOUT1_DIVIDE
=>
8
,
-- 125 MHz, not used
CLKOUT1_DIVIDE
=>
8
,
-- 125 MHz, not used
CLKOUT1_PHASE
=>
0
.
000
,
CLKOUT1_DUTY_CYCLE
=>
0
.
500
,
CLKOUT2_DIVIDE
=>
16
,
...
...
top/spec_wrnode/spec_top.vhd
View file @
34a46a24
...
...
@@ -241,7 +241,7 @@ begin
g_with_wr_phy
=>
false
,
g_with_white_rabbit
=>
false
,
g_double_wrnode_core_clock
=>
false
,
g_system_clock_freq
=>
100000000
,
-------***-------
g_system_clock_freq
=>
40000000
,
-- 40MHz clock
g_wr_node_config
=>
c_node_config
)
port
map
(
rst_n_sys_o
=>
rst_n_sys
,
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment