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MasterFIP - Gateware
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MasterFIP - Gateware
Commits
34a46a24
Commit
34a46a24
authored
Oct 16, 2015
by
Evangelia Gousiou
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WRNC and masterFIP_core at 40MHz
parent
ceb6ff76
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5 changed files
with
84 additions
and
84 deletions
+84
-84
wf_package.vhd
rtl/from_nanofip/wf_package.vhd
+2
-2
tb_masterFIP.vhd
sim/spec/testbench/tb_masterFIP.vhd
+1
-1
spec_masterFIP.xise
syn/spec/spec_masterFIP.xise
+78
-78
spec_masterFIP.vhd
top/spec/spec_masterFIP.vhd
+2
-2
spec_top.vhd
top/spec_wrnode/spec_top.vhd
+1
-1
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rtl/from_nanofip/wf_package.vhd
View file @
34a46a24
...
@@ -66,7 +66,7 @@ package wf_package is
...
@@ -66,7 +66,7 @@ package wf_package is
-- Constant regarding the user clock --
-- Constant regarding the user clock --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
constant
c_QUARTZ_PERIOD
:
real
:
=
10
.
0
;
----------***-----25
constant
c_QUARTZ_PERIOD
:
real
:
=
25
.
0
;
...
@@ -267,7 +267,7 @@ package wf_package is
...
@@ -267,7 +267,7 @@ package wf_package is
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
constant
c_PERIODS_COUNTER_LGTH
:
natural
:
=
1
3
;
-- in the slowest bit rate (31.25kbps), the -------***---------- 11
constant
c_PERIODS_COUNTER_LGTH
:
natural
:
=
1
1
;
-- in the slowest bit rate (31.25kbps), the
-- period is 32000 ns and can be measured after
-- period is 32000 ns and can be measured after
-- 1280 uclk ticks. Therefore a counter of 11
-- 1280 uclk ticks. Therefore a counter of 11
-- bits is the max needed for counting
-- bits is the max needed for counting
...
...
sim/spec/testbench/tb_masterFIP.vhd
View file @
34a46a24
...
@@ -240,7 +240,7 @@ constant pll_clk_period : time:= 8 ns;
...
@@ -240,7 +240,7 @@ constant pll_clk_period : time:= 8 ns;
constant
g_width
:
integer
:
=
32
;
constant
g_width
:
integer
:
=
32
;
constant
g_span
:
integer
:
=
32
;
constant
g_span
:
integer
:
=
32
;
constant
spec_clk_period
:
time
:
=
50
ns
;
constant
spec_clk_period
:
time
:
=
50
ns
;
signal
nanoFIP_clk_period
:
time
:
=
10
ns
;
-------***-------- 25
signal
nanoFIP_clk_period
:
time
:
=
25
ns
;
constant
start_retrig_period
:
time
:
=
512
ns
;
constant
start_retrig_period
:
time
:
=
512
ns
;
-- Number of Models receiving commands
-- Number of Models receiving commands
...
...
syn/spec/spec_masterFIP.xise
View file @
34a46a24
This diff is collapsed.
Click to expand it.
top/spec/spec_masterFIP.vhd
View file @
34a46a24
...
@@ -281,7 +281,7 @@ begin
...
@@ -281,7 +281,7 @@ begin
DIVCLK_DIVIDE
=>
1
,
DIVCLK_DIVIDE
=>
1
,
CLKFBOUT_MULT
=>
50
,
CLKFBOUT_MULT
=>
50
,
CLKFBOUT_PHASE
=>
0
.
000
,
CLKFBOUT_PHASE
=>
0
.
000
,
CLKOUT0_DIVIDE
=>
10
,
-- 40 MHz ----***---- 25
CLKOUT0_DIVIDE
=>
25
,
-- 40 MHz
CLKOUT0_PHASE
=>
0
.
000
,
CLKOUT0_PHASE
=>
0
.
000
,
CLKOUT0_DUTY_CYCLE
=>
0
.
500
,
CLKOUT0_DUTY_CYCLE
=>
0
.
500
,
CLKOUT1_DIVIDE
=>
8
,
-- 125 MHz, not used
CLKOUT1_DIVIDE
=>
8
,
-- 125 MHz, not used
...
...
top/spec_wrnode/spec_top.vhd
View file @
34a46a24
...
@@ -241,7 +241,7 @@ begin
...
@@ -241,7 +241,7 @@ begin
g_with_wr_phy
=>
false
,
g_with_wr_phy
=>
false
,
g_with_white_rabbit
=>
false
,
g_with_white_rabbit
=>
false
,
g_double_wrnode_core_clock
=>
false
,
g_double_wrnode_core_clock
=>
false
,
g_system_clock_freq
=>
100000000
,
-------***-------
g_system_clock_freq
=>
40000000
,
-- 40MHz clock
g_wr_node_config
=>
c_node_config
)
g_wr_node_config
=>
c_node_config
)
port
map
(
port
map
(
rst_n_sys_o
=>
rst_n_sys
,
rst_n_sys_o
=>
rst_n_sys
,
...
...
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