Skip to content

M
MasterFIP - Gateware
Commit 3de128f4 authored by Evangelia Gousiou's avatar Evangelia Gousiou
Browse files
Options

updated to latest MT core; changed ip_core branch; code cleanup

parent a6c43633
Show whitespace changes
Inline Side-by-side
Showing with 3582 additions and 3602 deletions
.gitmodules
View file @ 3de128f4
[submodule "ip_cores/wr-node-core"]
path = ip_cores/wr-node-core
url = git://ohwr.org/white-rabbit/wr-node-core.git
[submodule "ip_cores/general-cores"]
path = ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
general-cores @ 9a40120b
Subproject commit 8915ade1685e0af62b93ff178ebbc2023c3edd09
Subproject commit 9a40120ba4af4a7551f9fd8cbbe61f1d434f30bf
wr-node-core @ c13bc43e
Subproject commit 57feacea81ddf573180b6694e06c428838142d6e
Subproject commit c13bc43e88febd74b5eaa9c5d85675d6b28671cd
rtl/fmc_masterFIP_core.vhd
View file @ 3de128f4
......@@ -154,7 +154,7 @@ entity fmc_masterFIP_core is
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enable 50 Ohms termination of the pulse
ext_sync_dir_o : out std_logic; -- transceiver direction
ext_sync_oe_o : out std_logic; -- transceiver output enable
ext_sync_oe_n_o : out std_logic; -- transceiver output enable negative
ext_sync_tst_n_o : out std_logic; -- emulation of the LEMO input
ext_sync_i : in std_logic; -- sync pulse
......@@ -245,7 +245,8 @@ architecture rtl of fmc_masterFIP_core is
signal sync_led, out_of_sync_led : std_logic;
-- debug
signal mf_dbg : std_logic_vector(31 downto 0);
signal mf_dbg_p, mf_dbg_p_ext : std_logic;
signal mf_dbg_p, mf_dbg_p_ext, macrocyc_cnt_zero, macrocyc_cnt_twentyfive, macrocyc_cnt_twentyfive_p : std_logic;
-- chipscope
-- component chipscope_ila
......@@ -303,14 +304,6 @@ begin
adc_prim_conn_n_o <= '0' when reg_from_mt.adc_prim_conn_n_o = '0' else 'Z';
---------------------------------------------------------------------------------------------------
-- EXT SYNC PULSE --
---------------------------------------------------------------------------------------------------
ext_sync_tst_n_o <= '0' when reg_from_mt.ext_sync_tst_n_o = '0' else 'Z';
ext_sync_dir_o <= reg_from_mt.ext_sync_dir_o;
ext_sync_term_en_o <= reg_from_mt.ext_sync_term_en_o;
---------------------------------------------------------------------------------------------------
-- speed --
---------------------------------------------------------------------------------------------------
......@@ -341,6 +334,12 @@ begin
---------------------------------------------------------------------------------------------------
-- external sync --
---------------------------------------------------------------------------------------------------
ext_sync_tst_n_o <= '0' when reg_from_mt.ext_sync_tst_n_o = '0' else 'Z';
ext_sync_dir_o <= reg_from_mt.ext_sync_dir_o;
ext_sync_term_en_o <= reg_from_mt.ext_sync_term_en_o;
ext_sync_oe_n_o <= reg_from_mt.ext_sync_oe_n_o;
-- input synchronizer of the ext_sync_i signal
cmp_ext_sync_sync: gc_sync_ffs
port map
......@@ -750,7 +749,7 @@ begin
-- drivers. Note that a temperature reading is provided every second, with the first one a couple
-- of sec after the board power-up/ reset.
cmp_onewire: onewire_interf --gc_ds182x_interface
cmp_onewire: gc_ds182x_interface
generic map (freq => 100)
port map
(clk_i => clk_i,
......@@ -808,7 +807,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
(g_width => 10000)--1000000
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -816,16 +815,25 @@ begin
extended_o => sync_led);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_tmp_ext: gc_extend_pulse
generic map
(g_width => 10000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => macrocyc_cnt_twentyfive_p,
extended_o => macrocyc_cnt_twentyfive);
macrocyc_cnt_twentyfive_p <= '1' when macrocyc_cnt = "0000000000000000000000000011001" else '0';
aux_o(7) <= out_of_sync_led;
aux_o(6) <= mf_dbg_p_ext;
aux_o(5) <= reg_from_mt.dbg_o(5);
aux_o(4) <= reg_from_mt.dbg_o(4); --rx_byte_ready_p;
aux_o(3) <= rx_fss_received_p;--mf_dbg(3); --macrocyc_cnt_zero_p;
aux_o(2) <= rx_frame_ok_p;--(2); --tx_completed;
aux_o(1) <= tx_completed_p;--mf_dbg(1);
aux_o(0) <= silen_load_p;--mf_dbg(0); --sync_led;
ext_sync_oe_o <= ext_sync_oe;
aux_o(3) <= ext_sync_p_cnt_rst;--mf_dbg(3); --macrocyc_cnt_zero_p;
aux_o(2) <= reg_from_mt.macrocyc_start_o;--(2); --tx_completed;
aux_o(1) <= macrocyc_cnt_twentyfive;--mf_dbg(1);
aux_o(0) <= sync_led;--mf_dbg(0); --sync_led;
---------------------------------------------------------------------------------------------------
......
rtl/fmc_masterfip_csr.vhd
View file @ 3de128f4
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 10/07/16 17:41:49
-- Created : 10/17/16 12:35:48
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -52,7 +52,7 @@ signal mrfip_dac_config_load_dly0 : std_logic ;
signal mrfip_dac_config_load_int : std_logic ;
signal mrfip_ext_sync_term_en_int : std_logic ;
signal mrfip_ext_sync_dir_int : std_logic ;
signal mrfip_ext_sync_oe_int : std_logic ;
signal mrfip_ext_sync_oe_n_int : std_logic ;
signal mrfip_ext_sync_tst_n_int : std_logic ;
signal mrfip_ext_sync_p_cnt_rst_int : std_logic ;
signal mrfip_macrocyc_lgth_int : std_logic_vector(30 downto 0);
......@@ -178,7 +178,7 @@ begin
mrfip_dac_config_load_int <= '0';
mrfip_ext_sync_term_en_int <= '0';
mrfip_ext_sync_dir_int <= '0';
mrfip_ext_sync_oe_int <= '0';
mrfip_ext_sync_oe_n_int <= '0';
mrfip_ext_sync_tst_n_int <= '0';
mrfip_ext_sync_p_cnt_rst_int <= '0';
mrfip_macrocyc_lgth_int <= "0000000000000000000000000000000";
......@@ -438,13 +438,13 @@ begin
if (wb_we_i = '1') then
mrfip_ext_sync_term_en_int <= wrdata_reg(0);
mrfip_ext_sync_dir_int <= wrdata_reg(1);
mrfip_ext_sync_oe_int <= wrdata_reg(2);
mrfip_ext_sync_oe_n_int <= wrdata_reg(2);
mrfip_ext_sync_tst_n_int <= wrdata_reg(3);
mrfip_ext_sync_p_cnt_rst_int <= wrdata_reg(8);
end if;
rddata_reg(0) <= mrfip_ext_sync_term_en_int;
rddata_reg(1) <= mrfip_ext_sync_dir_int;
rddata_reg(2) <= mrfip_ext_sync_oe_int;
rddata_reg(2) <= mrfip_ext_sync_oe_n_int;
rddata_reg(3) <= mrfip_ext_sync_tst_n_int;
rddata_reg(8) <= mrfip_ext_sync_p_cnt_rst_int;
rddata_reg(4) <= 'X';
......@@ -1776,8 +1776,8 @@ begin
regs_o.ext_sync_term_en_o <= mrfip_ext_sync_term_en_int;
-- transceiver direction
regs_o.ext_sync_dir_o <= mrfip_ext_sync_dir_int;
-- transceiver output enable
regs_o.ext_sync_oe_o <= mrfip_ext_sync_oe_int;
-- transceiver output enable negative logic
regs_o.ext_sync_oe_n_o <= mrfip_ext_sync_oe_n_int;
-- test pulse
regs_o.ext_sync_tst_n_o <= mrfip_ext_sync_tst_n_int;
-- pulses counter reset
......
rtl/masterFIP_pkg.vhd
View file @ 3de128f4
......@@ -201,7 +201,7 @@ package masterFIP_pkg is
fd_txena_o : out std_logic;
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_o : out std_logic;
ext_sync_oe_n_o : out std_logic;
ext_sync_tst_n_o : out std_logic;
ext_sync_i : in std_logic;
adc_1v8_shdn_n_o : out std_logic;
......
rtl/mf_wbgen2_pkg.vhd
View file @ 3de128f4
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC masterFIP core registers
---------------------------------------------------------------------------------------
-- File : mf_wbgen2_pkg.vhd
-- File : fmc_masterfip_csr_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 10/07/16 17:41:49
-- Created : 10/17/16 12:35:48
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -222,7 +222,7 @@ package mrfip_wbgen2_pkg is
dac_config_load_o : std_logic;
ext_sync_term_en_o : std_logic;
ext_sync_dir_o : std_logic;
ext_sync_oe_o : std_logic;
ext_sync_oe_n_o : std_logic;
ext_sync_tst_n_o : std_logic;
ext_sync_p_cnt_rst_o : std_logic;
macrocyc_lgth_o : std_logic_vector(30 downto 0);
......@@ -318,7 +318,7 @@ package mrfip_wbgen2_pkg is
dac_config_load_o => '0',
ext_sync_term_en_o => '0',
ext_sync_dir_o => '0',
ext_sync_oe_o => '0',
ext_sync_oe_n_o => '0',
ext_sync_tst_n_o => '0',
ext_sync_p_cnt_rst_o => '0',
macrocyc_lgth_o => (others => '0'),
......
rtl/wbgen/fmc_masterfip_csr.h
View file @ 3de128f4
......@@ -3,7 +3,7 @@
* File : fmc_masterfip_csr.h
* Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
* Created : 10/07/16 17:06:15
* Created : 10/17/16 12:35:48
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -34,10 +34,10 @@
/* definitions for register: rst */
/* definitions for field: reset of the masterFIP core in reg: rst */
#define MF_RST_CORE WBGEN2_GEN_MASK(0, 1)
#define MRFIP_RST_CORE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: reset of the fieldrive chip in reg: rst */
#define MF_RST_FD WBGEN2_GEN_MASK(1, 1)
#define MRFIP_RST_FD WBGEN2_GEN_MASK(1, 1)
/* definitions for register: id */
......@@ -52,47 +52,47 @@
/* definitions for register: adc */
/* definitions for field: 1v8_shdn_n in reg: adc */
#define MF_ADC_1V8_SHDN_N WBGEN2_GEN_MASK(0, 1)
#define MRFIP_ADC_1V8_SHDN_N WBGEN2_GEN_MASK(0, 1)
/* definitions for field: m5v_shdn_n in reg: adc */
#define MF_ADC_M5V_SHDN_N WBGEN2_GEN_MASK(1, 1)
#define MRFIP_ADC_M5V_SHDN_N WBGEN2_GEN_MASK(1, 1)
/* definitions for field: 5v_en_n in reg: adc */
#define MF_ADC_5V_EN_N WBGEN2_GEN_MASK(2, 1)
#define MRFIP_ADC_5V_EN_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: prim_conn_n in reg: adc */
#define MF_ADC_PRIM_CONN_N WBGEN2_GEN_MASK(8, 1)
#define MRFIP_ADC_PRIM_CONN_N WBGEN2_GEN_MASK(8, 1)
/* definitions for field: sec_conn_n in reg: adc */
#define MF_ADC_SEC_CONN_N WBGEN2_GEN_MASK(9, 1)
#define MRFIP_ADC_SEC_CONN_N WBGEN2_GEN_MASK(9, 1)
/* definitions for register: dac */
/* definitions for field: value in reg: dac */
#define MF_DAC_CONFIG_VALUE_MASK WBGEN2_GEN_MASK(0, 16)
#define MF_DAC_CONFIG_VALUE_SHIFT 0
#define MF_DAC_CONFIG_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define MF_DAC_CONFIG_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
#define MRFIP_DAC_CONFIG_VALUE_MASK WBGEN2_GEN_MASK(0, 16)
#define MRFIP_DAC_CONFIG_VALUE_SHIFT 0
#define MRFIP_DAC_CONFIG_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define MRFIP_DAC_CONFIG_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: load in reg: dac */
#define MF_DAC_CONFIG_LOAD WBGEN2_GEN_MASK(16, 1)
#define MRFIP_DAC_CONFIG_LOAD WBGEN2_GEN_MASK(16, 1)
/* definitions for register: ext sync */
/* definitions for field: termination enable in reg: ext sync */
#define MF_EXT_SYNC_TERM_EN WBGEN2_GEN_MASK(0, 1)
#define MRFIP_EXT_SYNC_TERM_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: transceiver direction in reg: ext sync */
#define MF_EXT_SYNC_DIR WBGEN2_GEN_MASK(1, 1)
#define MRFIP_EXT_SYNC_DIR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: transceiver output enable in reg: ext sync */
#define MF_EXT_SYNC_OE WBGEN2_GEN_MASK(2, 1)
/* definitions for field: transceiver output enable negative logic in reg: ext sync */
#define MRFIP_EXT_SYNC_OE_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: test pulse in reg: ext sync */
#define MF_EXT_SYNC_TST_N WBGEN2_GEN_MASK(3, 1)
#define MRFIP_EXT_SYNC_TST_N WBGEN2_GEN_MASK(3, 1)
/* definitions for field: pulses counter reset in reg: ext sync */
#define MF_EXT_SYNC_P_CNT_RST WBGEN2_GEN_MASK(8, 1)
#define MRFIP_EXT_SYNC_P_CNT_RST WBGEN2_GEN_MASK(8, 1)
/* definitions for register: ext sync pulses cnt */
......@@ -101,35 +101,35 @@
/* definitions for register: macrocycle lgth */
/* definitions for field: macrocycle lgth in reg: macrocycle lgth */
#define MF_MACROCYC_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MF_MACROCYC_LGTH_SHIFT 0
#define MF_MACROCYC_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MF_MACROCYC_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
#define MRFIP_MACROCYC_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MRFIP_MACROCYC_LGTH_SHIFT 0
#define MRFIP_MACROCYC_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MRFIP_MACROCYC_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: macrocycle cnt start in reg: macrocycle lgth */
#define MF_MACROCYC_START WBGEN2_GEN_MASK(31, 1)
#define MRFIP_MACROCYC_START WBGEN2_GEN_MASK(31, 1)
/* definitions for register: turnaround lgth */
/* definitions for field: turnaround time in reg: turnaround lgth */
#define MF_TURNAR_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MF_TURNAR_LGTH_SHIFT 0
#define MF_TURNAR_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MF_TURNAR_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
#define MRFIP_TURNAR_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MRFIP_TURNAR_LGTH_SHIFT 0
#define MRFIP_TURNAR_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MRFIP_TURNAR_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: turnaround cnt start in reg: turnaround lgth */
#define MF_TURNAR_START WBGEN2_GEN_MASK(31, 1)
#define MRFIP_TURNAR_START WBGEN2_GEN_MASK(31, 1)
/* definitions for register: silence lgth */
/* definitions for field: silence time in reg: silence lgth */
#define MF_SILEN_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MF_SILEN_LGTH_SHIFT 0
#define MF_SILEN_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MF_SILEN_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
#define MRFIP_SILEN_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MRFIP_SILEN_LGTH_SHIFT 0
#define MRFIP_SILEN_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MRFIP_SILEN_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: silence cnt start in reg: silence lgth */
#define MF_SILEN_START WBGEN2_GEN_MASK(31, 1)
#define MRFIP_SILEN_START WBGEN2_GEN_MASK(31, 1)
/* definitions for register: macrocycle time cnt */
......@@ -142,38 +142,38 @@
/* definitions for register: tx ctrl */
/* definitions for field: tx rst in reg: tx ctrl */
#define MF_TX_CTRL_RST WBGEN2_GEN_MASK(0, 1)
#define MRFIP_TX_CTRL_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for field: tx strt in reg: tx ctrl */
#define MF_TX_CTRL_START WBGEN2_GEN_MASK(1, 1)
#define MRFIP_TX_CTRL_START WBGEN2_GEN_MASK(1, 1)
/* definitions for field: tx number of bytes in reg: tx ctrl */
#define MF_TX_CTRL_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MF_TX_CTRL_BYTES_NUM_SHIFT 8
#define MF_TX_CTRL_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MF_TX_CTRL_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
#define MRFIP_TX_CTRL_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MRFIP_TX_CTRL_BYTES_NUM_SHIFT 8
#define MRFIP_TX_CTRL_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MRFIP_TX_CTRL_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: tx status */
/* definitions for field: tx ended in reg: tx status */
#define MF_TX_STAT_STOP WBGEN2_GEN_MASK(0, 1)
#define MRFIP_TX_STAT_STOP WBGEN2_GEN_MASK(0, 1)
/* definitions for field: tx enable in reg: tx status */
#define MF_TX_STAT_ENA WBGEN2_GEN_MASK(8, 1)
#define MRFIP_TX_STAT_ENA WBGEN2_GEN_MASK(8, 1)
/* definitions for field: tx status current byte index in reg: tx status */
#define MF_TX_STAT_CURR_BYTE_INDX_MASK WBGEN2_GEN_MASK(9, 16)
#define MF_TX_STAT_CURR_BYTE_INDX_SHIFT 9
#define MF_TX_STAT_CURR_BYTE_INDX_W(value) WBGEN2_GEN_WRITE(value, 9, 16)
#define MF_TX_STAT_CURR_BYTE_INDX_R(reg) WBGEN2_GEN_READ(reg, 9, 16)
#define MRFIP_TX_STAT_CURR_BYTE_INDX_MASK WBGEN2_GEN_MASK(9, 16)
#define MRFIP_TX_STAT_CURR_BYTE_INDX_SHIFT 9
#define MRFIP_TX_STAT_CURR_BYTE_INDX_W(value) WBGEN2_GEN_WRITE(value, 9, 16)
#define MRFIP_TX_STAT_CURR_BYTE_INDX_R(reg) WBGEN2_GEN_READ(reg, 9, 16)
/* definitions for register: fieldrive wdgn, cdn */
/* definitions for field: fieldrive watchdog in reg: fieldrive wdgn, cdn */
#define MF_FD_WDG WBGEN2_GEN_MASK(0, 1)
#define MRFIP_FD_WDG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: fieldrive carrier detect in reg: fieldrive wdgn, cdn */
#define MF_FD_CD WBGEN2_GEN_MASK(1, 1)
#define MRFIP_FD_CD WBGEN2_GEN_MASK(1, 1)
/* definitions for register: fieldrive wdg timestamp */
......@@ -184,626 +184,626 @@
/* definitions for register: rx ctrl */
/* definitions for field: rx rst in reg: rx ctrl */
#define MF_RX_CTRL_RST WBGEN2_GEN_MASK(0, 1)
#define MRFIP_RX_CTRL_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for register: rx status */
/* definitions for field: rx preamble detected in reg: rx status */
#define MF_RX_STAT_PREAM_OK WBGEN2_GEN_MASK(0, 1)
#define MRFIP_RX_STAT_PREAM_OK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: rx frame ok in reg: rx status */
#define MF_RX_STAT_FRAME_OK WBGEN2_GEN_MASK(1, 1)
#define MRFIP_RX_STAT_FRAME_OK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: rx frame crc error in reg: rx status */
#define MF_RX_STAT_FRAME_CRC_ERR WBGEN2_GEN_MASK(2, 1)
#define MRFIP_RX_STAT_FRAME_CRC_ERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: rx number of payload bytes in reg: rx status */
#define MF_RX_STAT_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MF_RX_STAT_BYTES_NUM_SHIFT 8
#define MF_RX_STAT_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MF_RX_STAT_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
#define MRFIP_RX_STAT_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MRFIP_RX_STAT_BYTES_NUM_SHIFT 8
#define MRFIP_RX_STAT_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MRFIP_RX_STAT_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: rx current word index */
/* definitions for register: rx number of frames with CRC error */
/* definitions for register: rx data ctrl byte */
/* definitions for register: rx payload ctrl byte */
/* definitions for register: rx data reg1 */
/* definitions for register: rx payload reg1 */
/* definitions for register: rx data reg2 */
/* definitions for register: rx payload reg2 */
/* definitions for register: rx data reg3 */
/* definitions for register: rx payload reg3 */
/* definitions for register: rx data reg4 */
/* definitions for register: rx payload reg4 */
/* definitions for register: rx data reg5 */
/* definitions for register: rx payload reg5 */
/* definitions for register: rx data reg6 */
/* definitions for register: rx payload reg6 */
/* definitions for register: rx data reg7 */
/* definitions for register: rx payload reg7 */
/* definitions for register: rx data reg8 */
/* definitions for register: rx payload reg8 */
/* definitions for register: rx data reg9 */
/* definitions for register: rx payload reg9 */
/* definitions for register: rx data reg10 */
/* definitions for register: rx payload reg10 */
/* definitions for register: rx data reg11 */
/* definitions for register: rx payload reg11 */
/* definitions for register: rx data reg12 */
/* definitions for register: rx payload reg12 */
/* definitions for register: rx data reg13 */
/* definitions for register: rx payload reg13 */
/* definitions for register: rx data reg14 */
/* definitions for register: rx payload reg14 */
/* definitions for register: rx data reg15 */
/* definitions for register: rx payload reg15 */
/* definitions for register: rx data reg16 */
/* definitions for register: rx payload reg16 */
/* definitions for register: rx data reg17 */
/* definitions for register: rx payload reg17 */
/* definitions for register: rx data reg18 */
/* definitions for register: rx payload reg18 */
/* definitions for register: rx data reg19 */
/* definitions for register: rx payload reg19 */
/* definitions for register: rx data reg20 */
/* definitions for register: rx payload reg20 */
/* definitions for register: rx data reg21 */
/* definitions for register: rx payload reg21 */
/* definitions for register: rx data reg22 */
/* definitions for register: rx payload reg22 */
/* definitions for register: rx data reg23 */
/* definitions for register: rx payload reg23 */
/* definitions for register: rx data reg24 */
/* definitions for register: rx payload reg24 */
/* definitions for register: rx data reg25 */
/* definitions for register: rx payload reg25 */
/* definitions for register: rx data reg26 */
/* definitions for register: rx payload reg26 */
/* definitions for register: rx data reg27 */
/* definitions for register: rx payload reg27 */
/* definitions for register: rx data reg28 */
/* definitions for register: rx payload reg28 */
/* definitions for register: rx data reg29 */
/* definitions for register: rx payload reg29 */
/* definitions for register: rx data reg30 */
/* definitions for register: rx payload reg30 */
/* definitions for register: rx data reg31 */
/* definitions for register: rx payload reg31 */
/* definitions for register: rx data reg32 */
/* definitions for register: rx payload reg32 */
/* definitions for register: rx data reg33 */
/* definitions for register: rx payload reg33 */
/* definitions for register: rx data reg34 */
/* definitions for register: rx payload reg34 */
/* definitions for register: rx data reg35 */
/* definitions for register: rx payload reg35 */
/* definitions for register: rx data reg36 */
/* definitions for register: rx payload reg36 */
/* definitions for register: rx data reg37 */
/* definitions for register: rx payload reg37 */
/* definitions for register: rx data reg38 */
/* definitions for register: rx payload reg38 */
/* definitions for register: rx data reg39 */
/* definitions for register: rx payload reg39 */
/* definitions for register: rx data reg40 */
/* definitions for register: rx payload reg40 */
/* definitions for register: rx data reg41 */
/* definitions for register: rx payload reg41 */
/* definitions for register: rx data reg42 */
/* definitions for register: rx payload reg42 */
/* definitions for register: rx data reg43 */
/* definitions for register: rx payload reg43 */
/* definitions for register: rx data reg44 */
/* definitions for register: rx payload reg44 */
/* definitions for register: rx data reg45 */
/* definitions for register: rx payload reg45 */
/* definitions for register: rx data reg46 */
/* definitions for register: rx payload reg46 */
/* definitions for register: rx data reg47 */
/* definitions for register: rx payload reg47 */
/* definitions for register: rx data reg48 */
/* definitions for register: rx payload reg48 */
/* definitions for register: rx data reg49 */
/* definitions for register: rx payload reg49 */
/* definitions for register: rx data reg50 */
/* definitions for register: rx payload reg50 */
/* definitions for register: rx data reg51 */
/* definitions for register: rx payload reg51 */
/* definitions for register: rx data reg52 */
/* definitions for register: rx payload reg52 */
/* definitions for register: rx data reg53 */
/* definitions for register: rx payload reg53 */
/* definitions for register: rx data reg54 */
/* definitions for register: rx payload reg54 */
/* definitions for register: rx data reg55 */
/* definitions for register: rx payload reg55 */
/* definitions for register: rx data reg56 */
/* definitions for register: rx payload reg56 */
/* definitions for register: rx data reg57 */
/* definitions for register: rx payload reg57 */
/* definitions for register: rx data reg58 */
/* definitions for register: rx payload reg58 */
/* definitions for register: rx data reg59 */
/* definitions for register: rx payload reg59 */
/* definitions for register: rx data reg60 */
/* definitions for register: rx payload reg60 */
/* definitions for register: rx data reg61 */
/* definitions for register: rx payload reg61 */
/* definitions for register: rx data reg62 */
/* definitions for register: rx payload reg62 */
/* definitions for register: rx data reg63 */
/* definitions for register: rx payload reg63 */
/* definitions for register: rx data reg64 */
/* definitions for register: rx payload reg64 */
/* definitions for register: rx data reg65 */
/* definitions for register: rx payload reg65 */
/* definitions for register: rx data reg66 */
/* definitions for register: rx payload reg66 */
/* definitions for register: rx data reg67 */
/* definitions for register: rx payload reg67 */
/* definitions for register: tx ctrl byte */
/* definitions for register: tx data reg1 */
/* definitions for register: tx payload reg1 */
/* definitions for register: tx data reg2 */
/* definitions for register: tx payload reg2 */
/* definitions for register: tx data reg3 */
/* definitions for register: tx payload reg3 */
/* definitions for register: tx data reg4 */
/* definitions for register: tx payload reg4 */
/* definitions for register: tx data reg5 */
/* definitions for register: tx payload reg5 */
/* definitions for register: tx data reg6 */
/* definitions for register: tx payload reg6 */
/* definitions for register: tx data reg7 */
/* definitions for register: tx payload reg7 */
/* definitions for register: tx data reg8 */
/* definitions for register: tx payload reg8 */
/* definitions for register: tx data reg9 */
/* definitions for register: tx payload reg9 */
/* definitions for register: tx data reg10 */
/* definitions for register: tx payload reg10 */
/* definitions for register: tx data reg11 */
/* definitions for register: tx payload reg11 */
/* definitions for register: tx data reg12 */
/* definitions for register: tx payload reg12 */
/* definitions for register: tx data reg13 */
/* definitions for register: tx payload reg13 */
/* definitions for register: tx data reg14 */
/* definitions for register: tx payload reg14 */
/* definitions for register: tx data reg15 */
/* definitions for register: tx payload reg15 */
/* definitions for register: tx data reg16 */
/* definitions for register: tx payload reg16 */
/* definitions for register: tx data reg17 */
/* definitions for register: tx payload reg17 */
/* definitions for register: tx data reg18 */
/* definitions for register: tx payload reg18 */
/* definitions for register: tx data reg19 */
/* definitions for register: tx payload reg19 */
/* definitions for register: tx data reg20 */
/* definitions for register: tx payload reg20 */
/* definitions for register: tx data reg21 */
/* definitions for register: tx payload reg21 */
/* definitions for register: tx data reg22 */
/* definitions for register: tx payload reg22 */
/* definitions for register: tx data reg23 */
/* definitions for register: tx payload reg23 */
/* definitions for register: tx data reg24 */
/* definitions for register: tx payload reg24 */
/* definitions for register: tx data reg25 */
/* definitions for register: tx payload reg25 */
/* definitions for register: tx data reg26 */
/* definitions for register: tx payload reg26 */
/* definitions for register: tx data reg27 */
/* definitions for register: tx payload reg27 */
/* definitions for register: tx data reg28 */
/* definitions for register: tx payload reg28 */
/* definitions for register: tx data reg29 */
/* definitions for register: tx payload reg29 */
/* definitions for register: tx data reg30 */
/* definitions for register: tx payload reg30 */
/* definitions for register: tx data reg31 */
/* definitions for register: tx payload reg31 */
/* definitions for register: tx data reg32 */
/* definitions for register: tx payload reg32 */
/* definitions for register: tx data reg33 */
/* definitions for register: tx payload reg33 */
/* definitions for register: tx data reg34 */
/* definitions for register: tx payload reg34 */
/* definitions for register: tx data reg35 */
/* definitions for register: tx payload reg35 */
/* definitions for register: tx data reg36 */
/* definitions for register: tx payload reg36 */
/* definitions for register: tx data reg37 */
/* definitions for register: tx payload reg37 */
/* definitions for register: tx data reg38 */
/* definitions for register: tx payload reg38 */
/* definitions for register: tx data reg39 */
/* definitions for register: tx payload reg39 */
/* definitions for register: tx data reg40 */
/* definitions for register: tx payload reg40 */
/* definitions for register: tx data reg41 */
/* definitions for register: tx payload reg41 */
/* definitions for register: tx data reg42 */
/* definitions for register: tx payload reg42 */
/* definitions for register: tx data reg43 */
/* definitions for register: tx payload reg43 */
/* definitions for register: tx data reg44 */
/* definitions for register: tx payload reg44 */
/* definitions for register: tx data reg45 */
/* definitions for register: tx payload reg45 */
/* definitions for register: tx data reg46 */
/* definitions for register: tx payload reg46 */
/* definitions for register: tx data reg47 */
/* definitions for register: tx payload reg47 */
/* definitions for register: tx data reg48 */
/* definitions for register: tx payload reg48 */
/* definitions for register: tx data reg49 */
/* definitions for register: tx payload reg49 */
/* definitions for register: tx data reg50 */
/* definitions for register: tx payload reg50 */
/* definitions for register: tx data reg51 */
/* definitions for register: tx payload reg51 */
/* definitions for register: tx data reg52 */
/* definitions for register: tx payload reg52 */
/* definitions for register: tx data reg53 */
/* definitions for register: tx payload reg53 */
/* definitions for register: tx data reg54 */
/* definitions for register: tx payload reg54 */
/* definitions for register: tx data reg55 */
/* definitions for register: tx payload reg55 */
/* definitions for register: tx data reg56 */
/* definitions for register: tx payload reg56 */
/* definitions for register: tx data reg57 */
/* definitions for register: tx payload reg57 */
/* definitions for register: tx data reg58 */
/* definitions for register: tx payload reg58 */
/* definitions for register: tx data reg59 */
/* definitions for register: tx payload reg59 */
/* definitions for register: tx data reg60 */
/* definitions for register: tx payload reg60 */
/* definitions for register: tx data reg61 */
/* definitions for register: tx payload reg61 */
/* definitions for register: tx data reg62 */
/* definitions for register: tx payload reg62 */
/* definitions for register: tx data reg63 */
/* definitions for register: tx payload reg63 */
/* definitions for register: tx data reg64 */
/* definitions for register: tx payload reg64 */
/* definitions for register: tx data reg65 */
/* definitions for register: tx payload reg65 */
/* definitions for register: tx data reg66 */
/* definitions for register: tx payload reg66 */
/* definitions for register: tx data reg67 */
/* definitions for register: tx payload reg67 */
/* [0x0]: REG rst */
#define MF_REG_RST 0x00000000
#define MRFIP_REG_RST 0x00000000
/* [0x4]: REG id */
#define MF_REG_ID 0x00000004
#define MRFIP_REG_ID 0x00000004
/* [0x8]: REG dbg */
#define MF_REG_DBG 0x00000008
#define MRFIP_REG_DBG 0x00000008
/* [0xc]: REG mezzanine temperature */
#define MF_REG_DS1820_TEMPER 0x0000000c
#define MRFIP_REG_DS1820_TEMPER 0x0000000c
/* [0x10]: REG mezzanine unique id lsb */
#define MF_REG_DS1820_ID_LSB 0x00000010
#define MRFIP_REG_DS1820_ID_LSB 0x00000010
/* [0x14]: REG mezzanine unique id msb */
#define MF_REG_DS1820_ID_MSB 0x00000014
#define MRFIP_REG_DS1820_ID_MSB 0x00000014
/* [0x18]: REG adc */
#define MF_REG_ADC 0x00000018
#define MRFIP_REG_ADC 0x00000018
/* [0x1c]: REG dac */
#define MF_REG_DAC_CONFIG 0x0000001c
#define MRFIP_REG_DAC_CONFIG 0x0000001c
/* [0x20]: REG ext sync */
#define MF_REG_EXT_SYNC 0x00000020
#define MRFIP_REG_EXT_SYNC 0x00000020
/* [0x24]: REG ext sync pulses cnt */
#define MF_REG_EXT_SYNC_P_CNT 0x00000024
#define MRFIP_REG_EXT_SYNC_P_CNT 0x00000024
/* [0x28]: REG bus speed */
#define MF_REG_SPEED 0x00000028
#define MRFIP_REG_SPEED 0x00000028
/* [0x2c]: REG macrocycle lgth */
#define MF_REG_MACROCYC 0x0000002c
#define MRFIP_REG_MACROCYC 0x0000002c
/* [0x30]: REG turnaround lgth */
#define MF_REG_TURNAR 0x00000030
#define MRFIP_REG_TURNAR 0x00000030
/* [0x34]: REG silence lgth */
#define MF_REG_SILEN 0x00000034
#define MRFIP_REG_SILEN 0x00000034
/* [0x38]: REG macrocycle time cnt */
#define MF_REG_MACROCYC_TIME_CNT 0x00000038
#define MRFIP_REG_MACROCYC_TIME_CNT 0x00000038
/* [0x3c]: REG macrocycles number cnt */
#define MF_REG_MACROCYC_NUM_CNT 0x0000003c
#define MRFIP_REG_MACROCYC_NUM_CNT 0x0000003c
/* [0x40]: REG turnaround time cnt */
#define MF_REG_TURNAR_TIME_CNT 0x00000040
#define MRFIP_REG_TURNAR_TIME_CNT 0x00000040
/* [0x44]: REG silence time cnt */
#define MF_REG_SILEN_TIME_CNT 0x00000044
#define MRFIP_REG_SILEN_TIME_CNT 0x00000044
/* [0x48]: REG tx ctrl */
#define MF_REG_TX_CTRL 0x00000048
#define MRFIP_REG_TX_CTRL 0x00000048
/* [0x4c]: REG tx status */
#define MF_REG_TX_STAT 0x0000004c
#define MRFIP_REG_TX_STAT 0x0000004c
/* [0x50]: REG fieldrive wdgn, cdn */
#define MF_REG_FD 0x00000050
#define MRFIP_REG_FD 0x00000050
/* [0x54]: REG fieldrive wdg timestamp */
#define MF_REG_FD_WDG_TSTAMP 0x00000054
#define MRFIP_REG_FD_WDG_TSTAMP 0x00000054
/* [0x58]: REG fieldrive txer cnt */
#define MF_REG_FD_TXER_CNT 0x00000058
#define MRFIP_REG_FD_TXER_CNT 0x00000058
/* [0x5c]: REG fieldrive txer tstamp */
#define MF_REG_FD_TXER_TSTAMP 0x0000005c
#define MRFIP_REG_FD_TXER_TSTAMP 0x0000005c
/* [0x60]: REG rx ctrl */
#define MF_REG_RX_CTRL 0x00000060
#define MRFIP_REG_RX_CTRL 0x00000060
/* [0x64]: REG rx status */
#define MF_REG_RX_STAT 0x00000064
#define MRFIP_REG_RX_STAT 0x00000064
/* [0x68]: REG rx current word index */
#define MF_REG_RX_STAT_CURR_WORD_INDX 0x00000068
#define MRFIP_REG_RX_STAT_CURR_WORD_INDX 0x00000068
/* [0x6c]: REG rx number of frames with CRC error */
#define MF_REG_RX_STAT_CRC_ERR_CNT 0x0000006c
/* [0x70]: REG rx data ctrl byte */
#define MF_REG_RX_DATA_CTRL 0x00000070
/* [0x74]: REG rx data reg1 */
#define MF_REG_RX_DATA_REG1 0x00000074
/* [0x78]: REG rx data reg2 */
#define MF_REG_RX_DATA_REG2 0x00000078
/* [0x7c]: REG rx data reg3 */
#define MF_REG_RX_DATA_REG3 0x0000007c
/* [0x80]: REG rx data reg4 */
#define MF_REG_RX_DATA_REG4 0x00000080
/* [0x84]: REG rx data reg5 */
#define MF_REG_RX_DATA_REG5 0x00000084
/* [0x88]: REG rx data reg6 */
#define MF_REG_RX_DATA_REG6 0x00000088
/* [0x8c]: REG rx data reg7 */
#define MF_REG_RX_DATA_REG7 0x0000008c
/* [0x90]: REG rx data reg8 */
#define MF_REG_RX_DATA_REG8 0x00000090
/* [0x94]: REG rx data reg9 */
#define MF_REG_RX_DATA_REG9 0x00000094
/* [0x98]: REG rx data reg10 */
#define MF_REG_RX_DATA_REG10 0x00000098
/* [0x9c]: REG rx data reg11 */
#define MF_REG_RX_DATA_REG11 0x0000009c
/* [0xa0]: REG rx data reg12 */
#define MF_REG_RX_DATA_REG12 0x000000a0
/* [0xa4]: REG rx data reg13 */
#define MF_REG_RX_DATA_REG13 0x000000a4
/* [0xa8]: REG rx data reg14 */
#define MF_REG_RX_DATA_REG14 0x000000a8
/* [0xac]: REG rx data reg15 */
#define MF_REG_RX_DATA_REG15 0x000000ac
/* [0xb0]: REG rx data reg16 */
#define MF_REG_RX_DATA_REG16 0x000000b0
/* [0xb4]: REG rx data reg17 */
#define MF_REG_RX_DATA_REG17 0x000000b4
/* [0xb8]: REG rx data reg18 */
#define MF_REG_RX_DATA_REG18 0x000000b8
/* [0xbc]: REG rx data reg19 */
#define MF_REG_RX_DATA_REG19 0x000000bc
/* [0xc0]: REG rx data reg20 */
#define MF_REG_RX_DATA_REG20 0x000000c0
/* [0xc4]: REG rx data reg21 */
#define MF_REG_RX_DATA_REG21 0x000000c4
/* [0xc8]: REG rx data reg22 */
#define MF_REG_RX_DATA_REG22 0x000000c8
/* [0xcc]: REG rx data reg23 */
#define MF_REG_RX_DATA_REG23 0x000000cc
/* [0xd0]: REG rx data reg24 */
#define MF_REG_RX_DATA_REG24 0x000000d0
/* [0xd4]: REG rx data reg25 */
#define MF_REG_RX_DATA_REG25 0x000000d4
/* [0xd8]: REG rx data reg26 */
#define MF_REG_RX_DATA_REG26 0x000000d8
/* [0xdc]: REG rx data reg27 */
#define MF_REG_RX_DATA_REG27 0x000000dc
/* [0xe0]: REG rx data reg28 */
#define MF_REG_RX_DATA_REG28 0x000000e0
/* [0xe4]: REG rx data reg29 */
#define MF_REG_RX_DATA_REG29 0x000000e4
/* [0xe8]: REG rx data reg30 */
#define MF_REG_RX_DATA_REG30 0x000000e8
/* [0xec]: REG rx data reg31 */
#define MF_REG_RX_DATA_REG31 0x000000ec
/* [0xf0]: REG rx data reg32 */
#define MF_REG_RX_DATA_REG32 0x000000f0
/* [0xf4]: REG rx data reg33 */
#define MF_REG_RX_DATA_REG33 0x000000f4
/* [0xf8]: REG rx data reg34 */
#define MF_REG_RX_DATA_REG34 0x000000f8
/* [0xfc]: REG rx data reg35 */
#define MF_REG_RX_DATA_REG35 0x000000fc
/* [0x100]: REG rx data reg36 */
#define MF_REG_RX_DATA_REG36 0x00000100
/* [0x104]: REG rx data reg37 */
#define MF_REG_RX_DATA_REG37 0x00000104
/* [0x108]: REG rx data reg38 */
#define MF_REG_RX_DATA_REG38 0x00000108
/* [0x10c]: REG rx data reg39 */
#define MF_REG_RX_DATA_REG39 0x0000010c
/* [0x110]: REG rx data reg40 */
#define MF_REG_RX_DATA_REG40 0x00000110
/* [0x114]: REG rx data reg41 */
#define MF_REG_RX_DATA_REG41 0x00000114
/* [0x118]: REG rx data reg42 */
#define MF_REG_RX_DATA_REG42 0x00000118
/* [0x11c]: REG rx data reg43 */
#define MF_REG_RX_DATA_REG43 0x0000011c
/* [0x120]: REG rx data reg44 */
#define MF_REG_RX_DATA_REG44 0x00000120
/* [0x124]: REG rx data reg45 */
#define MF_REG_RX_DATA_REG45 0x00000124
/* [0x128]: REG rx data reg46 */
#define MF_REG_RX_DATA_REG46 0x00000128
/* [0x12c]: REG rx data reg47 */
#define MF_REG_RX_DATA_REG47 0x0000012c
/* [0x130]: REG rx data reg48 */
#define MF_REG_RX_DATA_REG48 0x00000130
/* [0x134]: REG rx data reg49 */
#define MF_REG_RX_DATA_REG49 0x00000134
/* [0x138]: REG rx data reg50 */
#define MF_REG_RX_DATA_REG50 0x00000138
/* [0x13c]: REG rx data reg51 */
#define MF_REG_RX_DATA_REG51 0x0000013c
/* [0x140]: REG rx data reg52 */
#define MF_REG_RX_DATA_REG52 0x00000140
/* [0x144]: REG rx data reg53 */
#define MF_REG_RX_DATA_REG53 0x00000144
/* [0x148]: REG rx data reg54 */
#define MF_REG_RX_DATA_REG54 0x00000148
/* [0x14c]: REG rx data reg55 */
#define MF_REG_RX_DATA_REG55 0x0000014c
/* [0x150]: REG rx data reg56 */
#define MF_REG_RX_DATA_REG56 0x00000150
/* [0x154]: REG rx data reg57 */
#define MF_REG_RX_DATA_REG57 0x00000154
/* [0x158]: REG rx data reg58 */
#define MF_REG_RX_DATA_REG58 0x00000158
/* [0x15c]: REG rx data reg59 */
#define MF_REG_RX_DATA_REG59 0x0000015c
/* [0x160]: REG rx data reg60 */
#define MF_REG_RX_DATA_REG60 0x00000160
/* [0x164]: REG rx data reg61 */
#define MF_REG_RX_DATA_REG61 0x00000164
/* [0x168]: REG rx data reg62 */
#define MF_REG_RX_DATA_REG62 0x00000168
/* [0x16c]: REG rx data reg63 */
#define MF_REG_RX_DATA_REG63 0x0000016c
/* [0x170]: REG rx data reg64 */
#define MF_REG_RX_DATA_REG64 0x00000170
/* [0x174]: REG rx data reg65 */
#define MF_REG_RX_DATA_REG65 0x00000174
/* [0x178]: REG rx data reg66 */
#define MF_REG_RX_DATA_REG66 0x00000178
/* [0x17c]: REG rx data reg67 */
#define MF_REG_RX_DATA_REG67 0x0000017c
#define MRFIP_REG_RX_STAT_CRC_ERR_CNT 0x0000006c
/* [0x70]: REG rx payload ctrl byte */
#define MRFIP_REG_RX_PAYLD_CTRL 0x00000070
/* [0x74]: REG rx payload reg1 */
#define MRFIP_REG_RX_PAYLD_REG1 0x00000074
/* [0x78]: REG rx payload reg2 */
#define MRFIP_REG_RX_PAYLD_REG2 0x00000078
/* [0x7c]: REG rx payload reg3 */
#define MRFIP_REG_RX_PAYLD_REG3 0x0000007c
/* [0x80]: REG rx payload reg4 */
#define MRFIP_REG_RX_PAYLD_REG4 0x00000080
/* [0x84]: REG rx payload reg5 */
#define MRFIP_REG_RX_PAYLD_REG5 0x00000084
/* [0x88]: REG rx payload reg6 */
#define MRFIP_REG_RX_PAYLD_REG6 0x00000088
/* [0x8c]: REG rx payload reg7 */
#define MRFIP_REG_RX_PAYLD_REG7 0x0000008c
/* [0x90]: REG rx payload reg8 */
#define MRFIP_REG_RX_PAYLD_REG8 0x00000090
/* [0x94]: REG rx payload reg9 */
#define MRFIP_REG_RX_PAYLD_REG9 0x00000094
/* [0x98]: REG rx payload reg10 */
#define MRFIP_REG_RX_PAYLD_REG10 0x00000098
/* [0x9c]: REG rx payload reg11 */
#define MRFIP_REG_RX_PAYLD_REG11 0x0000009c
/* [0xa0]: REG rx payload reg12 */
#define MRFIP_REG_RX_PAYLD_REG12 0x000000a0
/* [0xa4]: REG rx payload reg13 */
#define MRFIP_REG_RX_PAYLD_REG13 0x000000a4
/* [0xa8]: REG rx payload reg14 */
#define MRFIP_REG_RX_PAYLD_REG14 0x000000a8
/* [0xac]: REG rx payload reg15 */
#define MRFIP_REG_RX_PAYLD_REG15 0x000000ac
/* [0xb0]: REG rx payload reg16 */
#define MRFIP_REG_RX_PAYLD_REG16 0x000000b0
/* [0xb4]: REG rx payload reg17 */
#define MRFIP_REG_RX_PAYLD_REG17 0x000000b4
/* [0xb8]: REG rx payload reg18 */
#define MRFIP_REG_RX_PAYLD_REG18 0x000000b8
/* [0xbc]: REG rx payload reg19 */
#define MRFIP_REG_RX_PAYLD_REG19 0x000000bc
/* [0xc0]: REG rx payload reg20 */
#define MRFIP_REG_RX_PAYLD_REG20 0x000000c0
/* [0xc4]: REG rx payload reg21 */
#define MRFIP_REG_RX_PAYLD_REG21 0x000000c4
/* [0xc8]: REG rx payload reg22 */
#define MRFIP_REG_RX_PAYLD_REG22 0x000000c8
/* [0xcc]: REG rx payload reg23 */
#define MRFIP_REG_RX_PAYLD_REG23 0x000000cc
/* [0xd0]: REG rx payload reg24 */
#define MRFIP_REG_RX_PAYLD_REG24 0x000000d0
/* [0xd4]: REG rx payload reg25 */
#define MRFIP_REG_RX_PAYLD_REG25 0x000000d4
/* [0xd8]: REG rx payload reg26 */
#define MRFIP_REG_RX_PAYLD_REG26 0x000000d8
/* [0xdc]: REG rx payload reg27 */
#define MRFIP_REG_RX_PAYLD_REG27 0x000000dc
/* [0xe0]: REG rx payload reg28 */
#define MRFIP_REG_RX_PAYLD_REG28 0x000000e0
/* [0xe4]: REG rx payload reg29 */
#define MRFIP_REG_RX_PAYLD_REG29 0x000000e4
/* [0xe8]: REG rx payload reg30 */
#define MRFIP_REG_RX_PAYLD_REG30 0x000000e8
/* [0xec]: REG rx payload reg31 */
#define MRFIP_REG_RX_PAYLD_REG31 0x000000ec
/* [0xf0]: REG rx payload reg32 */
#define MRFIP_REG_RX_PAYLD_REG32 0x000000f0
/* [0xf4]: REG rx payload reg33 */
#define MRFIP_REG_RX_PAYLD_REG33 0x000000f4
/* [0xf8]: REG rx payload reg34 */
#define MRFIP_REG_RX_PAYLD_REG34 0x000000f8
/* [0xfc]: REG rx payload reg35 */
#define MRFIP_REG_RX_PAYLD_REG35 0x000000fc
/* [0x100]: REG rx payload reg36 */
#define MRFIP_REG_RX_PAYLD_REG36 0x00000100
/* [0x104]: REG rx payload reg37 */
#define MRFIP_REG_RX_PAYLD_REG37 0x00000104
/* [0x108]: REG rx payload reg38 */
#define MRFIP_REG_RX_PAYLD_REG38 0x00000108
/* [0x10c]: REG rx payload reg39 */
#define MRFIP_REG_RX_PAYLD_REG39 0x0000010c
/* [0x110]: REG rx payload reg40 */
#define MRFIP_REG_RX_PAYLD_REG40 0x00000110
/* [0x114]: REG rx payload reg41 */
#define MRFIP_REG_RX_PAYLD_REG41 0x00000114
/* [0x118]: REG rx payload reg42 */
#define MRFIP_REG_RX_PAYLD_REG42 0x00000118
/* [0x11c]: REG rx payload reg43 */
#define MRFIP_REG_RX_PAYLD_REG43 0x0000011c
/* [0x120]: REG rx payload reg44 */
#define MRFIP_REG_RX_PAYLD_REG44 0x00000120
/* [0x124]: REG rx payload reg45 */
#define MRFIP_REG_RX_PAYLD_REG45 0x00000124
/* [0x128]: REG rx payload reg46 */
#define MRFIP_REG_RX_PAYLD_REG46 0x00000128
/* [0x12c]: REG rx payload reg47 */
#define MRFIP_REG_RX_PAYLD_REG47 0x0000012c
/* [0x130]: REG rx payload reg48 */
#define MRFIP_REG_RX_PAYLD_REG48 0x00000130
/* [0x134]: REG rx payload reg49 */
#define MRFIP_REG_RX_PAYLD_REG49 0x00000134
/* [0x138]: REG rx payload reg50 */
#define MRFIP_REG_RX_PAYLD_REG50 0x00000138
/* [0x13c]: REG rx payload reg51 */
#define MRFIP_REG_RX_PAYLD_REG51 0x0000013c
/* [0x140]: REG rx payload reg52 */
#define MRFIP_REG_RX_PAYLD_REG52 0x00000140
/* [0x144]: REG rx payload reg53 */
#define MRFIP_REG_RX_PAYLD_REG53 0x00000144
/* [0x148]: REG rx payload reg54 */
#define MRFIP_REG_RX_PAYLD_REG54 0x00000148
/* [0x14c]: REG rx payload reg55 */
#define MRFIP_REG_RX_PAYLD_REG55 0x0000014c
/* [0x150]: REG rx payload reg56 */
#define MRFIP_REG_RX_PAYLD_REG56 0x00000150
/* [0x154]: REG rx payload reg57 */
#define MRFIP_REG_RX_PAYLD_REG57 0x00000154
/* [0x158]: REG rx payload reg58 */
#define MRFIP_REG_RX_PAYLD_REG58 0x00000158
/* [0x15c]: REG rx payload reg59 */
#define MRFIP_REG_RX_PAYLD_REG59 0x0000015c
/* [0x160]: REG rx payload reg60 */
#define MRFIP_REG_RX_PAYLD_REG60 0x00000160
/* [0x164]: REG rx payload reg61 */
#define MRFIP_REG_RX_PAYLD_REG61 0x00000164
/* [0x168]: REG rx payload reg62 */
#define MRFIP_REG_RX_PAYLD_REG62 0x00000168
/* [0x16c]: REG rx payload reg63 */
#define MRFIP_REG_RX_PAYLD_REG63 0x0000016c
/* [0x170]: REG rx payload reg64 */
#define MRFIP_REG_RX_PAYLD_REG64 0x00000170
/* [0x174]: REG rx payload reg65 */
#define MRFIP_REG_RX_PAYLD_REG65 0x00000174
/* [0x178]: REG rx payload reg66 */
#define MRFIP_REG_RX_PAYLD_REG66 0x00000178
/* [0x17c]: REG rx payload reg67 */
#define MRFIP_REG_RX_PAYLD_REG67 0x0000017c
/* [0x180]: REG tx ctrl byte */
#define MF_REG_TX_DATA_CTRL 0x00000180
/* [0x184]: REG tx data reg1 */
#define MF_REG_TX_DATA_REG1 0x00000184
/* [0x188]: REG tx data reg2 */
#define MF_REG_TX_DATA_REG2 0x00000188
/* [0x18c]: REG tx data reg3 */
#define MF_REG_TX_DATA_REG3 0x0000018c
/* [0x190]: REG tx data reg4 */
#define MF_REG_TX_DATA_REG4 0x00000190
/* [0x194]: REG tx data reg5 */
#define MF_REG_TX_DATA_REG5 0x00000194
/* [0x198]: REG tx data reg6 */
#define MF_REG_TX_DATA_REG6 0x00000198
/* [0x19c]: REG tx data reg7 */
#define MF_REG_TX_DATA_REG7 0x0000019c
/* [0x1a0]: REG tx data reg8 */
#define MF_REG_TX_DATA_REG8 0x000001a0
/* [0x1a4]: REG tx data reg9 */
#define MF_REG_TX_DATA_REG9 0x000001a4
/* [0x1a8]: REG tx data reg10 */
#define MF_REG_TX_DATA_REG10 0x000001a8
/* [0x1ac]: REG tx data reg11 */
#define MF_REG_TX_DATA_REG11 0x000001ac
/* [0x1b0]: REG tx data reg12 */
#define MF_REG_TX_DATA_REG12 0x000001b0
/* [0x1b4]: REG tx data reg13 */
#define MF_REG_TX_DATA_REG13 0x000001b4
/* [0x1b8]: REG tx data reg14 */
#define MF_REG_TX_DATA_REG14 0x000001b8
/* [0x1bc]: REG tx data reg15 */
#define MF_REG_TX_DATA_REG15 0x000001bc
/* [0x1c0]: REG tx data reg16 */
#define MF_REG_TX_DATA_REG16 0x000001c0
/* [0x1c4]: REG tx data reg17 */
#define MF_REG_TX_DATA_REG17 0x000001c4
/* [0x1c8]: REG tx data reg18 */
#define MF_REG_TX_DATA_REG18 0x000001c8
/* [0x1cc]: REG tx data reg19 */
#define MF_REG_TX_DATA_REG19 0x000001cc
/* [0x1d0]: REG tx data reg20 */
#define MF_REG_TX_DATA_REG20 0x000001d0
/* [0x1d4]: REG tx data reg21 */
#define MF_REG_TX_DATA_REG21 0x000001d4
/* [0x1d8]: REG tx data reg22 */
#define MF_REG_TX_DATA_REG22 0x000001d8
/* [0x1dc]: REG tx data reg23 */
#define MF_REG_TX_DATA_REG23 0x000001dc
/* [0x1e0]: REG tx data reg24 */
#define MF_REG_TX_DATA_REG24 0x000001e0
/* [0x1e4]: REG tx data reg25 */
#define MF_REG_TX_DATA_REG25 0x000001e4
/* [0x1e8]: REG tx data reg26 */
#define MF_REG_TX_DATA_REG26 0x000001e8
/* [0x1ec]: REG tx data reg27 */
#define MF_REG_TX_DATA_REG27 0x000001ec
/* [0x1f0]: REG tx data reg28 */
#define MF_REG_TX_DATA_REG28 0x000001f0
/* [0x1f4]: REG tx data reg29 */
#define MF_REG_TX_DATA_REG29 0x000001f4
/* [0x1f8]: REG tx data reg30 */
#define MF_REG_TX_DATA_REG30 0x000001f8
/* [0x1fc]: REG tx data reg31 */
#define MF_REG_TX_DATA_REG31 0x000001fc
/* [0x200]: REG tx data reg32 */
#define MF_REG_TX_DATA_REG32 0x00000200
/* [0x204]: REG tx data reg33 */
#define MF_REG_TX_DATA_REG33 0x00000204
/* [0x208]: REG tx data reg34 */
#define MF_REG_TX_DATA_REG34 0x00000208
/* [0x20c]: REG tx data reg35 */
#define MF_REG_TX_DATA_REG35 0x0000020c
/* [0x210]: REG tx data reg36 */
#define MF_REG_TX_DATA_REG36 0x00000210
/* [0x214]: REG tx data reg37 */
#define MF_REG_TX_DATA_REG37 0x00000214
/* [0x218]: REG tx data reg38 */
#define MF_REG_TX_DATA_REG38 0x00000218
/* [0x21c]: REG tx data reg39 */
#define MF_REG_TX_DATA_REG39 0x0000021c
/* [0x220]: REG tx data reg40 */
#define MF_REG_TX_DATA_REG40 0x00000220
/* [0x224]: REG tx data reg41 */
#define MF_REG_TX_DATA_REG41 0x00000224
/* [0x228]: REG tx data reg42 */
#define MF_REG_TX_DATA_REG42 0x00000228
/* [0x22c]: REG tx data reg43 */
#define MF_REG_TX_DATA_REG43 0x0000022c
/* [0x230]: REG tx data reg44 */
#define MF_REG_TX_DATA_REG44 0x00000230
/* [0x234]: REG tx data reg45 */
#define MF_REG_TX_DATA_REG45 0x00000234
/* [0x238]: REG tx data reg46 */
#define MF_REG_TX_DATA_REG46 0x00000238
/* [0x23c]: REG tx data reg47 */
#define MF_REG_TX_DATA_REG47 0x0000023c
/* [0x240]: REG tx data reg48 */
#define MF_REG_TX_DATA_REG48 0x00000240
/* [0x244]: REG tx data reg49 */
#define MF_REG_TX_DATA_REG49 0x00000244
/* [0x248]: REG tx data reg50 */
#define MF_REG_TX_DATA_REG50 0x00000248
/* [0x24c]: REG tx data reg51 */
#define MF_REG_TX_DATA_REG51 0x0000024c
/* [0x250]: REG tx data reg52 */
#define MF_REG_TX_DATA_REG52 0x00000250
/* [0x254]: REG tx data reg53 */
#define MF_REG_TX_DATA_REG53 0x00000254
/* [0x258]: REG tx data reg54 */
#define MF_REG_TX_DATA_REG54 0x00000258
/* [0x25c]: REG tx data reg55 */
#define MF_REG_TX_DATA_REG55 0x0000025c
/* [0x260]: REG tx data reg56 */
#define MF_REG_TX_DATA_REG56 0x00000260
/* [0x264]: REG tx data reg57 */
#define MF_REG_TX_DATA_REG57 0x00000264
/* [0x268]: REG tx data reg58 */
#define MF_REG_TX_DATA_REG58 0x00000268
/* [0x26c]: REG tx data reg59 */
#define MF_REG_TX_DATA_REG59 0x0000026c
/* [0x270]: REG tx data reg60 */
#define MF_REG_TX_DATA_REG60 0x00000270
/* [0x274]: REG tx data reg61 */
#define MF_REG_TX_DATA_REG61 0x00000274
/* [0x278]: REG tx data reg62 */
#define MF_REG_TX_DATA_REG62 0x00000278
/* [0x27c]: REG tx data reg63 */
#define MF_REG_TX_DATA_REG63 0x0000027c
/* [0x280]: REG tx data reg64 */
#define MF_REG_TX_DATA_REG64 0x00000280
/* [0x284]: REG tx data reg65 */
#define MF_REG_TX_DATA_REG65 0x00000284
/* [0x288]: REG tx data reg66 */
#define MF_REG_TX_DATA_REG66 0x00000288
/* [0x28c]: REG tx data reg67 */
#define MF_REG_TX_DATA_REG67 0x0000028c
#define MRFIP_REG_TX_PAYLD_CTRL 0x00000180
/* [0x184]: REG tx payload reg1 */
#define MRFIP_REG_TX_PAYLD_REG1 0x00000184
/* [0x188]: REG tx payload reg2 */
#define MRFIP_REG_TX_PAYLD_REG2 0x00000188
/* [0x18c]: REG tx payload reg3 */
#define MRFIP_REG_TX_PAYLD_REG3 0x0000018c
/* [0x190]: REG tx payload reg4 */
#define MRFIP_REG_TX_PAYLD_REG4 0x00000190
/* [0x194]: REG tx payload reg5 */
#define MRFIP_REG_TX_PAYLD_REG5 0x00000194
/* [0x198]: REG tx payload reg6 */
#define MRFIP_REG_TX_PAYLD_REG6 0x00000198
/* [0x19c]: REG tx payload reg7 */
#define MRFIP_REG_TX_PAYLD_REG7 0x0000019c
/* [0x1a0]: REG tx payload reg8 */
#define MRFIP_REG_TX_PAYLD_REG8 0x000001a0
/* [0x1a4]: REG tx payload reg9 */
#define MRFIP_REG_TX_PAYLD_REG9 0x000001a4
/* [0x1a8]: REG tx payload reg10 */
#define MRFIP_REG_TX_PAYLD_REG10 0x000001a8
/* [0x1ac]: REG tx payload reg11 */
#define MRFIP_REG_TX_PAYLD_REG11 0x000001ac
/* [0x1b0]: REG tx payload reg12 */
#define MRFIP_REG_TX_PAYLD_REG12 0x000001b0
/* [0x1b4]: REG tx payload reg13 */
#define MRFIP_REG_TX_PAYLD_REG13 0x000001b4
/* [0x1b8]: REG tx payload reg14 */
#define MRFIP_REG_TX_PAYLD_REG14 0x000001b8
/* [0x1bc]: REG tx payload reg15 */
#define MRFIP_REG_TX_PAYLD_REG15 0x000001bc
/* [0x1c0]: REG tx payload reg16 */
#define MRFIP_REG_TX_PAYLD_REG16 0x000001c0
/* [0x1c4]: REG tx payload reg17 */
#define MRFIP_REG_TX_PAYLD_REG17 0x000001c4
/* [0x1c8]: REG tx payload reg18 */
#define MRFIP_REG_TX_PAYLD_REG18 0x000001c8
/* [0x1cc]: REG tx payload reg19 */
#define MRFIP_REG_TX_PAYLD_REG19 0x000001cc
/* [0x1d0]: REG tx payload reg20 */
#define MRFIP_REG_TX_PAYLD_REG20 0x000001d0
/* [0x1d4]: REG tx payload reg21 */
#define MRFIP_REG_TX_PAYLD_REG21 0x000001d4
/* [0x1d8]: REG tx payload reg22 */
#define MRFIP_REG_TX_PAYLD_REG22 0x000001d8
/* [0x1dc]: REG tx payload reg23 */
#define MRFIP_REG_TX_PAYLD_REG23 0x000001dc
/* [0x1e0]: REG tx payload reg24 */
#define MRFIP_REG_TX_PAYLD_REG24 0x000001e0
/* [0x1e4]: REG tx payload reg25 */
#define MRFIP_REG_TX_PAYLD_REG25 0x000001e4
/* [0x1e8]: REG tx payload reg26 */
#define MRFIP_REG_TX_PAYLD_REG26 0x000001e8
/* [0x1ec]: REG tx payload reg27 */
#define MRFIP_REG_TX_PAYLD_REG27 0x000001ec
/* [0x1f0]: REG tx payload reg28 */
#define MRFIP_REG_TX_PAYLD_REG28 0x000001f0
/* [0x1f4]: REG tx payload reg29 */
#define MRFIP_REG_TX_PAYLD_REG29 0x000001f4
/* [0x1f8]: REG tx payload reg30 */
#define MRFIP_REG_TX_PAYLD_REG30 0x000001f8
/* [0x1fc]: REG tx payload reg31 */
#define MRFIP_REG_TX_PAYLD_REG31 0x000001fc
/* [0x200]: REG tx payload reg32 */
#define MRFIP_REG_TX_PAYLD_REG32 0x00000200
/* [0x204]: REG tx payload reg33 */
#define MRFIP_REG_TX_PAYLD_REG33 0x00000204
/* [0x208]: REG tx payload reg34 */
#define MRFIP_REG_TX_PAYLD_REG34 0x00000208
/* [0x20c]: REG tx payload reg35 */
#define MRFIP_REG_TX_PAYLD_REG35 0x0000020c
/* [0x210]: REG tx payload reg36 */
#define MRFIP_REG_TX_PAYLD_REG36 0x00000210
/* [0x214]: REG tx payload reg37 */
#define MRFIP_REG_TX_PAYLD_REG37 0x00000214
/* [0x218]: REG tx payload reg38 */
#define MRFIP_REG_TX_PAYLD_REG38 0x00000218
/* [0x21c]: REG tx payload reg39 */
#define MRFIP_REG_TX_PAYLD_REG39 0x0000021c
/* [0x220]: REG tx payload reg40 */
#define MRFIP_REG_TX_PAYLD_REG40 0x00000220
/* [0x224]: REG tx payload reg41 */
#define MRFIP_REG_TX_PAYLD_REG41 0x00000224
/* [0x228]: REG tx payload reg42 */
#define MRFIP_REG_TX_PAYLD_REG42 0x00000228
/* [0x22c]: REG tx payload reg43 */
#define MRFIP_REG_TX_PAYLD_REG43 0x0000022c
/* [0x230]: REG tx payload reg44 */
#define MRFIP_REG_TX_PAYLD_REG44 0x00000230
/* [0x234]: REG tx payload reg45 */
#define MRFIP_REG_TX_PAYLD_REG45 0x00000234
/* [0x238]: REG tx payload reg46 */
#define MRFIP_REG_TX_PAYLD_REG46 0x00000238
/* [0x23c]: REG tx payload reg47 */
#define MRFIP_REG_TX_PAYLD_REG47 0x0000023c
/* [0x240]: REG tx payload reg48 */
#define MRFIP_REG_TX_PAYLD_REG48 0x00000240
/* [0x244]: REG tx payload reg49 */
#define MRFIP_REG_TX_PAYLD_REG49 0x00000244
/* [0x248]: REG tx payload reg50 */
#define MRFIP_REG_TX_PAYLD_REG50 0x00000248
/* [0x24c]: REG tx payload reg51 */
#define MRFIP_REG_TX_PAYLD_REG51 0x0000024c
/* [0x250]: REG tx payload reg52 */
#define MRFIP_REG_TX_PAYLD_REG52 0x00000250
/* [0x254]: REG tx payload reg53 */
#define MRFIP_REG_TX_PAYLD_REG53 0x00000254
/* [0x258]: REG tx payload reg54 */
#define MRFIP_REG_TX_PAYLD_REG54 0x00000258
/* [0x25c]: REG tx payload reg55 */
#define MRFIP_REG_TX_PAYLD_REG55 0x0000025c
/* [0x260]: REG tx payload reg56 */
#define MRFIP_REG_TX_PAYLD_REG56 0x00000260
/* [0x264]: REG tx payload reg57 */
#define MRFIP_REG_TX_PAYLD_REG57 0x00000264
/* [0x268]: REG tx payload reg58 */
#define MRFIP_REG_TX_PAYLD_REG58 0x00000268
/* [0x26c]: REG tx payload reg59 */
#define MRFIP_REG_TX_PAYLD_REG59 0x0000026c
/* [0x270]: REG tx payload reg60 */
#define MRFIP_REG_TX_PAYLD_REG60 0x00000270
/* [0x274]: REG tx payload reg61 */
#define MRFIP_REG_TX_PAYLD_REG61 0x00000274
/* [0x278]: REG tx payload reg62 */
#define MRFIP_REG_TX_PAYLD_REG62 0x00000278
/* [0x27c]: REG tx payload reg63 */
#define MRFIP_REG_TX_PAYLD_REG63 0x0000027c
/* [0x280]: REG tx payload reg64 */
#define MRFIP_REG_TX_PAYLD_REG64 0x00000280
/* [0x284]: REG tx payload reg65 */
#define MRFIP_REG_TX_PAYLD_REG65 0x00000284
/* [0x288]: REG tx payload reg66 */
#define MRFIP_REG_TX_PAYLD_REG66 0x00000288
/* [0x28c]: REG tx payload reg67 */
#define MRFIP_REG_TX_PAYLD_REG67 0x0000028c
#endif
rtl/wbgen/fmc_masterfip_csr.htm
View file @ 3de128f4
This source diff could not be displayed because it is too large. You can view the blob instead.
rtl/wbgen/fmc_masterfip_csr.wb
View file @ 3de128f4
......@@ -3,7 +3,7 @@ peripheral {
description = "Wishbone slave for FMC masterFIP core";
hdl_entity = "fmc_masterfip_csr";
prefix = "mf";
prefix = "mrfip";
-------------------------------------------------------------------------------
-- reset --
......@@ -236,8 +236,8 @@ peripheral {
};
field {
name = "transceiver output enable";
prefix = "oe";
name = "transceiver output enable negative logic";
prefix = "oe_n";
description = "write 0: normal operation, the external sync pulse arrives to the FPGA\
write 1: the external sync pulse does not arrive to the FPGA";
type = BIT;
......@@ -313,7 +313,7 @@ peripheral {
description = "duration of the macrocycle in number of 10ns-clk-ticks";
prefix = "lgth";
type = SLV;
size = 32;
size = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -337,7 +337,7 @@ peripheral {
description = "turnaround time (i.e. time between two frames sent by the masterFIP) in number of 10ns-clk-ticks";
prefix = "lgth";
type = SLV;
size = 32;
size = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -361,7 +361,7 @@ peripheral {
description = "silence time (i.e. time that the masterFIP waits for a response frame) number of 10ns-clk-ticks";
prefix = "lgth";
type = SLV;
size = 32;
size = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -385,7 +385,7 @@ peripheral {
name = "macrocycle time counter";
description = "current value of the macrocycle time counter";
type = SLV;
size = 32;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......@@ -414,7 +414,7 @@ peripheral {
name = "turnaround time counter";
description = "current value of the turnaround time counter";
type = SLV;
size = 32;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......@@ -428,7 +428,7 @@ peripheral {
name = "silence time counter";
description = "current value of the silence time counter";
type = SLV;
size = 32;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......@@ -454,8 +454,8 @@ peripheral {
field {
name = "tx strt";
description = "write 1: initiates the serializer to send a frame of tx_ctrl_bytes_num data bytes;\
the bytes are retrieved one-by-one by the registers: tx_data_ctrl, tx_data_reg1..tx_data_reg67;\
description = "write 1: initiates the serializer to send a frame of tx_ctrl_bytes_num payload bytes;\
the bytes are retrieved one-by-one by the registers: tx_payld_ctrl, tx_payld_reg1..tx_payld_reg67;\
the bytes: FSS, CRC and FES are generated automatically by the serializer.\
note: there is no need to clear the field before writing another '1'";
prefix = "start";
......@@ -672,8 +672,8 @@ peripheral {
name = "rx number of payload bytes";
description = "number of payload bytes that have been received by the deserializer\
upon the rx_frame_ok activation.\
The counter includes all the bytes that come after the CTRL byte and before the CRC bytes.\
note that for the max WorldFIP frame size = 262 bytes (without preamble, CTRL, CRC, postamble)";
The counter includes all the bytes that come after the Control byte and before the CRC bytes.\
note that for the max WorldFIP frame size = 262 bytes (without preamble, Control, CRC, postamble)";
prefix = "bytes_num";
type = SLV;
size = 16;
......@@ -690,7 +690,7 @@ peripheral {
field {
name = "current word index";
description = "index of the current 32-bit-word being deserialized;\
word 1: LSB is the CTRL byte; the other 3 bytes are to be ignored\
word 1: LSB is the Control byte; the other 3 bytes are to be ignored\
word 2: contains the first 4 payload bytes..etc\
The max frame size is 66 words.\
The last word may also include CRC bytes;\
......@@ -718,16 +718,16 @@ peripheral {
};
-------------------------------------------------------------------------------
-- rx data bytes --
-- rx payload bytes --
-------------------------------------------------------------------------------
reg {
name = "rx data ctrl byte";
prefix = "rx_data_ctrl";
name = "rx payload ctrl byte";
prefix = "rx_payld_ctrl";
description = "contains the 8-bits of the control field of a received frame";
field {
name = "rx data ctrl byte";
name = "rx payload ctrl byte";
description = "contains the 8-bits of the control field of a received frame";
type = SLV;
size = 8;
......@@ -737,8 +737,8 @@ peripheral {
};
reg {
name = "rx data reg1";
prefix = "rx_data_reg1";
name = "rx payload reg1";
prefix = "rx_payld_reg1";
description = "32 bits of the received frame";
field {
......@@ -752,8 +752,8 @@ peripheral {
};
reg {
name = "rx data reg2";
prefix = "rx_data_reg2";
name = "rx payload reg2";
prefix = "rx_payld_reg2";
description = "32 bits of the received frame";
field {
......@@ -767,8 +767,8 @@ peripheral {
};
reg {
name = "rx data reg3";
prefix = "rx_data_reg3";
name = "rx payload reg3";
prefix = "rx_payld_reg3";
description = "32 bits of the received frame";
field {
......@@ -782,8 +782,8 @@ peripheral {
};
reg {
name = "rx data reg4";
prefix = "rx_data_reg4";
name = "rx payload reg4";
prefix = "rx_payld_reg4";
description = "32 bits of the received frame";
field {
......@@ -797,8 +797,8 @@ peripheral {
};
reg {
name = "rx data reg5";
prefix = "rx_data_reg5";
name = "rx payload reg5";
prefix = "rx_payld_reg5";
description = "32 bits of the received frame";
field {
......@@ -812,8 +812,8 @@ peripheral {
};
reg {
name = "rx data reg6";
prefix = "rx_data_reg6";
name = "rx payload reg6";
prefix = "rx_payld_reg6";
description = "32 bits of the received frame";
field {
......@@ -827,8 +827,8 @@ peripheral {
};
reg {
name = "rx data reg7";
prefix = "rx_data_reg7";
name = "rx payload reg7";
prefix = "rx_payld_reg7";
description = "32 bits of the received frame";
field {
......@@ -842,8 +842,8 @@ peripheral {
};
reg {
name = "rx data reg8";
prefix = "rx_data_reg8";
name = "rx payload reg8";
prefix = "rx_payld_reg8";
description = "32 bits of the received frame";
field {
......@@ -857,8 +857,8 @@ peripheral {
};
reg {
name = "rx data reg9";
prefix = "rx_data_reg9";
name = "rx payload reg9";
prefix = "rx_payld_reg9";
description = "32 bits of the received frame";
field {
......@@ -872,8 +872,8 @@ peripheral {
};
reg {
name = "rx data reg10";
prefix = "rx_data_reg10";
name = "rx payload reg10";
prefix = "rx_payld_reg10";
description = "32 bits of the received frame";
field {
......@@ -887,8 +887,8 @@ peripheral {
};
reg {
name = "rx data reg11";
prefix = "rx_data_reg11";
name = "rx payload reg11";
prefix = "rx_payld_reg11";
description = "32 bits of the received frame";
field {
......@@ -902,8 +902,8 @@ peripheral {
};
reg {
name = "rx data reg12";
prefix = "rx_data_reg12";
name = "rx payload reg12";
prefix = "rx_payld_reg12";
description = "32 bits of the received frame";
field {
......@@ -917,8 +917,8 @@ peripheral {
};
reg {
name = "rx data reg13";
prefix = "rx_data_reg13";
name = "rx payload reg13";
prefix = "rx_payld_reg13";
description = "32 bits of the received frame";
field {
......@@ -932,8 +932,8 @@ peripheral {
};
reg {
name = "rx data reg14";
prefix = "rx_data_reg14";
name = "rx payload reg14";
prefix = "rx_payld_reg14";
description = "32 bits of the received frame";
field {
......@@ -947,8 +947,8 @@ peripheral {
};
reg {
name = "rx data reg15";
prefix = "rx_data_reg15";
name = "rx payload reg15";
prefix = "rx_payld_reg15";
description = "32 bits of the received frame";
field {
......@@ -962,8 +962,8 @@ peripheral {
};
reg {
name = "rx data reg16";
prefix = "rx_data_reg16";
name = "rx payload reg16";
prefix = "rx_payld_reg16";
description = "32 bits of the received frame";
field {
......@@ -977,8 +977,8 @@ peripheral {
};
reg {
name = "rx data reg17";
prefix = "rx_data_reg17";
name = "rx payload reg17";
prefix = "rx_payld_reg17";
description = "32 bits of the received frame";
field {
......@@ -992,8 +992,8 @@ peripheral {
};
reg {
name = "rx data reg18";
prefix = "rx_data_reg18";
name = "rx payload reg18";
prefix = "rx_payld_reg18";
description = "32 bits of the received frame";
field {
......@@ -1007,8 +1007,8 @@ peripheral {
};
reg {
name = "rx data reg19";
prefix = "rx_data_reg19";
name = "rx payload reg19";
prefix = "rx_payld_reg19";
description = "32 bits of the received frame";
field {
......@@ -1022,8 +1022,8 @@ peripheral {
};
reg {
name = "rx data reg20";
prefix = "rx_data_reg20";
name = "rx payload reg20";
prefix = "rx_payld_reg20";
description = "32 bits of the received frame";
field {
......@@ -1037,8 +1037,8 @@ peripheral {
};
reg {
name = "rx data reg21";
prefix = "rx_data_reg21";
name = "rx payload reg21";
prefix = "rx_payld_reg21";
description = "32 bits of the received frame";
field {
......@@ -1052,8 +1052,8 @@ peripheral {
};
reg {
name = "rx data reg22";
prefix = "rx_data_reg22";
name = "rx payload reg22";
prefix = "rx_payld_reg22";
description = "32 bits of the received frame";
field {
......@@ -1067,8 +1067,8 @@ peripheral {
};
reg {
name = "rx data reg23";
prefix = "rx_data_reg23";
name = "rx payload reg23";
prefix = "rx_payld_reg23";
description = "32 bits of the received frame";
field {
......@@ -1082,8 +1082,8 @@ peripheral {
};
reg {
name = "rx data reg24";
prefix = "rx_data_reg24";
name = "rx payload reg24";
prefix = "rx_payld_reg24";
description = "32 bits of the received frame";
field {
......@@ -1097,8 +1097,8 @@ peripheral {
};
reg {
name = "rx data reg25";
prefix = "rx_data_reg25";
name = "rx payload reg25";
prefix = "rx_payld_reg25";
description = "32 bits of the received frame";
field {
......@@ -1112,8 +1112,8 @@ peripheral {
};
reg {
name = "rx data reg26";
prefix = "rx_data_reg26";
name = "rx payload reg26";
prefix = "rx_payld_reg26";
description = "32 bits of the received frame";
field {
......@@ -1127,8 +1127,8 @@ peripheral {
};
reg {
name = "rx data reg27";
prefix = "rx_data_reg27";
name = "rx payload reg27";
prefix = "rx_payld_reg27";
description = "32 bits of the received frame";
field {
......@@ -1142,8 +1142,8 @@ peripheral {
};
reg {
name = "rx data reg28";
prefix = "rx_data_reg28";
name = "rx payload reg28";
prefix = "rx_payld_reg28";
description = "32 bits of the received frame";
field {
......@@ -1157,8 +1157,8 @@ peripheral {
};
reg {
name = "rx data reg29";
prefix = "rx_data_reg29";
name = "rx payload reg29";
prefix = "rx_payld_reg29";
description = "32 bits of the received frame";
field {
......@@ -1172,8 +1172,8 @@ peripheral {
};
reg {
name = "rx data reg30";
prefix = "rx_data_reg30";
name = "rx payload reg30";
prefix = "rx_payld_reg30";
description = "32 bits of the received frame";
field {
......@@ -1187,8 +1187,8 @@ peripheral {
};
reg {
name = "rx data reg31";
prefix = "rx_data_reg31";
name = "rx payload reg31";
prefix = "rx_payld_reg31";
description = "32 bits of the received frame";
field {
......@@ -1202,8 +1202,8 @@ peripheral {
};
reg {
name = "rx data reg32";
prefix = "rx_data_reg32";
name = "rx payload reg32";
prefix = "rx_payld_reg32";
description = "32 bits of the received frame";
field {
......@@ -1217,8 +1217,8 @@ peripheral {
};
reg {
name = "rx data reg33";
prefix = "rx_data_reg33";
name = "rx payload reg33";
prefix = "rx_payld_reg33";
description = "32 bits of the received frame";
field {
......@@ -1232,8 +1232,8 @@ peripheral {
};
reg {
name = "rx data reg34";
prefix = "rx_data_reg34";
name = "rx payload reg34";
prefix = "rx_payld_reg34";
description = "32 bits of the received frame";
field {
......@@ -1247,8 +1247,8 @@ peripheral {
};
reg {
name = "rx data reg35";
prefix = "rx_data_reg35";
name = "rx payload reg35";
prefix = "rx_payld_reg35";
description = "32 bits of the received frame";
field {
......@@ -1262,8 +1262,8 @@ peripheral {
};
reg {
name = "rx data reg36";
prefix = "rx_data_reg36";
name = "rx payload reg36";
prefix = "rx_payld_reg36";
description = "32 bits of the received frame";
field {
......@@ -1277,8 +1277,8 @@ peripheral {
};
reg {
name = "rx data reg37";
prefix = "rx_data_reg37";
name = "rx payload reg37";
prefix = "rx_payld_reg37";
description = "32 bits of the received frame";
field {
......@@ -1292,8 +1292,8 @@ peripheral {
};
reg {
name = "rx data reg38";
prefix = "rx_data_reg38";
name = "rx payload reg38";
prefix = "rx_payld_reg38";
description = "32 bits of the received frame";
field {
......@@ -1307,8 +1307,8 @@ peripheral {
};
reg {
name = "rx data reg39";
prefix = "rx_data_reg39";
name = "rx payload reg39";
prefix = "rx_payld_reg39";
description = "32 bits of the received frame";
field {
......@@ -1322,8 +1322,8 @@ peripheral {
};
reg {
name = "rx data reg40";
prefix = "rx_data_reg40";
name = "rx payload reg40";
prefix = "rx_payld_reg40";
description = "32 bits of the received frame";
field {
......@@ -1337,8 +1337,8 @@ peripheral {
};
reg {
name = "rx data reg41";
prefix = "rx_data_reg41";
name = "rx payload reg41";
prefix = "rx_payld_reg41";
description = "32 bits of the received frame";
field {
......@@ -1352,8 +1352,8 @@ peripheral {
};
reg {
name = "rx data reg42";
prefix = "rx_data_reg42";
name = "rx payload reg42";
prefix = "rx_payld_reg42";
description = "32 bits of the received frame";
field {
......@@ -1367,8 +1367,8 @@ peripheral {
};
reg {
name = "rx data reg43";
prefix = "rx_data_reg43";
name = "rx payload reg43";
prefix = "rx_payld_reg43";
description = "32 bits of the received frame";
field {
......@@ -1382,8 +1382,8 @@ peripheral {
};
reg {
name = "rx data reg44";
prefix = "rx_data_reg44";
name = "rx payload reg44";
prefix = "rx_payld_reg44";
description = "32 bits of the received frame";
field {
......@@ -1397,8 +1397,8 @@ peripheral {
};
reg {
name = "rx data reg45";
prefix = "rx_data_reg45";
name = "rx payload reg45";
prefix = "rx_payld_reg45";
description = "32 bits of the received frame";
field {
......@@ -1412,8 +1412,8 @@ peripheral {
};
reg {
name = "rx data reg46";
prefix = "rx_data_reg46";
name = "rx payload reg46";
prefix = "rx_payld_reg46";
description = "32 bits of the received frame";
field {
......@@ -1427,8 +1427,8 @@ peripheral {
};
reg {
name = "rx data reg47";
prefix = "rx_data_reg47";
name = "rx payload reg47";
prefix = "rx_payld_reg47";
description = "32 bits of the received frame";
field {
......@@ -1442,8 +1442,8 @@ peripheral {
};
reg {
name = "rx data reg48";
prefix = "rx_data_reg48";
name = "rx payload reg48";
prefix = "rx_payld_reg48";
description = "32 bits of the received frame";
field {
......@@ -1457,8 +1457,8 @@ peripheral {
};
reg {
name = "rx data reg49";
prefix = "rx_data_reg49";
name = "rx payload reg49";
prefix = "rx_payld_reg49";
description = "32 bits of the received frame";
field {
......@@ -1472,8 +1472,8 @@ peripheral {
};
reg {
name = "rx data reg50";
prefix = "rx_data_reg50";
name = "rx payload reg50";
prefix = "rx_payld_reg50";
description = "32 bits of the received frame";
field {
......@@ -1487,8 +1487,8 @@ peripheral {
};
reg {
name = "rx data reg51";
prefix = "rx_data_reg51";
name = "rx payload reg51";
prefix = "rx_payld_reg51";
description = "32 bits of the received frame";
field {
......@@ -1502,8 +1502,8 @@ peripheral {
};
reg {
name = "rx data reg52";
prefix = "rx_data_reg52";
name = "rx payload reg52";
prefix = "rx_payld_reg52";
description = "32 bits of the received frame";
field {
......@@ -1517,8 +1517,8 @@ peripheral {
};
reg {
name = "rx data reg53";
prefix = "rx_data_reg53";
name = "rx payload reg53";
prefix = "rx_payld_reg53";
description = "32 bits of the received frame";
field {
......@@ -1532,8 +1532,8 @@ peripheral {
};
reg {
name = "rx data reg54";
prefix = "rx_data_reg54";
name = "rx payload reg54";
prefix = "rx_payld_reg54";
description = "32 bits of the received frame";
field {
......@@ -1547,8 +1547,8 @@ peripheral {
};
reg {
name = "rx data reg55";
prefix = "rx_data_reg55";
name = "rx payload reg55";
prefix = "rx_payld_reg55";
description = "32 bits of the received frame";
field {
......@@ -1562,8 +1562,8 @@ peripheral {
};
reg {
name = "rx data reg56";
prefix = "rx_data_reg56";
name = "rx payload reg56";
prefix = "rx_payld_reg56";
description = "32 bits of the received frame";
field {
......@@ -1577,8 +1577,8 @@ peripheral {
};
reg {
name = "rx data reg57";
prefix = "rx_data_reg57";
name = "rx payload reg57";
prefix = "rx_payld_reg57";
description = "32 bits of the received frame";
field {
......@@ -1592,8 +1592,8 @@ peripheral {
};
reg {
name = "rx data reg58";
prefix = "rx_data_reg58";
name = "rx payload reg58";
prefix = "rx_payld_reg58";
description = "32 bits of the received frame";
field {
......@@ -1607,8 +1607,8 @@ peripheral {
};
reg {
name = "rx data reg59";
prefix = "rx_data_reg59";
name = "rx payload reg59";
prefix = "rx_payld_reg59";
description = "32 bits of the received frame";
field {
......@@ -1622,8 +1622,8 @@ peripheral {
};
reg {
name = "rx data reg60";
prefix = "rx_data_reg60";
name = "rx payload reg60";
prefix = "rx_payld_reg60";
description = "32 bits of the received frame";
field {
......@@ -1637,8 +1637,8 @@ peripheral {
};
reg {
name = "rx data reg61";
prefix = "rx_data_reg61";
name = "rx payload reg61";
prefix = "rx_payld_reg61";
description = "32 bits of the received frame";
field {
......@@ -1652,8 +1652,8 @@ peripheral {
};
reg {
name = "rx data reg62";
prefix = "rx_data_reg62";
name = "rx payload reg62";
prefix = "rx_payld_reg62";
description = "32 bits of the received frame";
field {
......@@ -1667,8 +1667,8 @@ peripheral {
};
reg {
name = "rx data reg63";
prefix = "rx_data_reg63";
name = "rx payload reg63";
prefix = "rx_payld_reg63";
description = "32 bits of the received frame";
field {
......@@ -1682,8 +1682,8 @@ peripheral {
};
reg {
name = "rx data reg64";
prefix = "rx_data_reg64";
name = "rx payload reg64";
prefix = "rx_payld_reg64";
description = "32 bits of the received frame";
field {
......@@ -1697,8 +1697,8 @@ peripheral {
};
reg {
name = "rx data reg65";
prefix = "rx_data_reg65";
name = "rx payload reg65";
prefix = "rx_payld_reg65";
description = "32 bits of the received frame";
field {
......@@ -1712,8 +1712,8 @@ peripheral {
};
reg {
name = "rx data reg66";
prefix = "rx_data_reg66";
name = "rx payload reg66";
prefix = "rx_payld_reg66";
description = "32 bits of the received frame";
field {
......@@ -1727,8 +1727,8 @@ peripheral {
};
reg {
name = "rx data reg67";
prefix = "rx_data_reg67";
name = "rx payload reg67";
prefix = "rx_payld_reg67";
description = "32 bits of the received frame";
field {
......@@ -1742,12 +1742,12 @@ peripheral {
};
-------------------------------------------------------------------------------
-- tx data --
-- tx payload --
-------------------------------------------------------------------------------
reg {
name = "tx ctrl byte";
prefix = "tx_data_ctrl";
prefix = "tx_payld_ctrl";
description = "contains the 8-bits of the control field of a frame to transmit";
field {
......@@ -1761,8 +1761,8 @@ peripheral {
};
reg {
name = "tx data reg1";
prefix = "tx_data_reg1";
name = "tx payload reg1";
prefix = "tx_payld_reg1";
description = "32 bits of the received frame";
field {
......@@ -1776,8 +1776,8 @@ peripheral {
};
reg {
name = "tx data reg2";
prefix = "tx_data_reg2";
name = "tx payload reg2";
prefix = "tx_payld_reg2";
description = "32 bits of the received frame";
field {
......@@ -1791,8 +1791,8 @@ peripheral {
};
reg {
name = "tx data reg3";
prefix = "tx_data_reg3";
name = "tx payload reg3";
prefix = "tx_payld_reg3";
description = "32 bits of the received frame";
field {
......@@ -1806,8 +1806,8 @@ peripheral {
};
reg {
name = "tx data reg4";
prefix = "tx_data_reg4";
name = "tx payload reg4";
prefix = "tx_payld_reg4";
description = "32 bits of the received frame";
field {
......@@ -1821,8 +1821,8 @@ peripheral {
};
reg {
name = "tx data reg5";
prefix = "tx_data_reg5";
name = "tx payload reg5";
prefix = "tx_payld_reg5";
description = "32 bits of the received frame";
field {
......@@ -1836,8 +1836,8 @@ peripheral {
};
reg {
name = "tx data reg6";
prefix = "tx_data_reg6";
name = "tx payload reg6";
prefix = "tx_payld_reg6";
description = "32 bits of the received frame";
field {
......@@ -1851,8 +1851,8 @@ peripheral {
};
reg {
name = "tx data reg7";
prefix = "tx_data_reg7";
name = "tx payload reg7";
prefix = "tx_payld_reg7";
description = "32 bits of the received frame";
field {
......@@ -1866,8 +1866,8 @@ peripheral {
};
reg {
name = "tx data reg8";
prefix = "tx_data_reg8";
name = "tx payload reg8";
prefix = "tx_payld_reg8";
description = "32 bits of the received frame";
field {
......@@ -1881,8 +1881,8 @@ peripheral {
};
reg {
name = "tx data reg9";
prefix = "tx_data_reg9";
name = "tx payload reg9";
prefix = "tx_payld_reg9";
description = "32 bits of the received frame";
field {
......@@ -1896,8 +1896,8 @@ peripheral {
};
reg {
name = "tx data reg10";
prefix = "tx_data_reg10";
name = "tx payload reg10";
prefix = "tx_payld_reg10";
description = "32 bits of the received frame";
field {
......@@ -1911,8 +1911,8 @@ peripheral {
};
reg {
name = "tx data reg11";
prefix = "tx_data_reg11";
name = "tx payload reg11";
prefix = "tx_payld_reg11";
description = "32 bits of the received frame";
field {
......@@ -1926,8 +1926,8 @@ peripheral {
};
reg {
name = "tx data reg12";
prefix = "tx_data_reg12";
name = "tx payload reg12";
prefix = "tx_payld_reg12";
description = "32 bits of the received frame";
field {
......@@ -1940,8 +1940,8 @@ peripheral {
};
};
reg {
name = "tx data reg13";
prefix = "tx_data_reg13";
name = "tx payload reg13";
prefix = "tx_payld_reg13";
description = "32 bits of the received frame";
field {
......@@ -1954,8 +1954,8 @@ peripheral {
};
};
reg {
name = "tx data reg14";
prefix = "tx_data_reg14";
name = "tx payload reg14";
prefix = "tx_payld_reg14";
description = "32 bits of the received frame";
field {
......@@ -1969,8 +1969,8 @@ peripheral {
};
reg {
name = "tx data reg15";
prefix = "tx_data_reg15";
name = "tx payload reg15";
prefix = "tx_payld_reg15";
description = "32 bits of the received frame";
field {
......@@ -1984,8 +1984,8 @@ peripheral {
};
reg {
name = "tx data reg16";
prefix = "tx_data_reg16";
name = "tx payload reg16";
prefix = "tx_payld_reg16";
description = "32 bits of the received frame";
field {
......@@ -1999,8 +1999,8 @@ peripheral {
};
reg {
name = "tx data reg17";
prefix = "tx_data_reg17";
name = "tx payload reg17";
prefix = "tx_payld_reg17";
description = "32 bits of the received frame";
field {
......@@ -2014,8 +2014,8 @@ peripheral {
};
reg {
name = "tx data reg18";
prefix = "tx_data_reg18";
name = "tx payload reg18";
prefix = "tx_payld_reg18";
description = "32 bits of the received frame";
field {
......@@ -2029,8 +2029,8 @@ peripheral {
};
reg {
name = "tx data reg19";
prefix = "tx_data_reg19";
name = "tx payload reg19";
prefix = "tx_payld_reg19";
description = "32 bits of the received frame";
field {
......@@ -2044,8 +2044,8 @@ peripheral {
};
reg {
name = "tx data reg20";
prefix = "tx_data_reg20";
name = "tx payload reg20";
prefix = "tx_payld_reg20";
description = "32 bits of the received frame";
field {
......@@ -2059,8 +2059,8 @@ peripheral {
};
reg {
name = "tx data reg21";
prefix = "tx_data_reg21";
name = "tx payload reg21";
prefix = "tx_payld_reg21";
description = "32 bits of the received frame";
field {
......@@ -2074,8 +2074,8 @@ peripheral {
};
reg {
name = "tx data reg22";
prefix = "tx_data_reg22";
name = "tx payload reg22";
prefix = "tx_payld_reg22";
description = "32 bits of the received frame";
field {
......@@ -2089,8 +2089,8 @@ peripheral {
};
reg {
name = "tx data reg23";
prefix = "tx_data_reg23";
name = "tx payload reg23";
prefix = "tx_payld_reg23";
description = "32 bits of the received frame";
field {
......@@ -2104,8 +2104,8 @@ peripheral {
};
reg {
name = "tx data reg24";
prefix = "tx_data_reg24";
name = "tx payload reg24";
prefix = "tx_payld_reg24";
description = "32 bits of the received frame";
field {
......@@ -2119,8 +2119,8 @@ peripheral {
};
reg {
name = "tx data reg25";
prefix = "tx_data_reg25";
name = "tx payload reg25";
prefix = "tx_payld_reg25";
description = "32 bits of the received frame";
field {
......@@ -2134,8 +2134,8 @@ peripheral {
};
reg {
name = "tx data reg26";
prefix = "tx_data_reg26";
name = "tx payload reg26";
prefix = "tx_payld_reg26";
description = "32 bits of the received frame";
field {
......@@ -2148,8 +2148,8 @@ peripheral {
};
};
reg {
name = "tx data reg27";
prefix = "tx_data_reg27";
name = "tx payload reg27";
prefix = "tx_payld_reg27";
description = "32 bits of the received frame";
field {
......@@ -2163,8 +2163,8 @@ peripheral {
};
reg {
name = "tx data reg28";
prefix = "tx_data_reg28";
name = "tx payload reg28";
prefix = "tx_payld_reg28";
description = "32 bits of the received frame";
field {
......@@ -2178,8 +2178,8 @@ peripheral {
};
reg {
name = "tx data reg29";
prefix = "tx_data_reg29";
name = "tx payload reg29";
prefix = "tx_payld_reg29";
description = "32 bits of the received frame";
field {
......@@ -2193,8 +2193,8 @@ peripheral {
};
reg {
name = "tx data reg30";
prefix = "tx_data_reg30";
name = "tx payload reg30";
prefix = "tx_payld_reg30";
description = "32 bits of the received frame";
field {
......@@ -2208,8 +2208,8 @@ peripheral {
};
reg {
name = "tx data reg31";
prefix = "tx_data_reg31";
name = "tx payload reg31";
prefix = "tx_payld_reg31";
description = "32 bits of the received frame";
field {
......@@ -2222,8 +2222,8 @@ peripheral {
};
};
reg {
name = "tx data reg32";
prefix = "tx_data_reg32";
name = "tx payload reg32";
prefix = "tx_payld_reg32";
description = "32 bits of the received frame";
field {
......@@ -2237,8 +2237,8 @@ peripheral {
};
reg {
name = "tx data reg33";
prefix = "tx_data_reg33";
name = "tx payload reg33";
prefix = "tx_payld_reg33";
description = "32 bits of the received frame";
field {
......@@ -2252,8 +2252,8 @@ peripheral {
};
reg {
name = "tx data reg34";
prefix = "tx_data_reg34";
name = "tx payload reg34";
prefix = "tx_payld_reg34";
description = "32 bits of the received frame";
field {
......@@ -2267,8 +2267,8 @@ peripheral {
};
reg {
name = "tx data reg35";
prefix = "tx_data_reg35";
name = "tx payload reg35";
prefix = "tx_payld_reg35";
description = "32 bits of the received frame";
field {
......@@ -2282,8 +2282,8 @@ peripheral {
};
reg {
name = "tx data reg36";
prefix = "tx_data_reg36";
name = "tx payload reg36";
prefix = "tx_payld_reg36";
description = "32 bits of the received frame";
field {
......@@ -2297,8 +2297,8 @@ peripheral {
};
reg {
name = "tx data reg37";
prefix = "tx_data_reg37";
name = "tx payload reg37";
prefix = "tx_payld_reg37";
description = "32 bits of the received frame";
field {
......@@ -2312,8 +2312,8 @@ peripheral {
};
reg {
name = "tx data reg38";
prefix = "tx_data_reg38";
name = "tx payload reg38";
prefix = "tx_payld_reg38";
description = "32 bits of the received frame";
field {
......@@ -2327,8 +2327,8 @@ peripheral {
};
reg {
name = "tx data reg39";
prefix = "tx_data_reg39";
name = "tx payload reg39";
prefix = "tx_payld_reg39";
description = "32 bits of the received frame";
field {
......@@ -2342,8 +2342,8 @@ peripheral {
};
reg {
name = "tx data reg40";
prefix = "tx_data_reg40";
name = "tx payload reg40";
prefix = "tx_payld_reg40";
description = "32 bits of the received frame";
field {
......@@ -2357,8 +2357,8 @@ peripheral {
};
reg {
name = "tx data reg41";
prefix = "tx_data_reg41";
name = "tx payload reg41";
prefix = "tx_payld_reg41";
description = "32 bits of the received frame";
field {
......@@ -2372,8 +2372,8 @@ peripheral {
};
reg {
name = "tx data reg42";
prefix = "tx_data_reg42";
name = "tx payload reg42";
prefix = "tx_payld_reg42";
description = "32 bits of the received frame";
field {
......@@ -2387,8 +2387,8 @@ peripheral {
};
reg {
name = "tx data reg43";
prefix = "tx_data_reg43";
name = "tx payload reg43";
prefix = "tx_payld_reg43";
description = "32 bits of the received frame";
field {
......@@ -2402,8 +2402,8 @@ peripheral {
};
reg {
name = "tx data reg44";
prefix = "tx_data_reg44";
name = "tx payload reg44";
prefix = "tx_payld_reg44";
description = "32 bits of the received frame";
field {
......@@ -2417,8 +2417,8 @@ peripheral {
};
reg {
name = "tx data reg45";
prefix = "tx_data_reg45";
name = "tx payload reg45";
prefix = "tx_payld_reg45";
description = "32 bits of the received frame";
field {
......@@ -2432,8 +2432,8 @@ peripheral {
};
reg {
name = "tx data reg46";
prefix = "tx_data_reg46";
name = "tx payload reg46";
prefix = "tx_payld_reg46";
description = "32 bits of the received frame";
field {
......@@ -2447,8 +2447,8 @@ peripheral {
};
reg {
name = "tx data reg47";
prefix = "tx_data_reg47";
name = "tx payload reg47";
prefix = "tx_payld_reg47";
description = "32 bits of the received frame";
field {
......@@ -2462,8 +2462,8 @@ peripheral {
};
reg {
name = "tx data reg48";
prefix = "tx_data_reg48";
name = "tx payload reg48";
prefix = "tx_payld_reg48";
description = "32 bits of the received frame";
field {
......@@ -2477,8 +2477,8 @@ peripheral {
};
reg {
name = "tx data reg49";
prefix = "tx_data_reg49";
name = "tx payload reg49";
prefix = "tx_payld_reg49";
description = "32 bits of the received frame";
field {
......@@ -2492,8 +2492,8 @@ peripheral {
};
reg {
name = "tx data reg50";
prefix = "tx_data_reg50";
name = "tx payload reg50";
prefix = "tx_payld_reg50";
description = "32 bits of the received frame";
field {
......@@ -2507,8 +2507,8 @@ peripheral {
};
reg {
name = "tx data reg51";
prefix = "tx_data_reg51";
name = "tx payload reg51";
prefix = "tx_payld_reg51";
description = "32 bits of the received frame";
field {
......@@ -2522,8 +2522,8 @@ peripheral {
};
reg {
name = "tx data reg52";
prefix = "tx_data_reg52";
name = "tx payload reg52";
prefix = "tx_payld_reg52";
description = "32 bits of the received frame";
field {
......@@ -2537,8 +2537,8 @@ peripheral {
};
reg {
name = "tx data reg53";
prefix = "tx_data_reg53";
name = "tx payload reg53";
prefix = "tx_payld_reg53";
description = "32 bits of the received frame";
field {
......@@ -2552,8 +2552,8 @@ peripheral {
};
reg {
name = "tx data reg54";
prefix = "tx_data_reg54";
name = "tx payload reg54";
prefix = "tx_payld_reg54";
description = "32 bits of the received frame";
field {
......@@ -2567,8 +2567,8 @@ peripheral {
};
reg {
name = "tx data reg55";
prefix = "tx_data_reg55";
name = "tx payload reg55";
prefix = "tx_payld_reg55";
description = "32 bits of the received frame";
field {
......@@ -2582,8 +2582,8 @@ peripheral {
};
reg {
name = "tx data reg56";
prefix = "tx_data_reg56";
name = "tx payload reg56";
prefix = "tx_payld_reg56";
description = "32 bits of the received frame";
field {
......@@ -2597,8 +2597,8 @@ peripheral {
};
reg {
name = "tx data reg57";
prefix = "tx_data_reg57";
name = "tx payload reg57";
prefix = "tx_payld_reg57";
description = "32 bits of the received frame";
field {
......@@ -2612,8 +2612,8 @@ peripheral {
};
reg {
name = "tx data reg58";
prefix = "tx_data_reg58";
name = "tx payload reg58";
prefix = "tx_payld_reg58";
description = "32 bits of the received frame";
field {
......@@ -2627,8 +2627,8 @@ peripheral {
};
reg {
name = "tx data reg59";
prefix = "tx_data_reg59";
name = "tx payload reg59";
prefix = "tx_payld_reg59";
description = "32 bits of the received frame";
field {
......@@ -2642,8 +2642,8 @@ peripheral {
};
reg {
name = "tx data reg60";
prefix = "tx_data_reg60";
name = "tx payload reg60";
prefix = "tx_payld_reg60";
description = "32 bits of the received frame";
field {
......@@ -2657,8 +2657,8 @@ peripheral {
};
reg {
name = "tx data reg61";
prefix = "tx_data_reg61";
name = "tx payload reg61";
prefix = "tx_payld_reg61";
description = "32 bits of the received frame";
field {
......@@ -2672,8 +2672,8 @@ peripheral {
};
reg {
name = "tx data reg62";
prefix = "tx_data_reg62";
name = "tx payload reg62";
prefix = "tx_payld_reg62";
description = "32 bits of the received frame";
field {
......@@ -2687,8 +2687,8 @@ peripheral {
};
reg {
name = "tx data reg63";
prefix = "tx_data_reg63";
name = "tx payload reg63";
prefix = "tx_payld_reg63";
description = "32 bits of the received frame";
field {
......@@ -2702,8 +2702,8 @@ peripheral {
};
reg {
name = "tx data reg64";
prefix = "tx_data_reg64";
name = "tx payload reg64";
prefix = "tx_payld_reg64";
description = "32 bits of the received frame";
field {
......@@ -2717,8 +2717,8 @@ peripheral {
};
reg {
name = "tx data reg65";
prefix = "tx_data_reg65";
name = "tx payload reg65";
prefix = "tx_payld_reg65";
description = "32 bits of the received frame";
field {
......@@ -2732,8 +2732,8 @@ peripheral {
};
reg {
name = "tx data reg66";
prefix = "tx_data_reg66";
name = "tx payload reg66";
prefix = "tx_payld_reg66";
description = "32 bits of the received frame";
field {
......@@ -2747,8 +2747,8 @@ peripheral {
};
reg {
name = "tx data reg67";
prefix = "tx_data_reg67";
name = "tx payload reg67";
prefix = "tx_payld_reg67";
description = "32 bits of the received frame";
field {
......
syn/spec/spec_masterfip.xise
View file @ 3de128f4
......@@ -16,11 +16,11 @@
<files>
<file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
......@@ -28,7 +28,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../rtl/irq_generator.vhd" xil_pn:type="FILE_VHDL">
......@@ -39,202 +39,37 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -300,15 +135,15 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
......@@ -316,20 +151,20 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -344,8 +179,8 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -480,8 +315,8 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -575,76 +410,28 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
......@@ -652,16 +439,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -671,153 +458,109 @@
</file>
<file xil_pn:name="../../top/spec/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterFIP_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../rtl/masterFIP_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../top/spec/spec_masterFIP.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<file xil_pn:name="../../sim/spec/testbench/tb_masterFIP.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/tb_masterFIP.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="101"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/gnum_model/util.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<file xil_pn:name="../../sim/spec/testbench/gnum_model/util.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/gnum_model/cmd_router.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="99"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/gnum_model/gn412x_bfm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/gnum_model/mem_model.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/gnum_model/textutil.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterfip_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/gnum_model/cmd_router1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_crc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_rx_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_rx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../rtl/masterfip_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_tx_serializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../rtl/masterfip_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../top/spec/spec_masterFIP.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/slone_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/slone_monitor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/user_access_monitor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/user_config.vhd" xil_pn:type="FILE_VHDL">
......@@ -825,7 +568,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/user_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/user_sequencer.vhd" xil_pn:type="FILE_VHDL">
......@@ -841,39 +584,15 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/tb_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/board_settings.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/encounter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.ngc" xil_pn:type="FILE_NGC">
......@@ -902,8 +621,8 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -911,147 +630,383 @@
</file>
<file xil_pn:name="../../top/spec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/dualram_512x8.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/nanofip.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_consumption.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_cons_bytes_processor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_cons_outcome.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_crc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_dualram_512x8_clka_rd_clkb_wr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_engine_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_fd_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_fd_transmitter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_jtag_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_model_constr_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_production.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_prod_bytes_retriever.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_prod_data_lgth_calc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_prod_permit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_reset_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_rx_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_rx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_status_bytes_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_wb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/>
</file>
<file xil_pn:name="../../rtl/onewire_interf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/mf_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_master_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_msel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_dec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_pri_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_rf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_slave_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wb_conmax_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/wbconmax_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_conmax/xwb_conmax.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......@@ -1437,6 +1392,8 @@
<!-- include files. -->
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
</project>
syn/spec/tb_masterFIP.fdo
View file @ 3de128f4
######################################################################
##
## Filename: tb_masterFIP.fdo
## Created on: Tue Oct 04 14:18:34 W. Europe Daylight Time 2016
## Created on: Thu Oct 20 12:14:30 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Behavioral Simulation
##
......@@ -20,21 +20,19 @@ vlib work
#
# Compile sources
#
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_package.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_sync_register.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_package.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/dualram_512x8.vhd"
vcom -explicit -93 "../../rtl/mf_wbgen2_pkg.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_incr_counter.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_decr_counter.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_crc.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_incr_counter.vhd"
vlib nanoFIP_lib
......@@ -60,7 +58,7 @@ vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vcom -explicit -93 "../../sim/spec/testbench/tb_package.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd"
......@@ -102,20 +100,19 @@ vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd"
vcom -explicit -93 "../../top/spec/synthesis_descriptor.vhd"
vcom -explicit -93 "../../top/spec/spec_reset_gen.vhd"
vcom -explicit -93 "../../sim/spec/testbench/wishbone_monitor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/wishbone_interface.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_sequencer.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_config.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_access_monitor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/slone_monitor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/slone_interface.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_wb_controller.vhd"
vlib nanoFIP_lib
......@@ -139,7 +136,7 @@ vcom -explicit -93 "../../sim/spec/testbench/gnum_model/cmd_router1.vhd"
vcom -explicit -93 "../../rtl/fmc_masterFIP_core.vhd"
vcom -explicit -93 "../../rtl/carrier_info.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 "../../top/spec/spec_masterFIP.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_interface.vhd"
vlib nanoFIP_lib
......
syn/spec_mt/spec_masterfip_mt.xise
View file @ 3de128f4
......@@ -19,9 +19,9 @@
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
<properties>
......@@ -354,9 +354,9 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd" xil_pn:type="FILE_VHDL">
......@@ -365,7 +365,7 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
......@@ -380,32 +380,32 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_eca/eca_flags.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_rx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_iram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
<file xil_pn:name="../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -414,31 +414,31 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
......@@ -446,19 +446,19 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_tx_serializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
......@@ -477,24 +477,24 @@
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_irq_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_eca/eca_queue_channel.vhd" xil_pn:type="FILE_VHDL">
......@@ -518,8 +518,8 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -533,7 +533,7 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
......@@ -546,16 +546,16 @@
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -563,14 +563,14 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
......@@ -579,37 +579,37 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterfip_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_eca/eca_gpio_channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
......@@ -617,7 +617,7 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
......@@ -626,19 +626,19 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
......@@ -647,11 +647,11 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_framer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
<file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
......@@ -660,9 +660,9 @@
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_core_with_etherbone.vhd" xil_pn:type="FILE_VHDL">
......@@ -672,12 +672,12 @@
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_csr_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd" xil_pn:type="FILE_VHDL">
......@@ -686,80 +686,80 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_remote.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
......@@ -771,10 +771,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wb_remapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -783,13 +783,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -797,55 +797,55 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_cb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_slot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/smem/wrn_shared_mem.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
......@@ -855,42 +855,42 @@
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_rx_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_host.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
......@@ -911,49 +911,49 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_template.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
......@@ -966,42 +966,42 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../rtl/masterFIP_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
......@@ -1011,7 +1011,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
......@@ -1019,35 +1019,35 @@
<file xil_pn:name="../../rtl/masterfip_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
......@@ -1058,16 +1058,16 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterFIP_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
......@@ -1077,22 +1077,22 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1103,26 +1103,26 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
......@@ -1130,8 +1130,8 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
......@@ -1139,10 +1139,10 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
......@@ -1151,38 +1151,38 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_lm32_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_eca/eca_wb_channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
......@@ -1193,61 +1193,61 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_crc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
</file>
<file xil_pn:name="../../rtl/masterfip_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
......@@ -1256,11 +1256,11 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_eca/eca.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1295,7 +1295,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="388"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="389"/>
......@@ -1306,7 +1306,7 @@
</file>
<file xil_pn:name="../../top/spec_mt/spec_masterfip_mt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="339"/>
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../../top/spec_mt/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="340"/>
......@@ -1314,7 +1314,15 @@
</file>
<file xil_pn:name="../../rtl/onewire_interf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="355"/>
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/mf_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="391"/>
<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="394"/>
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......
top/spec_mt/spec_masterfip_mt.ucf
View file @ 3de128f4
......@@ -178,9 +178,10 @@ NET "fmc_prsnt_m2c_l_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot
#----------------------------------------
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "mezz_onewire_b" LOC = "C18";
NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
......@@ -220,8 +221,8 @@ NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_tst_n_o" LOC = U8;
NET "ext_sync_tst_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_o" LOC = W6;
NET "ext_sync_oe_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_n_o" LOC = W6;
NET "ext_sync_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
......
top/spec_mt/spec_masterfip_mt.vhd
View file @ 3de128f4
......@@ -48,6 +48,7 @@ use work.spec_node_pkg.all;
use work.wrn_mqueue_pkg.all;
use work.wr_node_pkg.all;
use work.masterFIP_pkg.all;
use work.mrfip_wbgen2_pkg.all;
use work.gencores_pkg.all;
library unisim;
......@@ -104,10 +105,13 @@ entity spec_masterfip_mt is
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
-- Mezzanine 1-wire
mezz_onewire_b : inout std_logic;
-- WorldFIP external synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enable 50 Ohms termination of the pulse
ext_sync_dir_o : out std_logic; -- transceiver direction
ext_sync_oe_o : out std_logic; -- transceiver output enable
ext_sync_oe_n_o : out std_logic; -- transceiver output enable
ext_sync_tst_n_o : out std_logic; -- emulation of the LEMO input
ext_sync_i : in std_logic; -- sync pulse
......@@ -321,7 +325,7 @@ begin
-- External Synch pulse
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_dir_o => ext_sync_dir_o,
ext_sync_oe_o => ext_sync_oe_o,
ext_sync_oe_n_o => ext_sync_oe_n_o,
ext_sync_tst_n_o => ext_sync_tst_n_o,
ext_sync_i => ext_sync_i,
-- ADC relays and supplies
......@@ -334,6 +338,8 @@ begin
dac_cs_n_o => dac_cs_n_o,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o,
-- Mezzanine one-wire
onewire_b => mezz_onewire_b,
-- WISHBONE interface with
wb_adr_i => fmc_wb_muxed_out.adr,
wb_dat_i => fmc_wb_muxed_out.dat,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment