Commit 4055ba8d authored by Evangelia Gousiou's avatar Evangelia Gousiou

corrected mistake of unsynched rx_frame_ok and rx_bytes_num

parent 9ba467f9
...@@ -136,12 +136,12 @@ architecture rtl of fmc_masterFIP_core is ...@@ -136,12 +136,12 @@ architecture rtl of fmc_masterFIP_core is
signal tx_ctrl_byte : std_logic_vector(7 downto 0); signal tx_ctrl_byte : std_logic_vector(7 downto 0);
signal tx_bytes_num, tx_byte_index : std_logic_vector(8 downto 0); -- up to 263 bytes signal tx_bytes_num, tx_byte_index : std_logic_vector(8 downto 0); -- up to 263 bytes
-- rx -- rx
signal rx_fss_received_p, rx_fss_received : std_logic; signal rx_fss_received_p, rx_fss_received, rx_fss_crc_fes_ok_p : std_logic;
signal rx_fss_crc_fes_ok_p, rx_frame_ok_p, rx_frame_ok : std_logic; signal rx_frame_ok_p, rx_frame_ok, rx_frame_ok_p_d1 : std_logic;
signal rx_crc_wrong_p, rx_crc_wrong, rx_byte_ready_p, fd_txena : std_logic; signal rx_crc_wrong_p, rx_crc_wrong, rx_byte_ready_p, fd_txena : std_logic;
signal rx_frame : rx_frame_t; signal rx_frame : rx_frame_t;
signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0); signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0);
signal rx_byte_index, rx_data_bytes : std_logic_vector(8 downto 0); -- up to 263 bytes signal rx_byte_index, rx_bytes_num : std_logic_vector(8 downto 0); -- up to 263 bytes
-- chipscope -- chipscope
-- component chipscope_ila -- component chipscope_ila
...@@ -234,7 +234,7 @@ begin ...@@ -234,7 +234,7 @@ begin
mf_rx_stat_frame_ok_i => rx_frame_ok, mf_rx_stat_frame_ok_i => rx_frame_ok,
mf_rx_stat_frame_err_i => rx_crc_wrong, mf_rx_stat_frame_err_i => rx_crc_wrong,
mf_rx_stat_frame_err_code_i => "000", mf_rx_stat_frame_err_code_i => "000",
mf_rx_stat_bytes_num_i => rx_byte_index, -- rx_data_bytes, mf_rx_stat_bytes_num_i => rx_bytes_num,
-- rx data -- rx data
mf_rx_data_ctrl_i => rx_ctrl_byte, mf_rx_data_ctrl_i => rx_ctrl_byte,
mf_rx_data_reg1_i => rx_frame(0), mf_rx_data_reg1_i => rx_frame(0),
...@@ -516,7 +516,7 @@ begin ...@@ -516,7 +516,7 @@ begin
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
rst_n_i => core_rst_n, rst_n_i => core_rst_n,
pulse_i => rx_frame_ok_p, pulse_i => rx_frame_ok_p_d1,
extended_o => rx_frame_ok); extended_o => rx_frame_ok);
-- extension of the rx_crc_wrong_p so as to ensure capturing by the wrnc -- extension of the rx_crc_wrong_p so as to ensure capturing by the wrnc
...@@ -537,6 +537,22 @@ begin ...@@ -537,6 +537,22 @@ begin
data_i => rx_rst, data_i => rx_rst,
ppulse_o => rx_rst_p); ppulse_o => rx_rst_p);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- registering the number of received bytes
p_rx_bytes_num : process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n = '0') then
rx_bytes_num <= (others => '0');
rx_frame_ok_p_d1 <= '0';
else
rx_frame_ok_p_d1 <= rx_frame_ok_p;
if rx_frame_ok_p = '1' then
rx_bytes_num <= rx_byte_index;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- rx -- -- rx --
...@@ -560,10 +576,6 @@ begin ...@@ -560,10 +576,6 @@ begin
rx_crc_wrong_p_o => rx_crc_wrong_p); rx_crc_wrong_p_o => rx_crc_wrong_p);
------------------------------------------------------------- -------------------------------------------------------------
-- number of bytes to read from the rx_frame regs
-- size of data bytes (without fss, fes, ctrl, crc); check with an RP_FIN if ok!
rx_data_bytes <= (std_logic_vector(unsigned(rx_byte_index)-4));
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- tx -- -- tx --
......
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