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MasterFIP - Gateware
Commit 56cccd4f authored by kblantos's avatar kblantos
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Add another check in check_build script. Constraint file has now the correct pin for ertec_rst_i

parent 749af830
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Showing with 10 additions and 8 deletions
syn/svec/check_build.sh
View file @ 56cccd4f
......@@ -53,6 +53,12 @@ if [ $? -ne 0 ]; then
ret_error=1
fi
if [[ $(cat *.par | grep -c "All constraints were met") = 0 ]]
then
echo -e "\e[31mTiming errors detected in PAR report. Aborting...\e[0m"
exit 1
fi
if [ $ret_error -eq 1 ]; then
exit 1
......
top/svec/svec_masterfip_mt_urv.ucf
View file @ 56cccd4f
......@@ -16,7 +16,6 @@ NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
NET "ertec_spi_clk_i" LOC = "AC15";
NET "ertec_spi_clk_i" TIG;
#NET "ertec_spi_clk_i" CLOCK_DEDICATED_ROUTE = FALSE;
NET "ertec_spi_clk_i" IOSTANDARD = "LVCMOS25";
NET "ertec_spi_cs_n_i" LOC = "AB19";
......@@ -28,15 +27,9 @@ NET "ertec_spi_mosi_i" IOSTANDARD = "LVCMOS25";
NET "ertec_spi_miso_o" LOC = "AD15";
NET "ertec_spi_miso_o" IOSTANDARD = "LVCMOS25";
NET "ertec_rst_i" LOC = "AE21";
NET "ertec_rst_i" LOC = "AJ15";
NET "ertec_rst_i" IOSTANDARD = "LVCMOS25";
#NET "ertec_mosi_busy_o" LOC = "AB12";
#NET "ertec_mosi_busy_o" IOSTANDARD = "LVCMOS25";
#NET "ertec_miso_busy_o" LOC = "Y16";
#NET "ertec_miso_busy_o" IOSTANDARD = "LVCMOS25";
NET "ertec_rmq_status_o[6]" LOC = "AE13";
NET "ertec_rmq_status_o[6]" IOSTANDARD = "LVCMOS25";
......@@ -181,3 +174,6 @@ TIMESPEC "TS_exception_cdc_2"= FROM "cmp_mt_profip_translator/spi_sample_clk_i"
# Reset false path
NET "*/s_rst_n" TIG;
# MOSI FIFO false path (set this to eliminate the timing errors that may occur)
NET "*/s_mosi_rd_en" TIG;
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