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MasterFIP - Gateware
Commit 7bb81e37 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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folders cleanup

parent c66efa60
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Showing with 5 additions and 5 deletions
syn/spec_mt/spec_masterfip_mt.xise → syn/spec/spec_masterfip_mt.xise
View file @ 7bb81e37
......@@ -142,7 +142,7 @@
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_masterfip_mt|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/spec_mt/spec_masterfip_mt.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/spec/spec_masterfip_mt.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spec_masterfip_mt" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -1645,14 +1645,14 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec_mt/spec_masterfip_mt.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../../top/spec/spec_masterfip_mt.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec_mt/spec_masterfip_mt.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../top/spec/spec_masterfip_mt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="237"/>
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../../top/spec_mt/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../top/spec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......@@ -1930,7 +1930,7 @@
</files>
<bindings>
<binding xil_pn:location="/spec_masterfip_mt" xil_pn:name="../../top/spec_mt/spec_masterfip_mt.ucf"/>
<binding xil_pn:location="/spec_masterfip_mt" xil_pn:name="../../top/spec/spec_masterfip_mt.ucf"/>
</bindings>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
......
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