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MasterFIP - Gateware
Commit 86ec47a0 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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- integrated changes from evaC_dev branch 

- general clean-up
- updated and renamed wbgen2 fileset.xml
parent 3de128f4
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rtl/fmc_masterFIP_core.vhd
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--_________________________________________________________________________________________________
-- |
-- |TDC core| |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
......@@ -14,92 +14,122 @@
-- |
-- Description The masterFIP_core instantiates all the modules needed to establish WorldFIP |
-- communication. Figure 1 shows the modules of the core. |
-- There is only one clock domain in the core. |
-- |
-- _ ________________________________________________________________ |
-- | | | fmc_masterFIP_core | |
-- |W| | _________________ ____________ ____________ ______ | |
-- |O| | | | | macrocycle | | silence | | | | |
-- |R| <--| | masterfip_tx | | time cnt | | time cnt | | | | |
-- |L| | _________________| |____________| |____________| | | | |
-- |D| | _________________ ____________ ____________ | fmc | | |
-- |F| -->| | | | turnaround | | | |master| | <-processor-> |
-- |I| | | masterfip_rx | | time cnt | | resets | | FIP | | |
-- |P| | |_________________| |____________| |____________| | csr | | |
-- |_| | | | | |
-- |F| | fmc_masterFIP_core | |
-- |I| | _________________ ____________ ____________ ______ | |
-- |E| | | | | MACROCYCLE | | SILENCE | | | | |
-- |L| <--| | TX | | TIME CNT | | TIME CNT | | | | |
-- |D| | _________________| |____________| |____________| | | | |
-- |R| | _________________ ____________ ____________ | | | |
-- |I| -->| | | | TURNAROUND | | | | | | |
-- |V| | | RX | | TIME CNT | | RESETS | | | | |
-- |E| | |_________________| |____________| |____________| |WBGEN2| | <-processor-> |
-- |_| | | CSR | | |
-- | _________________ | | | |
-- sync pulse -->| | ext sync pulse | | | | |
-- sync pulse -->| | EXT SYNC PULSE | | | | |
-- | |_________________| | | | |
-- | _______ | | | |
-- LEDs <--| | aux | | | | |
-- | |_______| |______| | |
-- | ___________ | | | |
-- DS18B20 <-->| | ONEWIRE | | | | |
-- | |___________| | | | |
-- | ______ | | | |
-- LEDs <--| | LEDs | | | | |
-- | |______| |______| | |
-- |________________________________________________________________| |
-- Figure 1 |
-- Figure 1: fmc_masterFIP_core architecture |
-- |
-- The fmc_masterfip_csr module establishes the interface with the processor, usually|
-- a Mock Turtle core. The module has been generated through the wbgen2 application. |
-- Please consult the fmc_masterfip_csr.htm for the registers map. |
-- MrFIP WBGEN2 CSR: |
-- The mrfip_wbgen2_csr module has been generated through the wbgen2 application. |
-- It establishes the interface with the processor, usually a Mock Turtle core. |
-- This interface contains a set of control and status registers for each one of the |
-- units of Figure 1; it also contains the WorldFIP frame PAYLOAD data for the TX |
-- and RX. Regarding the PAYLOAD data, it was decided not to use a FIFO for passing |
-- the WorldFIP PAYLOAD data from the processor to this core for serialization or for|
-- passing the WorldFIP PAYLOAD data that have been deserialized from this core to |
-- the processor. Instead a set of 67 registers (= 268 bytes, which is the max |
-- WorldFIP frame size) is used is used for each of the TX and RX; like this the |
-- time for which the data need to remain static to be read is minimized, leading to |
-- a simpler design. |
-- |
-- MASTERFIP TX: |
-- The masterfip_tx is placing a complete WorldFIP frame on the bus. |
-- The masterfip_tx is ignorant of the frame type (ID_DAT/RT_DAT/RP_MSG etc..) or the|
-- macrocycle sequence, as well as of timing issues (it does not for example measure |
-- internally the turnaround time after the delivery of an ID_DAT); the processor |
-- (Mock Turtle for example) is responsible for managing all these issues and |
-- for providing to the masterfip_tx (through the fmc_masterfip_csr) the data to |
-- serialise and a start pulse. The communication between the processor (MT) and the |
-- masterfip_tx is through a set of control (from the MT) and status (from the |
-- masterfip_tx) registers. Upon a rising edge on the tx_start control pulse, the |
-- masterfip_tx is copying all the data registers (tx_data_ctrl, |
-- tx_data_reg1..tx_data_reg66) and then it initiates a WorldFIP frame, starting with|
-- the FSS, the tx_data_ctrl and then the number of data bytes indicated by the |
-- tx_bytes_num register; it finally adds the CRC and FES and signals the processor |
-- through the status bit tx_stop. |
-- The masterfip_tx is ignorant of the frame type (ID_DAT/RT_DAT/RP_MSG etc..), |
-- of the macrocycle sequence and macrocycle timing; the processor (Mock Turtle for |
-- example) is responsible for managing all these issues and for providing to the |
-- masterfip_tx the bytes to serialise along with a start pulse. |
-- The communication between the processor (MT) and the masterfip_tx is through a set|
-- of control (from the MT) and status (from the masterfip_tx) signals/registers |
-- defined in the masterfip_wbgen2_csr module. |
-- Upon a rising edge on the tx_ctrl_start pulse, the masterfip_tx: |
-- - copies all the payload registers (tx_payld_ctrl, tx_payld_reg1..tx_payld_reg67)|
-- and the register that indicates the number of payload bytes to |
-- serialize (tx_ctrl_bytes_num) |
-- - starts serializing a WorldFIP frame (see following figure). Note that the FSS, |
-- CRC and FES fields are generated internally in the masterfip_tx unit. |
-- - after the FES, rises the tx_stat_stop status bit to signal the MT for the end |
-- of a successful frame transmission. |
-- ______________________________________________________________________________ |
-- |_____FSS_____|__Ctrl__|_____________tx_data______________|_____CRC____|__FES__| |
-- |_____FSS_____|__Ctrl__|_____________tx_payld_____________|_____CRC____|__FES__| |
-- |
-- <-- 2 byes --><-1byte-><--------- tx_bytes_num --------><-- 2 byes --><-1byte-> |
-- <---2 bytes--><-1byte-><------ tx_ctrl_bytes_num -------><--2 bytes--><-1byte-> |
-- |
-- Figure 2: WorldFIP tx frame structure |
-- |
-- MASTERFIP RX: |
-- The masterfip_rx is retrieving a WorldFIP frame from the bus. |
-- Similar to the masterfip_tx, the masterfip_rx has no intelligence regarding the |
-- macrocycle sequence; it is controlled and monitored by the processor through the |
-- fmc_masterfip_csr and a set of control and status registers. |
-- As long as it is not under reset, the masterfip_rx is looking at the WorldFIP bus |
-- macrocycle sequence; it is controlled and monitored by the processor (MT) through |
-- the masterfip_wbgen2_csr, where a set of control and status registers are defined.|
-- As long as it is not under reset, the masterfip_rx is probing the WorldFIP bus |
-- trying to identify the FSS sequence of a WorldFIP frame. Upon the FSS detection |
-- it signals the processor (MT) through the status bit fss_received and continues |
-- with following the rest of the frame. It stores the first byte after the FSS to |
-- the rx_data_ctrl register and the rest of the bytes to the registers |
-- rx_data_reg1..rx_data_reg66. Upon the detection of a FES the masterfip_rx is |
-- checking the CRC of the frame and enables the status bit rx_frame_ok or |
-- rx_frame_error accordingly. Upon the rx_frame_ok, the status register |
-- rx_bytes_num indicates the number of bytes that were in the frame (this indicates |
-- the number of rx_data_regs and the number of bytes inside the last rx_data_reg to |
-- be retrieved by the processor). |
-- it signals the processor through the status bit rx_stat_pream_ok and continues |
-- following the rest of the frame. It stores the first byte after the FSS to the |
-- rx_payld_ctrl register and the rest of the bytes to the registers |
-- rx_payld_reg1..rx_payld_reg67. Upon the detection of a FES the masterfip_rx |
-- checks the CRC of the frame and enables the status bit rx_stat_frame_ok or |
-- rx_stat_crc_err accordingly. Upon the rx_stat_frame_ok, the status register |
-- rx_stat_bytes_num indicates the number of bytes in the frame (this indicates |
-- the number of rx_payld_regs and the number of bytes inside the last rx_payld_reg |
-- to be retrieved by the processor). |
-- The processor should copy the rx_payld_regs upon a rx_stat_frame_ok; the regs |
-- keep their values until an rx_rst or until the detection of a new rx_stat_frame_ok|
-- this in the worst case of the fastest bit rate 2.5 Mbps with a received frame |
-- being followed by the shortest RP_FIN is: |
-- (Min Turnaround time of a node = 4 us) + (RP_FIN duration = 19.2 us) = 23.2 us |
-- ______________________________________________________________________________ |
-- |_____FSS_____|__Ctrl__|_____________rx_data______________|_____CRC____|__FES__| |
-- |_____FSS_____|__Ctrl__|_____________rx_payld_____________|_____CRC____|__FES__| |
-- |
-- <---2 bytes--><-1byte-><------ rx_ctrl_bytes_num -------><--2 bytes--><-1byte-> |
-- |
-- <-- 2 byes --><-1byte-><--------- rx_bytes_num --------><-- 2 byes --><-1byte-> |
-- Figure 2: WorldFIP rx frame structure |
-- |
-- The modules regarding the ext_sync_pulse are counting the number of rising-edge |
-- pulses that are arriving to the ext_sync input of the board and provide the result|
-- to the dedicated fmc_masterfip_csr register to be accessed by the processor (MT). |
-- EXT SYNC PULSE: |
-- The modules regarding the ext_sync_pulse are synchronising, deglitching and |
-- counting the number of rising-edge pulses that are arriving to the ext_sync input |
-- of the board and provide the result to the dedicated masterfip_wbgen2_csr register|
-- |
-- MACROCYCLE: |
-- The modules regarding the macrocycle are counting the time of a macrocycle using |
-- the 10ns input clock as well as the number of macrocycles since the |
-- startup/a reset. Dedicated registers in the fmc_masterfip_csr provide the counters|
-- values to the processor. |
-- the 10 ns input clock as well as the number of macrocycles since startup/a reset. |
-- Dedicated registers in the masterfip_wbgen2_csr provide the counters values |
-- to the processor (MT). Note that the macrocycle length comes from the processor |
-- through a dedicated register in the masterfip_wbgen2_csr and should be set once |
-- in the application startup. |
-- |
-- TURNAROUND, SILENCE TIMES: |
-- The modules regarding the turnaround and silence time are counting the respective |
-- time using the 10ns clock. Dedicated registers in the fmc_masterfip_csr provide |
-- the counters values to the processor. |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 07/2014 |
-- Version v1 |
-- Depends on |
-- time using the 10 ns clock. Dedicated regs in the masterfip_wbgen2_csr provide |
-- the counters values to the processor (MT). As in the case of the macrocycle length|
-- the turnaround and silence time length is provided through dedicated registers in |
-- the masterfip_wbgen2_csr that should be set once in the application startup. |
-- |
---------------- |
-- Last changes |
-- 07/2014 v1 EG First version |
-- ONEWIRE: |
-- The DS18B20 module is for the 1-wire reading of the unique ID and temperature on |
-- the mezzanine. Different than in other designs that implement sw-bit-banging, |
-- here the communication is hard-coded in vhdl, so as to simplify the drivers. |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -122,8 +152,8 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.mrfip_wbgen2_pkg.all;
use work.masterFIP_pkg.all;
use work.masterfip_wbgen2_pkg.all;
use work.masterfip_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
......@@ -141,46 +171,33 @@ entity fmc_masterFIP_core is
values_for_simul : boolean := FALSE); -- set to TRUE when instantiated in a test-bench
port
(-- Clock and reset
clk_i : in std_logic; -- only one clk domain
rst_i : in std_logic; -- PoR or PCIe reset, synched with the clk_i
clk_i : in std_logic; -- only one clk domain
rst_n_i : in std_logic; -- PCIe reset, synched with the clk_i
-- Bus Speed -- 31.25 Kbps: speed_b1 = 0, speed_b0 = 0
speed_b0_i : in std_logic; -- 1 Mbps : speed_b1 = 0, speed_b0 = 1
speed_b1_i : in std_logic; -- 2.5 Mbps : speed_b1 = 1, speed_b0 = 0
speed_b0_i : in std_logic; -- 1 Mbps : speed_b1 = 0, speed_b0 = 1
speed_b1_i : in std_logic; -- 2.5 Mbps : speed_b1 = 1, speed_b0 = 0
-- 5 Mbps : speed_b1 = 1, speed_b0 = 1
-- One wire DS18B20U+ on the mezzanine
onewire_b : inout std_logic; -- mezzanine 1-wire
onewire_b : inout std_logic; -- temper and unique id
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enable 50 Ohms termination of the pulse
ext_sync_term_en_o : out std_logic; -- enables the 50 Ohms termination of the pulse
ext_sync_dir_o : out std_logic; -- transceiver direction
ext_sync_oe_n_o : out std_logic; -- transceiver output enable negative
ext_sync_tst_n_o : out std_logic; -- emulation of the LEMO input
ext_sync_i : in std_logic; -- sync pulse
-- Power supplies for the ADC
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
adc_prim_conn_n_o : out std_logic;
adc_sec_conn_n_o : out std_logic;
-- DAC configuration (to set OSC1 to its middle range where the stability is max)
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
-- WISHBONE classic bus interface
ext_sync_a_i : in std_logic; -- sync pulse
-- FielDrive interface
fd_rstn_o : out std_logic; -- reset
fd_rxcdn_a_i : in std_logic; -- rx carrier detect
fd_rxd_a_i : in std_logic; -- rx data
fd_wdgn_a_i : in std_logic; -- tx watchdog
fd_txer_a_i : in std_logic; -- tx error
fd_txck_o : out std_logic; -- tx clk
fd_txd_o : out std_logic; -- tx data
fd_txena_o : out std_logic; -- tx enable
-- WISHBONE classic bus interface with the processor (MT)
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
......@@ -191,8 +208,8 @@ entity fmc_masterFIP_core is
wb_ack_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0);
-- Aux, 8 debugging signals to pass to the higher levels
aux_o : out std_logic_vector(7 downto 0));
-- LEDs and debugging signals to pass to the higher levels
leds_o : out std_logic_vector(g_width-1 downto 0));
end fmc_masterFIP_core;
......@@ -202,51 +219,50 @@ entity fmc_masterFIP_core is
architecture rtl of fmc_masterFIP_core is
-- wbgen2 regs from/to mock turtle
signal reg_to_mt : t_mrfip_in_registers;
signal reg_from_mt : t_mrfip_out_registers;
signal reg_to_mt : t_masterfip_in_registers;
signal reg_from_mt : t_masterfip_out_registers;
-- resets
signal rst_n, core_rst, core_rst_n : std_logic;
signal fd_host_rst : std_logic;
signal rst_n, core_rst, core_rst_n : std_logic;
signal fd_host_rst : std_logic;
signal extend : std_logic_vector(c_PERIODS_COUNTER_LGTH-1 downto 0);
-- config
signal speed : std_logic_vector(1 downto 0);
signal speed : std_logic_vector(1 downto 0);
-- ext pulse
signal ext_sync_p, ext_sync_oe : std_logic;
signal ext_sync_p_cnt_rst, ext_sync_p_cnt_host_rst : std_logic;
signal ext_sync_p_cnt : std_logic_vector(31 downto 0);
signal ext_sync_p, ext_sync_oe : std_logic;
signal ext_sync_p_cnt_rst : std_logic;
signal ext_sync_p_cnt : std_logic_vector(g_width-1 downto 0);
-- counters
signal macrocyc_load_p, turnar_load_p, silen_load_p : std_logic;
signal num_of_macrocyc_cnt : std_logic_vector(31 downto 0);
signal num_of_macrocyc_cnt_full, num_of_macrocyc_cnt_reinit : std_logic;
signal macrocyc_cnt : std_logic_vector(30 downto 0);
signal macrocyc_cnt_zero_p : std_logic;
signal macrocyc_load_p, turnar_load_p : std_logic;
signal num_of_macrocyc_cnt_full : std_logic;
signal num_of_macrocyc_cnt : std_logic_vector(g_width-1 downto 0);
signal num_of_macrocyc_cnt_reinit : std_logic;
signal macrocyc_cnt : std_logic_vector(g_width-2 downto 0);
signal macrocyc_cnt_zero_p, silen_load_p : std_logic;
-- tx
signal tx_completed_p, tx_completed : std_logic;
signal tx_rst, fd_txd, fd_txck : std_logic;
signal tx_frame : tx_frame_t;
signal tx_completed_p, tx_completed : std_logic;
signal tx_rst, fd_txd, fd_txck : std_logic;
signal tx_frame : tx_frame_t;
-- rx
signal rx_rst : std_logic;
signal rx_fss_received_p, rx_fss_received : std_logic;
signal rx_frame_ok_p, rx_frame_ok, rx_crc_wrong_p : std_logic;
signal rx_crc_wrong, rx_byte_ready_p, fd_txena : std_logic;
signal rx_frame : rx_frame_t;
signal rx_byte : std_logic_vector(7 downto 0);
signal rx_byte_index : std_logic_vector(15 downto 0);
signal rx_rst : std_logic;
signal rx_fss_received_p, rx_fss_received : std_logic;
signal rx_frame_ok_p, rx_frame_ok : std_logic;
signal rx_crc_wrong, rx_byte_ready_p : std_logic;
signal rx_crc_wrong_p, fd_txena : std_logic;
signal rx_frame : rx_frame_t;
signal rx_byte : std_logic_vector(C_BYTE_WIDTH-1 downto 0);
signal rx_byte_index : std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
-- fd_wdgn, fd_txer, fd_rxcdn
signal fd_wdg_tstamp, fd_txer_tstamp : std_logic_vector(30 downto 0);
signal fd_wdg_sync, fd_wdg, fd_rxcd, fd_rxcdn_sync : std_logic;
signal fd_txer, fd_txer_p, fd_txer_cnt_reinit : std_logic;
signal fd_wdg_tstamp, fd_txer_tstamp : std_logic_vector(30 downto 0);
signal fd_wdgn, fd_wdg, fd_wdg_p, fd_rxcd : std_logic;
signal fd_rxcdn, fd_txer_cnt_reinit : std_logic;
signal fd_txer, fd_txer_filt, fd_txer_p : std_logic;
-- one wire
signal tmp_temper : std_logic_vector(15 downto 0);
signal tmp_id : std_logic_vector(63 downto 0);
signal onewire_read_p, pps_is_zero, pps_load_p : std_logic;
signal tmp_temper : std_logic_vector(15 downto 0);
signal tmp_id : std_logic_vector(63 downto 0);
signal onewire_read_p, pps_is_zero : std_logic;
signal pps_load_p : std_logic;
-- ext_sync
signal ext_sync, ext_sync_filt : std_logic;
-- LEDs
signal sync_led, out_of_sync_led : std_logic;
-- debug
signal mf_dbg : std_logic_vector(31 downto 0);
signal mf_dbg_p, mf_dbg_p_ext, macrocyc_cnt_zero, macrocyc_cnt_twentyfive, macrocyc_cnt_twentyfive_p : std_logic;
signal ext_sync, ext_sync_filt : std_logic;
-- chipscope
-- component chipscope_ila
......@@ -274,100 +290,90 @@ architecture rtl of fmc_masterFIP_core is
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- WBGEN2 REGS FROM/TO MOCK TURTLE --
---------------------------------------------------------------------------------------------------
cmp_masterfip_csr: fmc_masterfip_csr
port map
(rst_n_i => rst_n,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i(9 downto 2),
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => wb_stall_o,
regs_i => reg_to_mt,
regs_o => reg_from_mt);
---------------------------------------------------------------------------------------------------
-- ADC SUPPLIES & RELAYS --
---------------------------------------------------------------------------------------------------
adc_1v8_shdn_n_o <= reg_from_mt.adc_1v8_shdn_n_o;
adc_m5v_shdn_n_o <= reg_from_mt.adc_m5v_shdn_n_o;
adc_5v_en_n_o <= reg_from_mt.adc_5v_en_n_o;
adc_sec_conn_n_o <= '0' when reg_from_mt.adc_sec_conn_n_o = '0' else 'Z';
adc_prim_conn_n_o <= '0' when reg_from_mt.adc_prim_conn_n_o = '0' else 'Z';
---------------------------------------------------------------------------------------------------
-- speed --
-- speed --
---------------------------------------------------------------------------------------------------
speed <= speed_b1_i & speed_b0_i;
reg_to_mt.speed_i <= speed;
---------------------------------------------------------------------------------------------------
-- resets --
-- RESETS --
---------------------------------------------------------------------------------------------------
rst_n <= not rst_i; -- PoR or PCIe reset
core_rst <= reg_from_mt.rst_core_o or rst_i; -- PoR or PCIe reset or reset from WRNC
core_rst <= reg_from_mt.rst_core_o or (not rst_n_i); -- reset from MT OR PCIe reset
core_rst_n <= not core_rst;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FIELDRIVE reset generation of length: 2 WorldFIP-clk-cycles of the lowest speed 31.25Kbps
cmp_fd_rst_generate: gc_extend_pulse
generic map (g_width => 6400)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FIELDRIVE rst: generation of a pulse 1 x WorldFIP-clk-cycles long
cmp_fd_rst_generate: gc_dyn_extend_pulse
generic map(g_len_width => c_PERIODS_COUNTER_LGTH)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => reg_from_mt.rst_fd_o, -- monostable: 1-clk-tick-long pulse
len_i => extend,
extended_o => fd_host_rst);
-- -- -- -- -- -- -- -- -- -- --
fd_rstn_o <= not fd_host_rst;
extend <= std_logic_vector(c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(speed))));
---------------------------------------------------------------------------------------------------
-- external sync --
-- WBGEN2 REGS FROM/TO MOCK TURTLE --
---------------------------------------------------------------------------------------------------
cmp_masterfip_csr: masterfip_wbgen2_csr
port map
(rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i(9 downto 2),
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => wb_stall_o,
regs_i => reg_to_mt,
regs_o => reg_from_mt);
ext_sync_tst_n_o <= '0' when reg_from_mt.ext_sync_tst_n_o = '0' else 'Z';
ext_sync_dir_o <= reg_from_mt.ext_sync_dir_o;
ext_sync_term_en_o <= reg_from_mt.ext_sync_term_en_o;
ext_sync_oe_n_o <= reg_from_mt.ext_sync_oe_n_o;
-- input synchronizer of the ext_sync_i signal
---------------------------------------------------------------------------------------------------
-- EXT SYNC PULSE --
---------------------------------------------------------------------------------------------------
ext_sync_dir_o <= reg_from_mt.ext_sync_ctrl_dir_o;
ext_sync_oe_n_o <= reg_from_mt.ext_sync_ctrl_oe_n_o;
ext_sync_term_en_o <= reg_from_mt.ext_sync_ctrl_term_en_o;
-- input synchronizer of the ext_sync_a_i signal
cmp_ext_sync_sync: gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => ext_sync_i,
data_i => ext_sync_a_i,
synced_o => ext_sync);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- deglitch filter
cmp_ext_sync_glitch_filt: gc_glitch_filt
generic map(g_len => 10) -- glitches up to 100ns are ignored;
port map -- Note that the filter adds a 100ns delay to the ext_sync signal
cmp_ext_sync_deglitch: gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
port map -- Note that the filter adds a 100 ns delay to the ext_sync signal
(clk_i => clk_i,
rst_n_i => core_rst_n,
dat_i => ext_sync,
dat_o => ext_sync_filt);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- rising edge detection on the deglitched signal
cmp_ext_sync_p_detect: gc_sync_ffs
cmp_ext_sync_deglitch_p_detect: gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => ext_sync_filt,
ppulse_o => ext_sync_p);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter of the number of rising edges
cmp_ext_sync_p_cnt:incr_counter
generic map(g_counter_lgth => 32)
......@@ -377,25 +383,27 @@ begin
counter_reinit_i => ext_sync_p_cnt_rst,
counter_o => reg_to_mt.ext_sync_p_cnt_i);
-- -- -- -- -- -- -- -- -- -- --
ext_sync_p_cnt_rst <= ext_sync_p_cnt_host_rst or core_rst;
ext_sync_p_cnt_rst <= reg_from_mt.ext_sync_ctrl_p_cnt_rst_o or core_rst;
---------------------------------------------------------------------------------------------------
-- macrocycle counter --
-- MACROCYCLE COUNTER --
---------------------------------------------------------------------------------------------------
-- Regarding synchronisation, the masterFIP application can work in two modes:
-- using an internal counter that counts each macrocycle based on the local oscillator, or
-- using the ext_sync_i pulse to signal the beginning of each macrocycle. There is also the option
-- using the ext_sync pulse to signal the beginning of each macrocycle. There is also the option
-- that when the external pulse does not arrive, the internal counter takes over the synchronisation.
-- In an application where the external synchronization pulse is expected for every macrocycle,
-- the macrocyc_lgth is set by the sw application slightly larger than the external synchronization
-- period; therefore the macrocycle counter should not be reaching zero; if it reaches zero,
-- it would mean that the external synchronization pulse did not arrive in time and a new macrocycle,
-- (slightly longer) will start automatically based on this internal counter.
-- it would mean that the external synchronization pulse did not arrive in time and a new
-- macrocycle (slightly longer) will start automatically based on this internal counter.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the macrocycle time;
-- the macrocycle length (counter top) should be set once upon the application startup
cmp_macrocycle_time_cnt: decr_counter
generic map(width => 31)
generic map(width => g_width-1)
port map
(clk_i => clk_i,
rst_i => core_rst,
......@@ -407,15 +415,15 @@ begin
reg_to_mt.macrocyc_time_cnt_i <= macrocyc_cnt;
macrocyc_load_p <= macrocyc_cnt_zero_p or reg_from_mt.macrocyc_start_o or ext_sync_p;
-- note: macrocyc_start_o is a monostable, 1-clk-tick-long pulse
-- note: macrocyc_start_o is a monostable, 1-clk-tick-long pulse
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the number of macrocycles;
-- being a 32-bit counter, for the fastest application of 20ms macrocycle, the counter can
-- being a 32-bit counter, for the fastest application of 20 ms macrocycle, the counter can
-- keep counting for 994 days; when it fills up it would restart from 0.
cmp_macrocycles_cnt:incr_counter
generic map(g_counter_lgth => 32)
generic map(g_counter_lgth => g_width)
port map
(clk_i => clk_i,
counter_incr_i => macrocyc_cnt_zero_p,
......@@ -427,12 +435,12 @@ begin
---------------------------------------------------------------------------------------------------
-- turnaround counter --
-- TURNAROUND COUNTER --
---------------------------------------------------------------------------------------------------
-- counter counting the turnaround time i.e. the time after the end of transmission of a frame
-- (tx_completed_p), or after the end of reception of a frame (rx_frame_ok_p/ rx_crc_wrong_p)
-- and before the transmission of a new frame.
-- Note that the Mock Turtle is using the turnar_cnt rather than the 1-clk-tick long counter_is_zero
-- Note that the MT is using the turnar_cnt rather than the 1-clk-tick long counter_is_zero pulse
-- turnaround counter
cmp_turnaround_cnt: decr_counter
......@@ -446,12 +454,12 @@ begin
counter_is_zero_o => open);
-- -- -- -- -- -- -- -- -- -- --
turnar_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or reg_from_mt.turnar_start_o;
-- note: turnar_start_o is a monostable, 1-clk-tick-long pulse
-- note: turnar_start_o is a monostable, 1-clk-tick-long pulse
--------------------------------------------------------------------------------------------------
-- silence counter --
--------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- SILENCE COUNTER --
---------------------------------------------------------------------------------------------------
-- counter counting the silence time i.e. the maximum amount of time that the masterFIP waits for
-- a response frame; the counting starts after the transmission of a frame sent by the master
-- (tx_completed_p) or after the reception of a frame (rx_frame_ok_p/ rx_crc_wrong_p) for the
......@@ -468,39 +476,62 @@ begin
counter_is_zero_o => open);
-- -- -- -- -- -- -- -- -- -- --
silen_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or reg_from_mt.silen_start_o;
-- note: turnar_start_o is a monostable, 1-clk-tick-long pulse
-- note: turnar_start_o is a monostable, 1-clk-tick-long pulse
--------------------------------------------------------------------------------------------------
-- signals for rx --
--------------------------------------------------------------------------------------------------
-- The receiver rx is disabled when a frame is being transmitted (fd_txena active).
---------------------------------------------------------------------------------------------------
-- MASTERFIP RX --
---------------------------------------------------------------------------------------------------
-- Note that the deglitching of the fd_rxd_a_i takes place inside the masterfip_rx unit.
cmp_masterfip_rx: masterfip_rx
port map
(clk_i => clk_i,
rst_i => core_rst,
rx_rst_i => rx_rst, -- reset from the MT or reset while transmitting
speed_i => speed,
rx_d_a_i => fd_rxd_a_i,
rx_byte_index_o => rx_byte_index, -- current byte index
rx_word_index_o => reg_to_mt.rx_stat_curr_word_indx_i,
rx_ctrl_byte_o => reg_to_mt.rx_payld_ctrl_i,
rx_frame_o => rx_frame,
rx_fss_crc_fes_ok_p_o => rx_frame_ok_p,
rx_fss_received_p_o => rx_fss_received_p,
rx_crc_wrong_p_o => rx_crc_wrong_p,
rx_byte_o => rx_byte, -- for debugging
rx_byte_ready_p_o => rx_byte_ready_p);-- for debugging
---------------------------------------------------------------------------------------------------
-- Signals for the RX --
---------------------------------------------------------------------------------------------------
-- The receiver RX is disabled when a frame is being transmitted (fd_txena active).
-- Note that the reg_from_mt.rx_ctrl_rst_o is a monostable, 1-clk-tick-long pulse
rx_rst <= reg_from_mt.rx_ctrl_rst_o or fd_txena;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- registering the number of received bytes upon rx_frame_ok_p
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- registering the number of received bytes upon rx_frame_ok_p; the final number does not include
-- FSS, CTRL, CRC and FES bytes.
p_rx_bytes_num : process(clk_i)
begin
if rising_edge(clk_i) then
if (core_rst_n = '0' or rx_rst = '1') then
if (core_rst = '1' or rx_rst = '1') then
reg_to_mt.rx_stat_bytes_num_i <= (others => '0');
reg_to_mt.rx_stat_frame_ok_i <= '0';
else
if rx_frame_ok_p = '1' then
reg_to_mt.rx_stat_frame_ok_i <= rx_frame_ok_p;
reg_to_mt.rx_stat_bytes_num_i <= rx_byte_index - 3; -- data payload, without FSS, CTRL, CRC, FES
end if;
reg_to_mt.rx_stat_bytes_num_i <= rx_byte_index - 3; -- data payload, without FSS, CTRL,
end if; -- CRC, FES
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- extending the rx_fss_received_p until a core_rst or rx_rst is received
p_rx_fss_received_extend : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst_n = '0' or rx_rst = '1') then
if(core_rst = '1' or rx_rst = '1') then
reg_to_mt.rx_stat_pream_ok_i <= '0';
else
if rx_fss_received_p = '1' then
......@@ -510,12 +541,12 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- extending the rx_crc_wrong_p until a core_rst or rx_rst is received
p_rx_crc_wrong_extend : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst_n = '0' or rx_rst = '1') then
if(core_rst = '1' or rx_rst = '1') then
reg_to_mt.rx_stat_frame_crc_err_i <= '0';
else
if rx_crc_wrong_p = '1' then
......@@ -525,7 +556,7 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter of frames with crc errors since the startup or a core reset (not on every macrocycle)
cmp_rx_crc_err_cnt:incr_counter
generic map(g_counter_lgth => 32)
......@@ -537,30 +568,7 @@ begin
---------------------------------------------------------------------------------------------------
-- rx --
---------------------------------------------------------------------------------------------------
cmp_masterfip_rx: masterfip_rx
port map
(clk_i => clk_i,
rst_i => core_rst,
speed_i => speed,
fd_rxd_a_i => fd_rxd_i,
rx_rst_i => rx_rst, -- reset from the WRNC or reset while transmitting
-------------------------------------------------------------
rx_byte_index_o => rx_byte_index, -- not currently used
rx_word_index_o => reg_to_mt.rx_stat_curr_word_indx_i,
rx_ctrl_byte_o => reg_to_mt.rx_payld_ctrl_i,
rx_frame_o => rx_frame,
rx_byte_o => rx_byte,
rx_byte_ready_p_o => rx_byte_ready_p,
rx_fss_crc_fes_ok_p_o => rx_frame_ok_p,
rx_fss_received_p_o => rx_fss_received_p,
rx_crc_wrong_p_o => rx_crc_wrong_p);
-------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- tx --
-- MASTERFIP TX --
---------------------------------------------------------------------------------------------------
cmp_masterfip_tx: masterfip_tx
......@@ -568,52 +576,38 @@ begin
(clk_i => clk_i,
rst_i => tx_rst,
speed_i => speed,
tx_bytes_num_i => reg_from_mt.tx_ctrl_bytes_num_o, -- number of bytes to serialize; sampled upon tx_start_p
tx_start_p_i => reg_from_mt.tx_ctrl_start_o, -- monostable, 1-clk-tick-long pulse
tx_bytes_num_i => reg_from_mt.tx_ctrl_bytes_num_o,-- num of bytes to serialize; sampled upon tx_start_p
tx_start_p_i => reg_from_mt.tx_ctrl_start_o, -- monostable, 1-clk-tick-long pulse
tx_frame_i => tx_frame,
tx_ctrl_byte_i => reg_from_mt.tx_payld_ctrl_o,
-------------------------------------------------------------
tx_byte_index_o => reg_to_mt.tx_stat_curr_byte_indx_i, -- index of current byte being serialized -- up to 263 bytes
tx_byte_index_o => reg_to_mt.tx_stat_curr_byte_indx_i,-- indx of current byte being serialized,
-- counting starts from 0 (indx 0 is
-- the Control byte) up to 262 bytes
tx_end_p_o => tx_completed_p,
tx_data_o => fd_txd,
tx_enable_o => fd_txena,
tx_d_o => fd_txd,
tx_ena_o => fd_txena,
tx_clk_o => fd_txck);
-------------------------------------------------------------
tx_rst <= core_rst or reg_from_mt.tx_ctrl_rst_o;
-- fd_txena_o <= fd_txena;
tx_rst <= core_rst or reg_from_mt.tx_ctrl_rst_o; -- reg_from_mt.tx_ctrl_rst_o is a monostable
fd_txena_o <= fd_txena;
fd_txd_o <= fd_txd;
fd_txck_o <= fd_txck;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- delay for 1 cycle the fd_txena
fd_txena_delay : process(clk_i)
begin
if rising_edge(clk_i) then
if(tx_rst = '1') then
fd_txena_o <= '0';
else
fd_txena_o <= fd_txena;
end if;
end if;
end process;
reg_to_mt.tx_stat_ena_i <= fd_txena;
--------------------------------------------------------------------------------------------------
-- signals for tx --
--------------------------------------------------------------------------------------------------
-- extending the tx_completed_p until a core_rst or rx_rst is received
-- note: reg_from_mt.tx_ctrl_rst_o and reg_from_mt.tx_ctrl_start_o are monostables,
-- 1-clk-tick-long pulses
---------------------------------------------------------------------------------------------------
-- Signals for the TX --
---------------------------------------------------------------------------------------------------
-- extending the tx_completed_p until a tx_rst or
-- a new request for serialization (reg_from_mt.tx_ctrl_start_o) is received
p_tx_completed_extend : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst_n = '0' or reg_from_mt.tx_ctrl_rst_o = '1' or reg_from_mt.tx_ctrl_start_o = '1') then
if(tx_rst = '1' or reg_from_mt.tx_ctrl_start_o = '1') then
reg_to_mt.tx_stat_stop_i <= '0';
else
if tx_completed_p = '1' then
reg_to_mt.tx_stat_stop_i <= '1'; -- stays active until a tx_rst or core_rst or tx_start_p
reg_to_mt.tx_stat_stop_i <= '1'; -- stays active until a tx_rst or tx_start_p
end if;
end if;
end if;
......@@ -621,71 +615,135 @@ begin
---------------------------------------------------------------------------------------------------
-- FielDrive TXERR, WDGN, CDN --
-- FielDrive TXER, WDGN, CDN --
---------------------------------------------------------------------------------------------------
-- The following modules provide to the MT information about the status signals coming from the
-- FielDrive: WDGN, CDN, TXER.
---------------------------------------------------------------------------------------------------
-- The fd_wdgn_i is activated when the FielDrive detects TXD activity > 1024 bytes long;
-- it is deactivated with a FielDrive reset.
-- The following processes provide to the MT the macrocycle number when the fd_wdgn_i was activated.
-- WDGN: is activated when the FielDrive detects activity > 1024 bytes long;
-- it is kept active until FielDrive's reinitialization with a fd_rstn_o.
-- Note that it is the logic running on the MT that is responsible for activating a fd_rst_o upon
-- the detection of a fd_wdgn_i.
-- synch of the incoming fd_wdgn_i signal
-- the activation of a fd_wdgn.
-- The following processes provide to the MT the filtered fd_wdgn and the macrocycle number when it
-- was activated.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- input synchronizer of the fd_wdgn_a_i signal
cmp_fd_wdgn_sync: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map
(clk_i => clk_i,
rst_n_i => rst_n,
data_i => fd_wdg,
synced_o => fd_wdg_sync);
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => fd_wdgn_a_i,
synced_o => fd_wdgn);
fd_wdg <= not fd_wdgn;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- deglitch filter
cmp_fd_wdg_deglitch: gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
-- Note that the filter adds a 100 ns delay to the ext_sync signal
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
dat_i => fd_wdg,
dat_o => reg_to_mt.fd_wdg_i);
fd_wdg <= not fd_wdgn_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- edge detection
cmp_fd_wdgn_deglitch_p_detect: gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => reg_to_mt.fd_wdg_i,
ppulse_o => fd_wdg_p);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- process that registers at the same time the activation of fd_wdgn_i and the macrocycle_cnt
-- upon the activation; the signals are reset upon a core_rst_n or a fd_host_rstn
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- process that registers the moment within the macrocycle (macrocycle_cnt) when the
-- fd_wdgn_p appeared
p_fd_wdgn_capture : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst = '1' or fd_host_rst = '1') then
reg_to_mt.fd_wdg_i <= '0';
if(core_rst = '1' or fd_host_rst = '1') then -- resets upon core reset or FielDrive reset
reg_to_mt.fd_wdg_tstamp_i <= (others => '0');
else
if fd_wdg_sync = '1' then
reg_to_mt.fd_wdg_i <= '1';
if fd_wdg_p = '1' then
reg_to_mt.fd_wdg_tstamp_i <= '0' & macrocyc_cnt;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- synch of the incoming fd_rxcdn_i signal
---------------------------------------------------------------------------------------------------
-- CDN: synch and filtering of the incoming fd_rxcdn_a_i signal.
-- On the processor (MT) side there should be the verification that before a tx_ctrl_start the CDN
-- is inactive.
-- input synchronizer of the fd_rxcdn_a_i signal
cmp_fd_rxcdn_sync: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map
(clk_i => clk_i,
rst_n_i => rst_n,
data_i => fd_rxcd,
synced_o => fd_rxcdn_sync);
fd_rxcd <= not fd_rxcdn_i;
reg_to_mt.fd_cd_i <= fd_rxcdn_sync;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The fd_txerr_i is activated when the FielDrive detects an overload/underload; for example if
-- edge detection on the fd_txer_i signal
cmp_fd_txer_i_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
rst_n_i => core_rst_n,
data_i => fd_rxcdn_a_i,
synced_o => fd_rxcdn);
fd_rxcd <= not fd_rxcdn;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- deglitch filter
cmp_fd_rxcd_deglitch: gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
-- Note that the filter adds a 100 ns delay to the ext_sync signal
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
dat_i => fd_rxcd,
dat_o => reg_to_mt.fd_cd_i);
---------------------------------------------------------------------------------------------------
-- TXER: is activated upon a bus overload/ underload detected by the FielDrive driver outputs;
-- like for example when the WorldFIP cable has been disconnected.
-- It is also activated when during transmission there has been no Manchester-edge detected after
-- the duration of 4 bits.
-- Note that the signal does not need a FielDrive reset to go back to inactive.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- input synchronizer of the fd_txer_a_i signal
cmp_fd_txer_sync: gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => fd_txer_a_i,
synced_o => fd_txer);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- deglitch filter
cmp_fd_txer_deglitch: gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
-- Note that the filter adds a 100 ns delay to the ext_sync signal
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
dat_i => fd_txer,
dat_o => fd_txer_filt);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- edge detection on the fd_txer_filt signal
cmp_fd_txer_deglitch_p_detect: gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => rst_n,
data_i => fd_txer_i,
rst_n_i => core_rst_n,
data_i => fd_txer_filt,
ppulse_o => fd_txer_p);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter counting the number of fd_txerr_p
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the number of fd_txer_p
cmp_fd_txer_cnt:incr_counter
generic map(g_counter_lgth => 32)
port map
......@@ -698,17 +756,16 @@ begin
fd_txer_cnt_reinit <= '1' when core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rst = '1'
else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- process that registers the macrocycle_cnt value upon the last fd_txer_p of a macrocycle
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- process that registers the moment within the !current! macrocycle (macrocycle_cnt value) when
-- the last fd_txer_p appeared
p_fd_txer_capture : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rst = '1') then
fd_txer <= '1';
if(core_rst = '1' or fd_host_rst = '1' or macrocyc_load_p = '1') then
reg_to_mt.fd_txer_tstamp_i <= (others => '0');
else
if fd_txer_p = '1' then
fd_txer <= '0';
reg_to_mt.fd_txer_tstamp_i <= '0' & macrocyc_cnt;
end if;
end if;
......@@ -716,41 +773,17 @@ begin
end process;
---------------------------------------------------------------------------------------------------
-- DAC --
---------------------------------------------------------------------------------------------------
-- Communication with the SPEC DAC AD5662BRM2 that controls the 20 MHz OSC2 which is the source of
-- the design's timing. Setting the DAC at its middle range maximized the oscillator's stability;
-- this is important for free-running applications that are not using the ext_sync_i
cmp_dac_config : spec_serial_dac_arb
generic map
(g_invert_sclk => false,
g_num_extra_bits => 8)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
val1_i => reg_from_mt.dac_config_value_o,
load1_i => reg_from_mt.dac_config_load_o, -- monostable: 1-clk-tick-long pulse
val2_i => (others => '0'),
load2_i => '0',
dac_cs_n_o(0) => dac_cs_n_o(0),
dac_cs_n_o(1) => dac_cs_n_o(1),
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o);
---------------------------------------------------------------------------------------------------
-- DS18B20U one wire --
-- DS18B20U ONE WIRE --
---------------------------------------------------------------------------------------------------
-- Communication with the 1-wire DS18B20U+ for the unique ID and temperature reading;
-- rather than sw bit-banging the whole 1-wire communication is implemented in vhdl, to simplify
-- drivers. Note that a temperature reading is provided every second, with the first one a couple
-- of sec after the board power-up/ reset.
-- different than in other designs that implement sw-bit-banging, here the communication is
-- implemented in vhdl, so as to simplify the drivers.
-- Note that a temperature reading is provided every second, with the first one a couple of sec
-- after the board power-up/ reset.
cmp_onewire: gc_ds182x_interface
generic map (freq => 100)
generic map (freq => c_QUARTZ_FREQ_MHZ_INT)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -760,85 +793,65 @@ begin
id_read_o => onewire_read_p,
pps_p_i => pps_is_zero);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- pps generator based on the 100 MHz clk
cmp_pps_gen: wf_decr_counter
generic map(g_counter_lgth => 27)
generic map(g_counter_lgth => c_1SEC_CNT_LGTH)
port map
(uclk_i => clk_i,
counter_rst_i => core_rst,
counter_decr_i => '1',
counter_load_i => pps_load_p,
counter_top_i => "101111101011110000100000000", -- 100'000'000
counter_top_i => c_1SEC_CLK_TICKS,
counter_is_zero_o => pps_is_zero);
-- -- -- -- -- -- -- -- -- -- --
pps_load_p <= pps_is_zero; -- looping
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- registering of the read values
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- registering of the read values upon the activation of the id_read_o
reg_reading: process(clk_i)
begin
if rising_edge(clk_i) then
reg_to_mt.ds1820_temper_i <= (others => '0');
reg_to_mt.ds1820_id_lsb_i <= (others => '0');
reg_to_mt.ds1820_id_msb_i <= (others => '0');
if(onewire_read_p = '1') then
reg_to_mt.ds1820_temper_i <= tmp_temper;
reg_to_mt.ds1820_id_lsb_i <= tmp_id (31 downto 0);
reg_to_mt.ds1820_id_msb_i <= tmp_id (63 downto 32);
if core_rst = '1' then
reg_to_mt.ds1820_temper_i <= (others => '0');
reg_to_mt.ds1820_id_lsb_i <= (others => '0');
reg_to_mt.ds1820_id_msb_i <= (others => '0');
else
if(onewire_read_p = '1') then
reg_to_mt.ds1820_temper_i <= tmp_temper;
reg_to_mt.ds1820_id_lsb_i <= tmp_id (31 downto 0);
reg_to_mt.ds1820_id_msb_i <= tmp_id (63 downto 32);
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- LEDs & aux --
-- LEDs & AUX --
---------------------------------------------------------------------------------------------------
cmp_out_of_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => macrocyc_cnt_zero_p,
extended_o => out_of_sync_led);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sync_led: gc_extend_pulse
generic map
(g_width => 10000)--1000000
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => ext_sync_p,
extended_o => sync_led);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_tmp_ext: gc_extend_pulse
generic map
(g_width => 10000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => macrocyc_cnt_twentyfive_p,
extended_o => macrocyc_cnt_twentyfive);
macrocyc_cnt_twentyfive_p <= '1' when macrocyc_cnt = "0000000000000000000000000011001" else '0';
aux_o(7) <= out_of_sync_led;
aux_o(6) <= mf_dbg_p_ext;
aux_o(5) <= reg_from_mt.dbg_o(5);
aux_o(4) <= reg_from_mt.dbg_o(4); --rx_byte_ready_p;
aux_o(3) <= ext_sync_p_cnt_rst;--mf_dbg(3); --macrocyc_cnt_zero_p;
aux_o(2) <= reg_from_mt.macrocyc_start_o;--(2); --tx_completed;
aux_o(1) <= macrocyc_cnt_twentyfive;--mf_dbg(1);
aux_o(0) <= sync_led;--mf_dbg(0); --sync_led;
-- active low LEDs
leds_o(0) <= not reg_from_mt.led_rx_act_o;
leds_o(1) <= not reg_from_mt.led_rx_err_o;
leds_o(2) <= not reg_from_mt.led_tx_act_o;
leds_o(3) <= not reg_from_mt.led_tx_err_o;
leds_o(4) <= not reg_from_mt.led_ext_sync_act_o when reg_from_mt.led_ext_sync_used_o = '1' else '0';
leds_o(5) <= not reg_from_mt.led_ext_sync_err_o when reg_from_mt.led_ext_sync_used_o = '1' else '0';
leds_o(7 downto 6) <= "00"; -- not used
leds_o(31 downto 8) <= reg_from_mt.led_dbg_o;
---------------------------------------------------------------------------------------------------
-- Sigh:-/ --
-- Assignments --
---------------------------------------------------------------------------------------------------
-- To simplify the interface between the MT and the fmc_masterfip_core, the serialized/deserialized
-- payload bytes are stored in registers, not in FIFO.
-- The fmc_masterfip_core is copying locally the tx registers upon a tx_stat_start.
-- The processor should copy all the rx data upon a rx_stat_frame_ok; the data stays stable in the
-- rx_frame regs until a rx_rst or until the detection of another rx_stat_frame_ok; this in the
-- worst case of the fastest bit rate 2.5 Mbps with a received frame being followed by the shortest
-- RP_FIN is: (Min Turnaround time of a node = 4 us) + (RP_FIN duration = 19.2 us) = 23.2 us.
-- tx regs
tx_frame(0) <= reg_from_mt.tx_payld_reg1_o;
tx_frame(1) <= reg_from_mt.tx_payld_reg2_o;
......@@ -975,10 +988,10 @@ begin
reg_to_mt.rx_payld_reg64_i <= rx_frame(63);
reg_to_mt.rx_payld_reg65_i <= rx_frame(64);
reg_to_mt.rx_payld_reg66_i <= rx_frame(65);
reg_to_mt.rx_payld_reg67_i <= rx_frame(66);
reg_to_mt.rx_payld_reg67_i <= rx_frame(66);
---------------------------------------------------------------------------------------------------
-- CHIPSCOPE --
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
-- chipscope_ila_1 : chipscope_ila
-- port map (
......@@ -995,20 +1008,20 @@ begin
-- TRIG0(8 downto 0) <= reg_from_mt.tx_ctrl_bytes_num_o;
-- TRIG0(18 downto 11) <= tx_ctrl_byte;
-- TRIG0(27 downto 19) <= reg_to_mt.tx_stat_curr_byte_indx_i;
-- TRIG0(28) <= tx_completed_p;
-- TRIG0(29) <= fd_txena;
-- TRIG0(30) <= fd_txd;
-- TRIG0(31) <= fd_txck;
-- TRIG1 <= tx_frame(0);
-- TRIG0(28) <= tx_completed_p;
-- TRIG0(29) <= fd_txena;
-- TRIG0(30) <= fd_txd;
-- TRIG0(31) <= fd_txck;
-- TRIG1 <= tx_frame(0);
-- TRIG1(15 downto 8) <= rx_byte_index;
-- TRIG2(8 downto 0) <= rx_byte_index;
-- TRIG2(9) <= rx_fss_received_p;
-- TRIG2(10) <= rx_byte_ready_p;
-- TRIG2(9) <= rx_fss_received_p;
-- TRIG2(10) <= rx_byte_ready_p;
-- TRIG2(18 downto 11) <= rx_byte;
-- TRIG2(26 downto 19) <= rx_ctrl_byte;
-- TRIG2(27) <= rx_frame_ok_p;
-- TRIG2(28) <= rx_crc_wrong_p;
-- TRIG2(29) <= core_rst;
-- TRIG2(27) <= rx_frame_ok_p;
-- TRIG2(28) <= rx_crc_wrong_p;
-- TRIG2(29) <= core_rst;
-- TRIG2(31 downto 30) <= speed_b1_i & speed_b0_i;
end rtl;
......
rtl/from_nanofip/wf_package.vhd
View file @ 86ec47a0
......@@ -54,9 +54,13 @@ package wf_package is
---------------------------------------------------------------------------------------------------
-- 10ns clock for the masterFIP_core; same for the CPUs
constant c_QUARTZ_PERIOD : real := 10.0;
constant c_QUARTZ_PERIOD_NS : real := 10.0;
constant c_QUARTZ_FREQ_MHZ : real := 100.0;
constant c_QUARTZ_FREQ_MHZ_INT : integer := 100;
constant c_1SEC_CNT_LGTH : natural := 27;
constant c_1SEC_CLK_TICKS : unsigned := to_unsigned((1000000000 / integer(c_QUARTZ_PERIOD_NS)),
c_1SEC_CNT_LGTH);
---------------------------------------------------------------------------------------------------
-- Constants regarding the session timeout counters --
---------------------------------------------------------------------------------------------------
......@@ -81,7 +85,7 @@ package wf_package is
-- Constant regarding the deglitch filter --
---------------------------------------------------------------------------------------------------
constant c_DEGLITCH_THRESHOLD : natural := 4;
constant c_DEGLITCH_THRESHOLD : natural := 10;
---------------------------------------------------------------------------------------------------
......@@ -138,11 +142,13 @@ package wf_package is
-- transmission/ reception periods.
constant c_BIT_RATE_UCLK_TICKS_31_25Kbit: unsigned :=
to_unsigned((32000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
to_unsigned((32000 / integer(c_QUARTZ_PERIOD_NS)),c_PERIODS_COUNTER_LGTH);
constant c_BIT_RATE_UCLK_TICKS_1_Mbit: unsigned :=
to_unsigned((1000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
to_unsigned((1000 / integer(c_QUARTZ_PERIOD_NS)),c_PERIODS_COUNTER_LGTH);
constant c_BIT_RATE_UCLK_TICKS_2_5_Mbit: unsigned :=
to_unsigned((400 /integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
to_unsigned((400 /integer(c_QUARTZ_PERIOD_NS)),c_PERIODS_COUNTER_LGTH);
constant c_BIT_RATE_UCLK_TICKS_5_Mbit: unsigned :=
to_unsigned((200 /integer(c_QUARTZ_PERIOD_NS)),c_PERIODS_COUNTER_LGTH);
-- Creation of a table with the c_BIT_RATE_UCLK_TICKS info per bit rate
type t_uclk_ticks is array (Natural range <>) of unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
......@@ -151,7 +157,7 @@ package wf_package is
(0 => (c_BIT_RATE_UCLK_TICKS_31_25Kbit),
1 => (c_BIT_RATE_UCLK_TICKS_1_Mbit),
2 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit),
3 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit));
3 => (c_BIT_RATE_UCLK_TICKS_5_Mbit));
---------------------------------------------------------------------------------------------------
......
rtl/masterFIP_pkg.vhd
View file @ 86ec47a0
......@@ -48,7 +48,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.wf_package.all;
use work.mrfip_wbgen2_pkg.all;
use work.masterfip_wbgen2_pkg.all;
......@@ -120,7 +120,7 @@ package masterFIP_pkg is
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000FFFF",
addr_last => x"00000000000003FF",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000AAA", -- ...
......@@ -130,28 +130,42 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
-- Vector with the data Registers --
-- Array of words with the WorldFIP produced/consumed PAYLOAD bytes --
---------------------------------------------------------------------------------------------------
subtype data_word is std_logic_vector(31 downto 0);
-- Structure with 67 words of 32-bit each = 268 bytes which represents the max length of a frame,
-- including FSS (2 bytes),
-- CTRL (1 byte),
-- Data (up to 262 for a message),
-- CRC (2 bytes) and
-- FES (1 byte).
-- Note that the deserializer, is registering bytes one by one as they arrive, after the FSS and
-- until the FES detection.
-- Upon the rx_fss_crc_fes_ok_p_o the processor needs to read the rx_ctrl_byte (separate register,
-- not included in the rx_frame structure) and rx_byte_index_o-4 bytes from the rx_frame structure
-- (minus the CTRL, CRC and FES bytes)
type rx_frame_t is array (66 downto 0) of data_word;
constant C_BYTE_WIDTH : integer := 8;
constant C_WORD_WIDTH : integer := 32;
-- Declaration of a structure with 67 words of 32-bit each = 268 bytes which represent the max
-- length of a frame, including
-- FSS (2 bytes),
-- CTRL (1 byte),
-- Data (up to 262 for a message),
-- CRC (2 bytes) and
-- FES (1 byte).
-- Note that the deserializer, is registering bytes one by one as they arrive, after the FSS and
-- until the FES detection; therefore the max amount of bytes expected to be counted by the
-- deserializer is 266. Upon the rx_fss_crc_fes_ok_p_o the processor needs to read the rx_ctrl_byte
-- (separate register, not included in the rx_frame structure) and rx_byte_index_o-4 bytes from the
-- rx_frame structure (minus the CTRL, CRC and FES bytes).
-- Note that the serializer, is counting one by one the bytes that are serialized, after the FSS and
-- before the CRC; therefore the max amount of bytes expected to be counted by the serializer is
-- 263.
constant C_MAX_FRAME_WORDS : integer := 67;
constant C_FRAME_WORDS_CNT_LGTH : integer := 7; -- ((std_logic_vector(C_MAX_FRAME_WORDS))'left)
constant C_FRAME_BYTES_CNT_LGTH : integer := 9; -- (((std_logic_vector(C_MAX_FRAME_WORDS) srl 2))'left)
subtype data_word is std_logic_vector(C_WORD_WIDTH-1 downto 0);
type rx_frame_t is array (C_MAX_FRAME_WORDS-1 downto 0) of data_word;
-- Note that the serializer is not provided with the CRC and FES; the processor needs to provide
-- the CTRL byte (in a separate register, not included in the rx_frame structure) and up to
-- 262 Data bytes. In principle 66 data_words would be sufficient, but for symmetry with rx we kept 67.
type tx_frame_t is array (66 downto 0) of data_word;
type tx_frame_t is array (C_MAX_FRAME_WORDS-1 downto 0) of data_word;
---------------------------------------------------------------------------------------------------
......@@ -173,220 +187,148 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
---------------------------------------------------------------------------------------------------
-- Constant regarding the deglitch filters --
---------------------------------------------------------------------------------------------------
-- constant c_DEGLITCH_THRESHOLD : natural := 10; -- declared in the wf_package
---------------------------------------------------------------------------------------------------
-- Components Declarations: --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
component fmc_masterFIP_core is
generic
(g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := FALSE);
(g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := FALSE);
port
(clk_i : in std_logic;
rst_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
onewire_b : inout std_logic;
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_n_o : out std_logic;
ext_sync_tst_n_o : out std_logic;
ext_sync_i : in std_logic;
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
adc_prim_conn_n_o : out std_logic;
adc_sec_conn_n_o : out std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
aux_o : out std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0));
(clk_i : in std_logic;
rst_n_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
onewire_b : inout std_logic;
fd_rxcdn_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_n_o : out std_logic;
ext_sync_a_i : in std_logic;
leds_o : out std_logic_vector(g_width-1 downto 0);
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0));
end component;
---------------------------------------------------------------------------------------------------
component fmc_masterfip_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_mrfip_in_registers;
regs_o : out t_mrfip_out_registers
);
end component;
component masterfip_wbgen2_csr is
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_masterfip_in_registers;
regs_o : out t_masterfip_out_registers);
end component;
---------------------------------------------------------------------------------------------------
component spec_reset_gen is
port
(clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
(clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
component temperature is
port
(
clk1m: in std_logic;
temper: out std_logic_vector(15 downto 0);
wireout: inout std_logic
);
end component;
component onewire_interf is
generic (
freq : integer := 40 --Frequency in MHz
);
port(
clk_i : in std_logic;
rst_n_i: in std_logic;
onewire_b : inout std_logic; -- IO to be connected to the chip (DS1822)
id_o : out std_logic_vector(63 downto 0); -- ID value
temper_o : out std_logic_vector(15 downto 0); -- Temperature value (refreshed every second)
id_read_o : out std_logic; -- ID value is valid
pps_p_i : in std_logic; -- Pulse per second (for temperature read)
id_ok_o : out std_logic -- Same as IdRead, but not reset with RstN !!
);
end component;
---------------------------------------------------------------------------------------------------
component carrier_info
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
carrier_info_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
carrier_info_carrier_reserved_i : in std_logic_vector(11 downto 0);
carrier_info_carrier_type_i : in std_logic_vector(15 downto 0);
carrier_info_stat_fmc_pres_i : in std_logic;
carrier_info_stat_p2l_pll_lck_i : in std_logic;
carrier_info_stat_sys_pll_lck_i : in std_logic;
carrier_info_stat_ddr3_cal_done_i : in std_logic;
carrier_info_stat_reserved_i : in std_logic_vector(27 downto 0);
carrier_info_ctrl_led_green_o : out std_logic;
carrier_info_ctrl_led_red_o : out std_logic;
carrier_info_ctrl_dac_clr_n_o : out std_logic;
carrier_info_ctrl_reserved_o : out std_logic_vector(28 downto 0);
carrier_info_rst_fmc0_n_o : out std_logic;
carrier_info_rst_fmc0_n_i : in std_logic;
carrier_info_rst_fmc0_n_load_o : out std_logic;
carrier_info_rst_reserved_o : out std_logic_vector(30 downto 0));
end component carrier_info;
---------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
component masterfip_rx is
port (
clk_i : in std_logic;
speed_i : in std_logic_vector (1 downto 0);
fd_rxd_a_i : in std_logic;
rst_i : in std_logic;
rx_rst_i : in std_logic;
-----------------------------------------------------------------
rx_byte_index_o : out std_logic_vector (15 downto 0);
rx_word_index_o : out std_logic_vector (6 downto 0);
rx_ctrl_byte_o : out std_logic_vector (7 downto 0);
rx_frame_o : out rx_frame_t;
rx_byte_o : out std_logic_vector (7 downto 0);
rx_byte_ready_p_o : out std_logic;
rx_fss_crc_fes_ok_p_o : out std_logic;
rx_fss_received_p_o : out std_logic;
rx_crc_wrong_p_o : out std_logic );
-----------------------------------------------------------------
port
(clk_i : in std_logic;
speed_i : in std_logic_vector(1 downto 0);
rx_d_a_i : in std_logic;
rst_i : in std_logic;
rx_rst_i : in std_logic;
rx_byte_index_o : out std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
rx_word_index_o : out std_logic_vector(C_FRAME_WORDS_CNT_LGTH-1 downto 0);
rx_ctrl_byte_o : out std_logic_vector(C_BYTE_WIDTH-1 downto 0);
rx_frame_o : out rx_frame_t;
rx_byte_o : out std_logic_vector(C_BYTE_WIDTH-1 downto 0);
rx_byte_ready_p_o : out std_logic;
rx_fss_crc_fes_ok_p_o : out std_logic;
rx_fss_received_p_o : out std_logic;
rx_crc_wrong_p_o : out std_logic );
end component masterfip_rx;
---------------------------------------------------------------------------------------------------
component masterfip_tx is
port (
clk_i : in std_logic;
speed_i : in std_logic_vector (1 downto 0);
rst_i : in std_logic;
tx_start_p_i : in std_logic;
tx_bytes_num_i : in std_logic_vector (15 downto 0);
tx_frame_i : in tx_frame_t;
tx_ctrl_byte_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
tx_byte_index_o : out std_logic_vector (15 downto 0);
tx_end_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
tx_clk_o : out std_logic);
-----------------------------------------------------------------
port
(clk_i : in std_logic;
speed_i : in std_logic_vector(1 downto 0);
rst_i : in std_logic;
tx_start_p_i : in std_logic;
tx_bytes_num_i : in std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
tx_frame_i : in tx_frame_t;
tx_ctrl_byte_i : in std_logic_vector(C_BYTE_WIDTH-1 downto 0);
tx_byte_index_o : out std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
tx_end_p_o : out std_logic;
tx_d_o : out std_logic;
tx_ena_o : out std_logic;
tx_clk_o : out std_logic);
end component masterfip_tx;
---------------------------------------------------------------------------------------------------
component decr_counter
generic
(width : integer := 32);
(width : integer := 32);
port
(clk_i : in std_logic;
rst_i : in std_logic;
counter_load_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0);
-------------------------------------------------------------
counter_is_zero_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0));
-------------------------------------------------------------
(clk_i : in std_logic;
rst_i : in std_logic;
counter_load_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0);
counter_is_zero_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0));
end component;
---------------------------------------------------------------------------------------------------
component incr_counter is
generic
(g_counter_lgth : natural := 4);
(g_counter_lgth : natural := 4);
port
(clk_i : in std_logic;
counter_incr_i : in std_logic;
counter_reinit_i : in std_logic;
-------------------------------------------------------------
counter_o : out std_logic_vector (g_counter_lgth-1 downto 0);
counter_is_full_o : out std_logic);
(clk_i : in std_logic;
counter_incr_i : in std_logic;
counter_reinit_i : in std_logic;
counter_o : out std_logic_vector(g_counter_lgth-1 downto 0);
counter_is_full_o : out std_logic);
end component incr_counter;
-------------------------------------------------------------
end masterFIP_pkg;
--=================================================================================================
......
rtl/masterfip_rx.vhd
View file @ 86ec47a0
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
......@@ -13,36 +13,46 @@
-- File masterfip_rx.vhd |
-- |
-- Description The unit groups the main actions that regard FIELDRIVE data reception. |
-- It instantiates the units/processes: |
-- Figure 1 shows the main units/processes; the units RX DESERIALIZER, RX OSC and |
-- RX DEGLITCHER come unmodified from the nanoFIP project. |
-- Figure 2 shows the WorldFIP frame structure; note that the fmc_masterfip_core |
-- is completely ignorant of the notion of PDU_TYPE, LGTH, MPS, etc fields inside |
-- the PAYLOAD part of the frame and is not checking them during reception. |
-- It is the processor (MT) that is handling individually the bytes inside the |
-- PAYLOAD frame field. On the other hand the FSS, CRC and FES fields are |
-- checked by the masterfip_rx. |
-- As long as the rx_rst_i is not activated the deserializer is probing the bus |
-- looking for a FSS; upon the detection of a FES it activates the rx_crc_wrong_p_o |
-- or rx_fss_crc_fes_ok_p_o accordingly. |
-- |
-- o wf_rx_osc : for the clock recovery |
-- RX OSC for the clock recovery |
-- |
-- o wf_rx_deglitcher : for the filtering of the input FD_RXD |
-- RX for the filtering of the input FD_RXD |
-- |
-- o wf_rx_deserializer: for the bytes retrieval; also detects FSS/FES & checks CRC |
-- RX DESERIALIZER for the bytes retrieval; also detects FSS/FES & checks CRC |
-- |
-- o bytes_c : for the counting of the retrieved bytes |
-- BYTES_C for the counting of the retrieved bytes |
-- |
-- o create_32bit_words: for the formation of 32-bit words to be provided to the |
-- processor (Mock Turtle for example) |
-- CREATE 32bit WORDS for the formation of 32-bit words to be provided to the |
-- processor (Mock Turtle for example) |
-- |
-- Mock Turtle |
-- ___________________________________________________________ |
-- | | |
-- | _________ _______________________ | |
-- | | | | | | |
-- | | bytes_c | | create_32bit_words | | |
-- | | BYTES_C | | CREATE 32bit WORDS | | |
-- | |_________| |_______________________| | |
-- | /\ /\ _________ | |
-- | _______________________________________ | | | |
-- | | | | | | |
-- | | wf_rx_deserializer | | wf_rx | | |
-- | | | < | _osc | | |
-- | | RX DESERIALIZER | | RX OSC | | |
-- | | | < | | | |
-- | |_______________________________________| | | | |
-- | /\ |_________| | |
-- | _______________________________________ | |
-- | | | | |
-- | | wf_rx_deglitcher | | |
-- | | RX DEGLITCHER | | |
-- | |_______________________________________| | |
-- | | |
-- |___________________________________________________________| |
......@@ -50,15 +60,12 @@
-- ___________________________________________________________________ |
-- 0_____________________________FIELDBUS______________________________0 |
-- |
-- ___________ ______ ________________________________________ ___________ _______ |
-- |____FSS____|_CTRL_||_____________..DATA/PAYLOAD..___________||____CRC____|__FES__| |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 30/09/2015 |
-- Version v0.01 |
-- Depends on |
-- Figure 2: WorldFIP Frame structure |
-- |
---------------- |
-- Last changes |
-- 09/2015 v0.01 EG First version |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -96,48 +103,55 @@ use work.wf_package.all;
--=================================================================================================
entity masterfip_rx is port(
-- INPUTS
clk_i : in std_logic; -- 100 MHZ clock
clk_i : in std_logic; -- only one clk domain
rst_i : in std_logic; -- core rst, synched with clk_i
rst_i : in std_logic; -- core rst, synched with clk_i
rx_rst_i : in std_logic; -- rx reset during production or
-- reset pulse from the processor (eg. MT)
-- when during reception a frame is rejected
-- (ex: RP_DAT > 133 bytes, wrong CTRL byte)
speed_i : in std_logic_vector(1 downto 0); -- WorldFIP bit rate
rx_rst_i : in std_logic; -- dedicated rx reset during transmission OR
-- reset pulse from the processor (MT) when for eg. a
-- frame is rejected during reception
-- (ex: RP_DAT > 133 bytes, wrong CTRL byte)
fd_rxd_a_i : in std_logic; -- FielDrive receiver data
speed_i : in std_logic_vector(1 downto 0); -- WorldFIP bit rate
rx_d_a_i : in std_logic; -- FielDrive receiver data
-- OUTPUTS
rx_byte_ready_p_o : out std_logic; -- pulse indicating a new retrieved byte
rx_byte_ready_p_o : out std_logic; -- pulse indicating a new retrieved byte
rx_byte_o : out std_logic_vector(C_BYTE_WIDTH-1 downto 0);
-- currently retrieved byte
rx_byte_o : out std_logic_vector(7 downto 0); -- currently retrieved byte
rx_byte_index_o : out std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
-- index of currently retrieved byte
-- counting starts after FSS; it includes
-- the CTRL, DATA, CRC and FES fields;
-- counting starts from 0 and normally
-- the value should not exceed 265
rx_byte_index_o : out std_logic_vector(15 downto 0);-- index of currently retrieved byte
-- counting starts after FSS; it includes the
-- CTRL, DATA, CRC and FES fields;
-- normally the value should not exceed 266
rx_word_index_o : out std_logic_vector(C_FRAME_WORDS_CNT_LGTH-1 downto 0);
-- index of currently retrieved word
-- counting starts from 0 and normally
-- the value should not exceed 66
rx_word_index_o : out std_logic_vector(6 downto 0); -- index of the word ...
rx_ctrl_byte_o : out std_logic_vector(C_BYTE_WIDTH-1 downto 0); -- frame CTRL byte
rx_ctrl_byte_o : out std_logic_vector(7 downto 0); -- frame CTRL byte
rx_frame_o : out rx_frame_t; -- frame DATA bytes
-- structure with 67 words of 32-bit each = 268 bytes
-- able to house a frame of max length.
-- Upon the rx_fss_crc_fes_ok_p_o the processor needs
-- to read the rx_ctrl_byte and rx_byte_index_o - 4
-- bytes from the rx_frame_o. The content of rx_frame_o
-- changes upon the end of reception of a new frame
-- (i.e. a new rx_fss_crc_fes_ok_p_o).
rx_frame_o : out rx_frame_t; -- frame DATA bytes
-- structure with 67 words of 32-bit each = 268 bytes
-- this represents the max length of a frame.
-- Upon the rx_fss_crc_fes_ok_p_o the processor needs
-- to read the rx_ctrl_byte and rx_byte_index_o - 4
-- bytes from the rx_frame_o.
rx_fss_crc_fes_ok_p_o : out std_logic; -- indication of a frame with correct FSS, FES & CRC;
-- pulse upon FES detection
rx_fss_crc_fes_ok_p_o : out std_logic; -- indication of a frame with
-- correct FSS, FES & CRC; pulse upon FES detection
rx_crc_wrong_p_o : out std_logic; -- indication of a frame with
-- wrong CRC; pulse upon FES detection
rx_crc_wrong_p_o : out std_logic; -- indication of a frame with wrong CRC; pulse upon FES
rx_fss_received_p_o : out std_logic); -- pulse upon FSS detection (ID/ RP_DAT)
rx_fss_received_p_o : out std_logic); -- pulse upon FSS detection (ID/ RP_DAT)
end entity masterfip_rx;
......@@ -148,21 +162,25 @@ end entity masterfip_rx;
architecture struc of masterfip_rx is
-- wf_rx_osc
signal s_rx_osc_rst, s_adjac_bits_window, s_signif_edge_window : std_logic;
signal s_sample_bit_p, s_sample_manch_bit_p : std_logic;
signal s_rx_osc_rst, s_adjac_bits_window : std_logic;
signal s_signif_edge_window : std_logic;
signal s_sample_bit_p : std_logic;
signal s_sample_manch_bit_p : std_logic;
-- wf_rx_deglitcher
signal s_fd_rxd_filt, s_rxd_filt_edge_p : std_logic;
signal s_fd_rxd_filt_f_edge_p, s_fd_rxd_filt_r_edge_p : std_logic;
-- wf_rx_deserializer
signal rx_byte_ready_p, rx_fss_crc_fes_ok_p : std_logic;
signal rx_byte : std_logic_vector (7 downto 0);
signal s_fd_rxd_filt, s_rxd_filt_edge_p : std_logic;
signal s_fd_rxd_filt_f_edge_p : std_logic;
signal s_fd_rxd_filt_r_edge_p : std_logic;
-- wf_rx_deserializer
signal rx_byte_ready_p : std_logic;
signal rx_fss_crc_fes_ok_p : std_logic;
signal rx_byte : std_logic_vector (C_BYTE_WIDTH-1 downto 0);
-- retrieved bytes into 32-bit regs
signal byte0, byte1, byte2, byte3 : std_logic_vector(7 downto 0) := (others => '0');
signal word32_num : integer range 0 to 66;
signal byte0, byte1, byte2, byte3 : std_logic_vector(C_BYTE_WIDTH-1 downto 0);
signal word32_num : integer range 0 to C_MAX_FRAME_WORDS-1;
-- bytes counter
signal rx_byte_index, rx_byte_index_d1 : unsigned(15 downto 0) := (others => '0');
signal bytes_c_rst : std_logic;
signal rx_byte_index, rx_byte_index_d1 : unsigned(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
signal bytes_c_rst : std_logic;
--=================================================================================================
-- architecture begin
......@@ -176,8 +194,8 @@ begin
cmp_rx_deglitcher: wf_rx_deglitcher
port map(
uclk_i => clk_i,
nfip_rst_i => rst_i,
fd_rxd_a_i => fd_rxd_a_i,
nfip_rst_i => rst_i, -- or rx_rst??
fd_rxd_a_i => rx_d_a_i,
-----------------------------------------------------------------
fd_rxd_filt_o => s_fd_rxd_filt,
fd_rxd_filt_edge_p_o => s_rxd_filt_edge_p,
......@@ -185,7 +203,7 @@ begin
-----------------------------------------------------------------
s_fd_rxd_filt_r_edge_p <= s_rxd_filt_edge_p and (not s_fd_rxd_filt_f_edge_p);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_deserializer: wf_rx_deserializer
port map(
uclk_i => clk_i,
......@@ -210,11 +228,11 @@ begin
rx_byte_o <= rx_byte;
rx_fss_crc_fes_ok_p_o <= rx_fss_crc_fes_ok_p;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_osc: wf_rx_osc
port map(
uclk_i => clk_i,
rate_i => speed_i,
rate_i => speed_i, -- or rx_rst??
nfip_rst_i => rst_i,
fd_rxd_edge_p_i => s_rxd_filt_edge_p,
rx_osc_rst_i => s_rx_osc_rst,
......@@ -230,11 +248,7 @@ begin
-- bytes counter --
---------------------------------------------------------------------------------------------------
cmp_rx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 16) -- normally max frame size = 268 bytes which would fit in 9 bits;
-- more bits have been added to be able to detect if the
-- deserializer is by mistake continuing acquiring bytes;
-- note: the 83ms time-out of the deserializer unit, translates to
-- up to 26000 bytes at the fastest speed 2.5Mbps
generic map(g_counter_lgth => C_FRAME_BYTES_CNT_LGTH)
port map(
uclk_i => clk_i,
counter_reinit_i => bytes_c_rst,
......@@ -246,10 +260,10 @@ begin
bytes_c_rst <= '1' when (rst_i = '1' or rx_rst_i = '1') else '0';
rx_byte_index_o <= std_logic_vector(rx_byte_index);
---------------------------------------------------------------------------------------------------
-- combination of four retrieved bytes to a 32-bit word --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
create_32bit_words: process (clk_i)
begin
if rising_edge (clk_i) then
......@@ -257,13 +271,13 @@ begin
byte0 <= (others => '0');
byte1 <= (others => '0');
byte2 <= (others => '0');
byte3 <= (others => '0');
rx_ctrl_byte_o <= (others => '0');
byte3 <= (others => '0');
rx_ctrl_byte_o <= (others => '0');
else
if rx_byte_ready_p = '1' then
if rx_byte_index = resize(unsigned(c_CTRL_BYTE_INDEX),9) then
rx_ctrl_byte_o <= rx_byte;
else
rx_ctrl_byte_o <= rx_byte;
else
byte0 <= rx_byte;
byte1 <= byte0;
byte2 <= byte1;
......@@ -274,7 +288,7 @@ begin
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Storage of consumed bytes to the cons_frame regs --
---------------------------------------------------------------------------------------------------
......@@ -287,33 +301,34 @@ begin
rx_byte_index_d1 <= (others =>'0'); -- needed for synching
else
if rx_byte_ready_p = '1' then
rx_byte_index_d1 <= rx_byte_index;
rx_byte_index_d1 <= rx_byte_index;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
data_transfer_to_regs: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
word32_num <= 0;
rx_frame_o <= (others =>(others =>'0'));
else
-- upon rx_fss_crc_fes_ok_p, the last 32bit word will contain for sure CRC0 and CRC1
-- and it may also contain one or two bytes of data.
-- the last word will always include as last bytes, byte1 and byte0: the two CRC bytes.
-- it could also include one or two useful data bytes
if rx_fss_crc_fes_ok_p = '1' then
if word32_num = 0 then -- only in the case of RP_FIN, where there are not enough bytes to create a word; needed for keeping the MT sw generic
if word32_num = 0 then -- only in the case of RP_FIN, where there are not enough
-- bytes to create a word; needed for keeping the MT sw generic
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3; --
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3; --
elsif (rx_byte_index-2) mod 4 = 3 then -- [CRC|CRC|BYTE|BYTE]
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3; -- byte 3 and byte 2 are useful
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3; -- byte 3 and byte 2 are useful
elsif (rx_byte_index-2) mod 4 = 2 then -- [0|CRC|CRC|BYTE]
word32_num <= word32_num + 1;
......@@ -329,7 +344,7 @@ begin
end if;
end if;
end process;
rx_word_index_o <= std_logic_vector(to_unsigned(word32_num,7));
......
rtl/masterfip_tx.vhd
View file @ 86ec47a0
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
......@@ -13,52 +13,61 @@
-- File masterfip_tx.vhd |
-- |
-- Description The unit groups the main actions that regard FIELDRIVE data transmission. |
-- It instantiates the units/processes: |
-- Figure 1 shows the main units/processes; the units TX SERIALIZER and TX OSC come |
-- unmodified from the nanoFIP project. |
-- Figure 2 shows the frame structure; note that the fmc_masterfip_core is completely|
-- ignorant of the notion of PDU_TYPE, LGTH, MPS, etc fields inside the PAYLOAD |
-- part of the frame. It is the processor (MT) that is providing all the bytes inside|
-- the PAYLOAD frame field. On the other hand the FSS, CRC and FES fields are |
-- generated by the masterfip_tx. |
-- The serialization starts upon a rising edge on the tx_start_p_i and upon the end |
-- of the FES transmission the masterfip_tx is activating the tx_end_p_o signal. |
-- |
-- o wf_tx_serializer: that receives bytes from the processor (Mock Turtle for |
-- example) trough the tx_frame structure, encodes them |
-- (Manchester 2), adds the FSS, FCS, FES fields and puts one by |
-- one bits to the FIELDRIVE output FD_TXD following the |
-- synchronization signals from the wf_tx_osc unit. |
-- Also generates the output FD_TXENA. |
-- o TX SERIALIZER this unit comes unmodified from the nanoFIP project. |
-- It receives bytes from the processor (Mock Turtle for example) |
-- trough the tx_frame structure, encodes them in Manchester 2, |
-- adds the FSS, CRC, FES fields and puts one by one bits to the |
-- FIELDRIVE output FD_TXD following the synchronization signals |
-- from the wf_tx_osc unit. It also generates the output FD_TXENA. |
-- |
-- o wf_tx_osc : that generates the output FD_TXCK and the array of pulses |
-- tx_sched_p_buff, used for the synchronization of the |
-- wf_tx_serializer's actions. |
-- o TX OSC this unit comes unmodified from the nanoFIP project. |
-- It generates the output FD_TXCK as well as an array of pulses, |
-- tx_sched_p_buff, used for the synchronization of the |
-- TX SERIALIZER's actions. |
-- |
-- o data_retrieval : that copies the bytes provided by the processor upon the |
-- activation of the signal tx_start. |
-- o DATA RETRIEVAL this unit copies the bytes provided by the processor (MT) |
-- upon the activation of the signal tx_start. |
-- |
-- Mock Turtle |
-- ___________________________________________________________ |
-- | _______________________________ | |
-- | | | | |
-- | | data_retrieval | | |
-- | | DATA RETRIEVAL | | |
-- | |_______________________________| | |
-- | \/ \/ | |
-- | _________ _______________ | |
-- | | | | | | |
-- | | bytes_c | | select_byte | | |
-- | | BYTES_C | | SELECT BYTE | | |
-- | |_________| |_______________| | |
-- | \/ | |
-- | _____________ __________________________________ | |
-- | | | | | | |
-- | | wf_tx_osc | > | wf_tx_serializer | | |
-- | | TX OSC | > | TX SERIALIZER | | |
-- | | | | | | |
-- | |_____________| |__________________________________| | |
-- |___________________________________________________________| |
-- \/ |
-- \/ |
-- ___________________________________________________________________ |
-- 0_____________________________FIELDBUS______________________________O |
-- |
-- Figure 1: Module architecture |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 30/09/2015 |
-- Version v0.01 |
-- ___________ ______ ________________________________________ ___________ _______ |
-- |____FSS____|_CTRL_||_____________..DATA/PAYLOAD..___________||____CRC____|__FES__| |
-- |
-- Figure 2: WorldFIP Frame structure |
-- |
---------------- |
-- Last changes |
-- 09/2015 v0.01 EG First version |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -96,34 +105,39 @@ use work.wf_package.all;
entity masterfip_tx is port(
-- INPUTS
clk_i : in std_logic; -- 100 MHz clock
clk_i : in std_logic; -- only one clk domain
rst_i : in std_logic; -- core rst, synched with clk_i
rst_i : in std_logic; -- core rst, synched with clk_i
speed_i : in std_logic_vector(1 downto 0); -- WorldFIP bit rate
speed_i : in std_logic_vector(1 downto 0); -- WorldFIP bit rate
tx_frame_i : in tx_frame_t; -- frame DATA bytes
-- structure with 66 words of 32-bit each
-- this represents the max length of a frame
-- upon tx_start_p_i only tx_bytes_num_i are read and transmitted
tx_frame_i : in tx_frame_t; -- frame PAYLOAD bytes;
-- structure with 67 words of 32-bit each,
-- able to house a frame of max length;
-- upon tx_start_p_i, tx_bytes_num_i are
-- copied locally to be serialized
tx_bytes_num_i : in std_logic_vector(15 downto 0); -- number of bytes to be serialized
tx_bytes_num_i : in std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
-- number of bytes to be serialized
tx_ctrl_byte_i : in std_logic_vector(7 downto 0); -- frame CTRL byte
tx_ctrl_byte_i : in std_logic_vector(C_BYTE_WIDTH-1 downto 0);
-- frame CTRL byte
tx_start_p_i : in std_logic; -- indication for the start of the serialization
tx_start_p_i : in std_logic; -- indication for the start of the serialization
-- OUTPUTS
tx_byte_index_o : out std_logic_vector(15 downto 0); -- index of the byte currently being serialized (0-262)
tx_byte_index_o : out std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
-- indx of byte currently being serialized (0-262)
tx_end_p_o : out std_logic; -- pulse upon termination of a transmission (CRC & FES included)
tx_end_p_o : out std_logic; -- 1-clk-tick long pulse upon termination of
-- transmission (after FES)
tx_data_o : out std_logic; -- FIELDRIVE transmitter data
tx_d_o : out std_logic; -- FIELDRIVE transmitter data
tx_enable_o : out std_logic; -- FIELDRIVE transmitter enable
tx_ena_o : out std_logic; -- FIELDRIVE transmitter enable
tx_clk_o : out std_logic); -- FIELDRIVE transmitter line driver half bit clock
tx_clk_o : out std_logic); -- FIELDRIVE transmitter line driver half bit clk
end entity masterfip_tx;
......@@ -134,19 +148,19 @@ end entity masterfip_tx;
architecture struc of masterfip_tx is
-- frame bytes
signal prod_bytes_c : unsigned(15 downto 0);
signal ctrl_byte, tx_byte : std_logic_vector(7 downto 0);
signal prod_bytes_c : unsigned(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
signal ctrl_byte, tx_byte : std_logic_vector(C_BYTE_WIDTH-1 downto 0);
signal prod_frame : tx_frame_t;
signal word32_num : integer range 0 to 66;
signal word32 : std_logic_vector(31 downto 0);
signal word32_num : integer range 0 to C_MAX_FRAME_WORDS-1;
signal word32 : std_logic_vector(C_WORD_WIDTH-1 downto 0);
-- bytes counter
signal bytes_num : std_logic_vector(15 downto 0);
signal bytes_num : std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
signal prod_data_lgth_match : std_logic;
signal last_data_byte_p, last_data_byte_p_d : std_logic;
-- wf_tx_osc
-- signals for wf_tx_osc
signal s_tx_clk_p_buff : std_logic_vector(c_TX_SCHED_BUFF_LGTH-1 downto 0);
signal s_tx_osc_rst_p : std_logic;
-- other signals
-- signals for wf_tx_serializer
signal byte_request_accept_p : std_logic;
signal byte_request_accept_p_d1 : std_logic;
signal byte_request_accept_p_d2 : std_logic;
......@@ -154,6 +168,7 @@ architecture struc of masterfip_tx is
signal last_data_byte_p_tmp : std_logic;
signal byte_request_accept_p_tmp : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -162,7 +177,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Copy of the frame data --
---------------------------------------------------------------------------------------------------
-- Retrieval of the data bytes upon the tx_start_p_i.
-- Local copy of the data bytes upon the tx_start_p_i.
-- All the frame bytes are copied to local registers; like this the frame data remain stable
-- until the next tx_start_p_i arrives.
......@@ -170,25 +185,33 @@ begin
begin
if rising_edge (clk_i) then
if rst_i = '1' then
prod_frame <= ((others => (others=>'0')));
ctrl_byte <= (others=>'0');
bytes_num <= (others=>'0');
prod_frame <= ((others => (others => '0')));
ctrl_byte <= (others => '0');
bytes_num <= (others => '0');
else
if tx_start_p_i = '1' then
prod_frame <= tx_frame_i; -- copying of the data bytes
ctrl_byte <= tx_ctrl_byte_i; -- copying of the ctrl byte
prod_frame <= tx_frame_i; -- copying of the DATA bytes
ctrl_byte <= tx_ctrl_byte_i; -- copying of the CTRL byte
bytes_num <= tx_bytes_num_i; -- num of bytes to serialize from the prod_frame
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Sequential byte selection --
---------------------------------------------------------------------------------------------------
-- Mux to select the right byte --
---------------------------------------------------------------------------------------------------
-- The process retrieves sequentially one by one the byte to be sent to the serializer.
select_byte: process (clk_i)
-- The following processes are responsible for the selection of the next byte to be serialised.
-- Following the frame structure of Figure 2, after the FSS (which is hard-coded in the
-- wf_tx_serializer's state machine), the first byte to serialize is the CTRL byte that comes from
-- the dedicated register ctrl_byte. Then, bytes are selected one by one from the prod_frame words
-- array, starting from byte(0) of the prod_frame(0). The wf_tx_serializer's signal
-- tx_byte_request_p indicates the need to retrieve a new byte for serialization.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Selection of one 32-bit word of the prod_frame words array
select_word: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
......@@ -199,36 +222,35 @@ begin
end if;
end if;
end if;
end process;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter for the counting of the number of the bytes that are
-- being serialized.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter for the counting of the number of the bytes that are
-- being serialized.
cmp_tx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 16)
generic map(g_counter_lgth => C_FRAME_BYTES_CNT_LGTH)
port map(
uclk_i => clk_i,
counter_reinit_i => tx_start_p_i,
counter_incr_i => tx_byte_request_p,
counter_is_full_o => open,
-------------------------------------------------------
counter_o => prod_bytes_c);
-------------------------------------------------------
tx_byte_index_o <= std_logic_vector(prod_bytes_c);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Selection of one byte
word32 <= prod_frame(word32_num);
tx_byte <= ctrl_byte when prod_bytes_c = "00000000" else
word32(7 downto 0) when prod_bytes_c mod 4 = 1 else
word32(15 downto 8) when prod_bytes_c mod 4 = 2 else
word32(23 downto 16) when prod_bytes_c mod 4 = 3 else
word32(31 downto 24);
tx_byte <= ctrl_byte when prod_bytes_c = "00000000" else -- first byte to serialize is the CTRL
word32(7 downto 0) when prod_bytes_c mod 4 = 1 else -- byte(0) (lsb) of a prod_frame word
word32(15 downto 8) when prod_bytes_c mod 4 = 2 else -- byte(1) of a prod_frame word
word32(23 downto 16) when prod_bytes_c mod 4 = 3 else -- byte(2) of a prod_frame word
word32(31 downto 24); -- byte(3) (msb) of a prod_frame word
---------------------------------------------------------------------------------------------------
-- Serializer as in the nanoFIP project --
-- TX as in the nanoFIP project --
---------------------------------------------------------------------------------------------------
cmp_tx_serializer: wf_tx_serializer
port map(
uclk_i => clk_i,
......@@ -241,13 +263,13 @@ begin
-----------------------------------------------
tx_byte_request_p_o => tx_byte_request_p,
tx_completed_p_o => tx_end_p_o,
tx_data_o => tx_data_o,
tx_data_o => tx_d_o,
tx_osc_rst_p_o => s_tx_osc_rst_p,
tx_enable_o => tx_enable_o);
tx_enable_o => tx_ena_o);
-----------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_tx_osc: wf_tx_osc
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_tx_osc: wf_tx_osc
port map(
uclk_i => clk_i,
rate_i => speed_i,
......@@ -258,20 +280,21 @@ begin
tx_sched_p_buff_o => s_tx_clk_p_buff);
-----------------------------------------------
---------------------------------------------------------------------------------------------------
-- Signals essential to the serializer --
---------------------------------------------------------------------------------------------------
-- Other signals --
---------------------------------------------------------------------------------------------------
-- when s_prod_data_lgth bytes have been counted,the signal prod_data_lgth_match is activated
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- when s_prod_data_lgth bytes have been counted, the signal prod_data_lgth_match is activated
prod_data_lgth_match <= '1' when prod_bytes_c = unsigned(bytes_num) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
synch_signals: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
last_data_byte_p <= '0'; -- indication of the last data byte (CRC, FES not included)
last_data_byte_p <= '0'; -- indication of the last DATA byte (CRC, FES not included)
last_data_byte_p_d <= '0';
byte_request_accept_p_d1 <= '0';
byte_request_accept_p_d2 <= '0';
......@@ -279,6 +302,7 @@ begin
else
last_data_byte_p_d <= last_data_byte_p_tmp;
last_data_byte_p <= last_data_byte_p_d;
byte_request_accept_p_d1 <= byte_request_accept_p_tmp;
byte_request_accept_p_d2 <= byte_request_accept_p_d1;
end if;
......@@ -287,9 +311,10 @@ begin
-- -- -- -- -- -- -- -- -- -- --
byte_request_accept_p_tmp <= tx_byte_request_p or tx_start_p_i;
last_data_byte_p_tmp <= prod_data_lgth_match and tx_byte_request_p;
byte_request_accept_p <= byte_request_accept_p_d2; -- response to wf_tx_serializer request for a byte
byte_request_accept_p <= byte_request_accept_p_d2; -- response to wf_tx_serializer's request
-- for a byte
end architecture struc;
--=================================================================================================
-- architecture end
......
rtl/fmc_masterfip_csr.vhd → rtl/masterfip_wbgen2_csr.vhd
View file @ 86ec47a0
This source diff could not be displayed because it is too large. You can view the blob instead.
rtl/mf_wbgen2_pkg.vhd → rtl/masterfip_wbgen2_pkg.vhd
View file @ 86ec47a0
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC masterFIP core registers
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 10/17/16 12:35:48
-- File : masterfip_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 02/09/17 10:52:07
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -14,12 +14,12 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mrfip_wbgen2_pkg is
package masterfip_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_mrfip_in_registers is record
type t_masterfip_in_registers is record
ds1820_temper_i : std_logic_vector(15 downto 0);
ds1820_id_lsb_i : std_logic_vector(31 downto 0);
ds1820_id_msb_i : std_logic_vector(31 downto 0);
......@@ -31,7 +31,7 @@ package mrfip_wbgen2_pkg is
silen_time_cnt_i : std_logic_vector(30 downto 0);
tx_stat_stop_i : std_logic;
tx_stat_ena_i : std_logic;
tx_stat_curr_byte_indx_i : std_logic_vector(15 downto 0);
tx_stat_curr_byte_indx_i : std_logic_vector(8 downto 0);
fd_wdg_i : std_logic;
fd_cd_i : std_logic;
fd_wdg_tstamp_i : std_logic_vector(31 downto 0);
......@@ -40,7 +40,7 @@ package mrfip_wbgen2_pkg is
rx_stat_pream_ok_i : std_logic;
rx_stat_frame_ok_i : std_logic;
rx_stat_frame_crc_err_i : std_logic;
rx_stat_bytes_num_i : std_logic_vector(15 downto 0);
rx_stat_bytes_num_i : std_logic_vector(8 downto 0);
rx_stat_curr_word_indx_i : std_logic_vector(6 downto 0);
rx_stat_crc_err_cnt_i : std_logic_vector(31 downto 0);
rx_payld_ctrl_i : std_logic_vector(7 downto 0);
......@@ -113,7 +113,7 @@ package mrfip_wbgen2_pkg is
rx_payld_reg67_i : std_logic_vector(31 downto 0);
end record;
constant c_mrfip_in_registers_init_value: t_mrfip_in_registers := (
constant c_masterfip_in_registers_init_value: t_masterfip_in_registers := (
ds1820_temper_i => (others => '0'),
ds1820_id_lsb_i => (others => '0'),
ds1820_id_msb_i => (others => '0'),
......@@ -209,22 +209,21 @@ package mrfip_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_mrfip_out_registers is record
type t_masterfip_out_registers is record
rst_core_o : std_logic;
rst_fd_o : std_logic;
dbg_o : std_logic_vector(31 downto 0);
adc_1v8_shdn_n_o : std_logic;
adc_m5v_shdn_n_o : std_logic;
adc_5v_en_n_o : std_logic;
adc_prim_conn_n_o : std_logic;
adc_sec_conn_n_o : std_logic;
dac_config_value_o : std_logic_vector(15 downto 0);
dac_config_load_o : std_logic;
ext_sync_term_en_o : std_logic;
ext_sync_dir_o : std_logic;
ext_sync_oe_n_o : std_logic;
ext_sync_tst_n_o : std_logic;
ext_sync_p_cnt_rst_o : std_logic;
led_rx_act_o : std_logic;
led_rx_err_o : std_logic;
led_tx_act_o : std_logic;
led_tx_err_o : std_logic;
led_ext_sync_used_o : std_logic;
led_ext_sync_act_o : std_logic;
led_ext_sync_err_o : std_logic;
led_dbg_o : std_logic_vector(23 downto 0);
ext_sync_ctrl_term_en_o : std_logic;
ext_sync_ctrl_dir_o : std_logic;
ext_sync_ctrl_oe_n_o : std_logic;
ext_sync_ctrl_p_cnt_rst_o : std_logic;
macrocyc_lgth_o : std_logic_vector(30 downto 0);
macrocyc_start_o : std_logic;
turnar_lgth_o : std_logic_vector(30 downto 0);
......@@ -233,7 +232,7 @@ package mrfip_wbgen2_pkg is
silen_start_o : std_logic;
tx_ctrl_rst_o : std_logic;
tx_ctrl_start_o : std_logic;
tx_ctrl_bytes_num_o : std_logic_vector(15 downto 0);
tx_ctrl_bytes_num_o : std_logic_vector(8 downto 0);
rx_ctrl_rst_o : std_logic;
tx_payld_ctrl_o : std_logic_vector(7 downto 0);
tx_payld_reg1_o : std_logic_vector(31 downto 0);
......@@ -305,22 +304,21 @@ package mrfip_wbgen2_pkg is
tx_payld_reg67_o : std_logic_vector(31 downto 0);
end record;
constant c_mrfip_out_registers_init_value: t_mrfip_out_registers := (
constant c_masterfip_out_registers_init_value: t_masterfip_out_registers := (
rst_core_o => '0',
rst_fd_o => '0',
dbg_o => (others => '0'),
adc_1v8_shdn_n_o => '0',
adc_m5v_shdn_n_o => '0',
adc_5v_en_n_o => '0',
adc_prim_conn_n_o => '0',
adc_sec_conn_n_o => '0',
dac_config_value_o => (others => '0'),
dac_config_load_o => '0',
ext_sync_term_en_o => '0',
ext_sync_dir_o => '0',
ext_sync_oe_n_o => '0',
ext_sync_tst_n_o => '0',
ext_sync_p_cnt_rst_o => '0',
led_rx_act_o => '0',
led_rx_err_o => '0',
led_tx_act_o => '0',
led_tx_err_o => '0',
led_ext_sync_used_o => '0',
led_ext_sync_act_o => '0',
led_ext_sync_err_o => '0',
led_dbg_o => (others => '0'),
ext_sync_ctrl_term_en_o => '0',
ext_sync_ctrl_dir_o => '0',
ext_sync_ctrl_oe_n_o => '0',
ext_sync_ctrl_p_cnt_rst_o => '0',
macrocyc_lgth_o => (others => '0'),
macrocyc_start_o => '0',
turnar_lgth_o => (others => '0'),
......@@ -400,12 +398,12 @@ package mrfip_wbgen2_pkg is
tx_payld_reg66_o => (others => '0'),
tx_payld_reg67_o => (others => '0')
);
function "or" (left, right: t_mrfip_in_registers) return t_mrfip_in_registers;
function "or" (left, right: t_masterfip_in_registers) return t_masterfip_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body mrfip_wbgen2_pkg is
package body masterfip_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
......@@ -426,8 +424,8 @@ end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_mrfip_in_registers) return t_mrfip_in_registers is
variable tmp: t_mrfip_in_registers;
function "or" (left, right: t_masterfip_in_registers) return t_masterfip_in_registers is
variable tmp: t_masterfip_in_registers;
begin
tmp.ds1820_temper_i := f_x_to_zero(left.ds1820_temper_i) or f_x_to_zero(right.ds1820_temper_i);
tmp.ds1820_id_lsb_i := f_x_to_zero(left.ds1820_id_lsb_i) or f_x_to_zero(right.ds1820_id_lsb_i);
......
rtl/wbgen/fmc_masterfip_csr.wb → rtl/wbgen/masterfip_csr.wb
View file @ 86ec47a0
peripheral {
name = "FMC masterFIP core registers";
description = "Wishbone slave for FMC masterFIP core";
hdl_entity = "fmc_masterfip_csr";
hdl_entity = "masterfip_wbgen2_csr";
prefix = "mrfip";
prefix = "masterfip";
-------------------------------------------------------------------------------
-- reset --
-------------------------------------------------------------------------------
-- Note that for html readability, some of the lines are longer than 100 characters.
----------------------------------------------------------------------------------------------------
-- RESET --
----------------------------------------------------------------------------------------------------
reg {
name = "rst";
prefix = "rst";
......@@ -15,52 +17,106 @@ peripheral {
field {
name = "reset of the masterFIP core";
description = "write 1: generates a 1-tick-long (10ns) masterFIP core reset;\
note: there is no need to clear the field before writing another '1'";
description = "write 1: generates a 1-clk-tick-long (10ns) masterFIP core reset;\
note: there is no need to clear the bit before writing another '1'";
type = MONOSTABLE;
prefix = "core";
};
field {
name = "reset of the fieldrive chip";
description = "write 1: to generate a fieldrive reset;\
upon writing, the masterFIP_core generates a 1-WorldFIP-tick-long FD RSTN;\
note: there is no need to clear the field before writing another '1'";
name = "reset of the FielDrive chip";
description = "write 1: to generate a FielDrive reset;\
upon writing, the fmc_masterFIP_core generates a 1-WorldFIP-clk-tick-long FD RSTN;\
note: there is no need to clear the bit before writing another '1'";
type = MONOSTABLE;
prefix = "fd";
};
};
-------------------------------------------------------------------------------
-- identification --
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- CORE IDENTIFIER --
----------------------------------------------------------------------------------------------------
reg {
name = "id";
description = "constant identification value: COOOFFEE";
name = "core id";
description = "constant identification value: C000FFEE";
prefix = "id";
field {
name = "an id value";
description = "equal to <code>0xc000ffee</code> for the moment";
description = "equal to <code>0xC000FFEE</code>";
size = 32;
type = CONSTANT;
value = 0xc000ffee;
value = 0xC000FFEE;
};
};
-------------------------------------------------------------------------------
-- debugging --
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- LEDs and DEBUGGING --
----------------------------------------------------------------------------------------------------
reg {
name = "dbg";
description = "for debugging purposes; used to pass signals to front panel LEDs";
prefix = "dbg";
name = "leds and debug";
description = "managing of the front panel LEDs of the masterFIP mezzanine;\
note that if an application is not using synchronisation through the LEMO EXT SYNC,\
the EXT_SYNC_ACT and EXT_SYNC_ERR LEDs will be both switched off.\
Note also that the remaining bits of this register are used for debugging purposes";
prefix = "led";
field {
name = "debugging";
size = 32;
name = "rx act green led";
prefix = "rx_act";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "rx err red led";
prefix = "rx_err";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "tx act green led";
prefix = "tx_act";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "tx err red led";
prefix = "tx_err";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "write 1 to indicate that the ext sync is used";
prefix = "ext_sync_used";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ext sync act green led";
prefix = "ext_sync_act";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ext sync err red led";
prefix = "ext_sync_err";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "dbg";
prefix = "dbg";
size = 24;
align = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -68,11 +124,11 @@ peripheral {
};
-------------------------------------------------------------------------------
-- one wire --
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- DS1820 ONE WIRE --
----------------------------------------------------------------------------------------------------
reg {
name = "mezzanine temperature";
name = "fmc temperature";
description = "raw temperature data from the one wire DS18B20U+;\
the register is 2-bytes long; it translates to oC as follows:\
temp = ((byte1 << 8) | byte0) / 16.0";
......@@ -88,7 +144,7 @@ peripheral {
};
reg {
name = "mezzanine unique id lsb";
name = "fmc unique id lsb";
description = "id (lsb) read from the one wire DS18B20U+";
prefix = "ds1820_id_lsb";
......@@ -102,7 +158,7 @@ peripheral {
};
reg {
name = "mezzanine unique id msb";
name = "fmc unique id msb";
description = "id (msb) read from the one wire DS18B20U+";
prefix = "ds1820_id_msb";
......@@ -116,104 +172,12 @@ peripheral {
};
-------------------------------------------------------------------------------
-- ADC power supplies --
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- EXT SYNC PULSE --
----------------------------------------------------------------------------------------------------
reg {
name = "adc";
prefix = "adc";
field {
name = "1v8_shdn_n";
prefix = "1v8_shdn_n";
description = "write 0: disable the ADC 1V8\
write 1: enable the ADC 1V8";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "m5v_shdn_n";
prefix = "m5v_shdn_n";
description = "write 0: disable the ADC M5V\
write 1: enable the ADC M5V";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "5v_en_n";
prefix = "5v_en_n";
description = "write 0: enable the ADC 5V\
write 1: disable the ADC 5V";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "prim_conn_n";
prefix = "prim_conn_n";
description = "write 0: connect the ADC to the primary side of the FieldTR (bus side)\
write 1: disconnect the ADC from the primary side of the FieldTR (bus side)";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "sec_conn_n";
prefix = "sec_conn_n";
description = "write 0: connect the ADC to the secondary side of the FieldTR (FielDrive side)\
write 1: disconnect the ADC from the secondary side of the FieldTR (FielDrive side)";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-------------------------------------------------------------------------------
-- DAC configuration --
-------------------------------------------------------------------------------
reg {
name = "dac";
prefix = "dac_config";
field {
name = "value";
prefix = "value";
description = "Vout= Vref (value/ 65536)\
For the DAC middle range: value = 32768 = 0x8000";
type = SLV;
size = 16;
-- add reset_value = "0x8000";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "load";
prefix = "load";
description = "write 1: loads the dac with the dac_value;\
note: there is no need to clear the field before writing another '1'";
type = MONOSTABLE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-------------------------------------------------------------------------------
-- external synch --
-------------------------------------------------------------------------------
reg {
name = "ext sync";
prefix = "ext_sync";
name = "ext sync ctrl";
prefix = "ext_sync_ctrl";
field {
name = "termination enable";
......@@ -229,7 +193,8 @@ peripheral {
name = "transceiver direction";
prefix = "dir";
description = "write 0: normal operation\
write 1: test mode where a pulse from the FPGA can be output to the front panel LEMO connector";
write 1: test mode where a pulse from the FPGA can be output to the front panel LEMO connector\
WARNING: this bit is hard-wired in the HDL top to 0";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -239,21 +204,13 @@ peripheral {
name = "transceiver output enable negative logic";
prefix = "oe_n";
description = "write 0: normal operation, the external sync pulse arrives to the FPGA\
write 1: the external sync pulse does not arrive to the FPGA";
write 1: the external sync pulse does not arrive to the FPGA\
WARNING: this bit is hard-wired in the HDL top to 0";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "test pulse";
prefix = "tst_n";
description = "emulate a pulse";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "pulses counter reset";
prefix = "p_cnt_rst";
......@@ -271,7 +228,8 @@ peripheral {
field {
name = "ext_sync_p_cnt";
description = "number of ext sync pulses";
description = "number of ext sync pulses since the application startup OR a rst_core OR a ext_sync_p_cnt_rst;\
for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -280,19 +238,19 @@ peripheral {
};
-------------------------------------------------------------------------------
-- speed configuration from the board --
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- SPEED CONFIG FROM THE FMC MEZZ --
----------------------------------------------------------------------------------------------------
reg {
name = "bus speed";
prefix = "speed";
field {
name = "speed";
description = "WorldFIP speed: 00: 31.25Kbps\
01: 1Mbps\
10: 2.5 Mbps\
11: 5 Mbps";
name = "WorldFIP speed, hard-wired on the FMC";
description = " 00: 31.25Kbps\
01: 1Mbps\
10: 2.5 Mbps\
11: 5 Mbps";
type = SLV;
size = 2;
access_bus = READ_ONLY;
......@@ -301,9 +259,9 @@ peripheral {
};
-------------------------------------------------------------------------------
-- counters --
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- MACROCYCLE TURNAROUND SILENCE TIME COUNTERS --
----------------------------------------------------------------------------------------------------
reg {
name = "macrocycle lgth";
prefix = "macrocyc";
......@@ -319,8 +277,9 @@ peripheral {
};
field {
name = "macrocycle cnt start";
description = "write 1: initiates the counting of the macrocycle counter\
note: there is no need to clear the field before writing another '1'";
description = "write 1: initiates the counting of the macrocycle counter;\
the counter also automatically starts counting upon the arrival of an ext_sync pulse\
note: there is no need to clear the bit before writing another '1'";
prefix = "start";
type = MONOSTABLE;
access_bus = READ_WRITE;
......@@ -328,13 +287,44 @@ peripheral {
};
};
reg {
name = "macrocycle time cnt";
prefix = "macrocyc_time_cnt";
field {
name = "macrocycle time counter";
description = "current value of the macrocycle time counter;\
the counter top value is set through the register macrocycle lgth and it counts down;\
it is reloaded upon the activation of the macrocycle_cnt_start register bit OR automatically upon the arrival of an ext_sync pulse.";
type = SLV;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "macrocycles number cnt";
prefix = "macrocyc_num_cnt";
field {
name = "number of macrocycles";
description = "amount of macrocycles that have been counted since the application startup OR a rst_core;\
for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "turnaround lgth";
prefix = "turnar";
field {
name = "turnaround time";
description = "turnaround time (i.e. time between two frames sent by the masterFIP) in number of 10ns-clk-ticks";
description = "turnaround time (i.e. time to wait after reception/transmission of a frame and before transmitting a new frame) in number of 10ns-clk-ticks";
prefix = "lgth";
type = SLV;
size = 31;
......@@ -343,8 +333,10 @@ peripheral {
};
field {
name = "turnaround cnt start";
description = "write 1: initiates the counting of the turnaround counter\
note: there is no need to clear the field before writing another '1'";
description = "write 1: initiates the counting of the turnaround counter;\
the counter also automatically starts counting upon the end of a frame serialization (tx stop)\
OR upon the end of a frame deserialization (rx_frame_ok OR rx_frame_crc_error).\
note: there is no need to clear the bit before writing another '1'";
prefix = "start";
type = MONOSTABLE;
access_bus = READ_WRITE;
......@@ -352,6 +344,23 @@ peripheral {
};
};
reg {
name = "turnaround time cnt";
prefix = "turnar_time_cnt";
field {
name = "turnaround time counter";
description = "current value of the turnaround time counter;\
the counter top value is set through the register turnar_lgth and it counts down;\
it is reloaded upon the activation of the turnar_cnt_start OR automatically upon the end of a\
frame serialization (tx stop) OR upon the end of a frame deserialization (rx frame ok OR rx frame crc error).";
type = SLV;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "silence lgth";
prefix = "silen";
......@@ -367,66 +376,27 @@ peripheral {
};
field {
name = "silence cnt start";
description = "initiates the counting of the silence counter\
note: there is no need to clear the field before writing another '1'";
description = "initiates the counting of the silence counter;\
the counter also automatically starts counting upon the end of a frame serialization (tx stop)\
OR upon the end of a frame deserialization (rx frame ok OR rx frame crc error for the case of RP_FIN).\
note: there is no need to clear the bit before writing another '1'";
prefix = "start";
type = MONOSTABLE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "macrocycle time cnt";
prefix = "macrocyc_time_cnt";
field {
name = "macrocycle time counter";
description = "current value of the macrocycle time counter";
type = SLV;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "macrocycles number cnt";
prefix = "macrocyc_num_cnt";
field {
name = "number of macrocycles";
description = "amount of macrocycles that have been counted so far";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "turnaround time cnt";
prefix = "turnar_time_cnt";
field {
name = "turnaround time counter";
description = "current value of the turnaround time counter";
type = SLV;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "silence time cnt";
prefix = "silen_time_cnt";
field {
name = "silence time counter";
description = "current value of the silence time counter";
description = "current value of the silence time counter\
the counter top value is set through the register silen_lgth and it counts down;\
it is reloaded upon the activation of the silen_cnt_start OR automatically upon the end of a\
frame serialization (tx stop) OR upon the end of a frame deserialization (rx frame ok OR rx frame crc error for the case of RP_FIN).";
type = SLV;
size = 31;
access_bus = READ_ONLY;
......@@ -435,17 +405,17 @@ peripheral {
};
-------------------------------------------------------------------------------
-- serializer ctrl --
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- TX CTRL --
----------------------------------------------------------------------------------------------------
reg {
name = "tx ctrl";
prefix = "tx_ctrl";
field {
name = "tx rst";
description = "write 1: generates a 1-tick-long reset to the serializer\
note: there is no need to clear the field before writing another '1'";
description = "write 1: generates a 1-clk-tick-long reset to the serializer;\
note: there is no need to clear the bit before writing another '1'";
prefix = "rst";
type = MONOSTABLE;
access_bus = READ_WRITE;
......@@ -454,10 +424,10 @@ peripheral {
field {
name = "tx strt";
description = "write 1: initiates the serializer to send a frame of tx_ctrl_bytes_num payload bytes;\
description = "write 1: triggers the serializer to send a frame of tx_ctrl_bytes_num payload bytes;\
the bytes are retrieved one-by-one by the registers: tx_payld_ctrl, tx_payld_reg1..tx_payld_reg67;\
the bytes: FSS, CRC and FES are generated automatically by the serializer.\
note: there is no need to clear the field before writing another '1'";
note: there is no need to clear the bit before writing another '1'";
prefix = "start";
type = MONOSTABLE;
access_bus = READ_WRITE;
......@@ -467,12 +437,12 @@ peripheral {
field {
name = "tx number of bytes";
description = "number of bytes to serialize; the number should include all the bytes in the Control and Data fields\
of a frame and not include the bytes in the Preamble, CRC, Postamble fields; the masterFIP_core samples\
this number upon the tx_strt; note that for the max supported WorldFIP frame, which is a message of\
of a frame and not include the bytes in the Preamble(FSS), CRC, Postamble(FES) fields; the fmc_masterFIP_core\
samples this number upon the tx_strt; note that for the max supported WorldFIP frame, which is a message of\
256 Data bytes, the number of bytes to serialize = 263 (Control byte+6 address bytes+256 Data bytes)";
prefix = "bytes_num";
type = SLV;
size = 16;
size = 9;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -480,17 +450,17 @@ peripheral {
};
-------------------------------------------------------------------------------
-- serializer status --
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- TX STATUS --
----------------------------------------------------------------------------------------------------
reg {
name = "tx status";
prefix = "tx_stat";
field {
name = "tx ended";
description = "indication that the serializer finished the delivery of a frame\
the bit stays active until a rstn_core or a tx_ctrl_rst or a tx_ctrl_strt";
description = "indication that the serializer finished the delivery of a frame;\
the bit stays active until a rst_core OR a tx_ctrl_rst OR a tx_ctrl_strt";
prefix = "stop";
type = BIT;
access_bus = READ_ONLY;
......@@ -499,9 +469,9 @@ peripheral {
field {
name = "tx enable";
description = "fieldrive fd_txena signal;\
description = "FielDrive fd_txena signal;\
read 0: masterFIP serializer is inactive\
read 1: masterFIP serializer is active putting bits to the bus";
read 1: masterFIP serializer is active transmitting bits on the bus";
prefix = "ena";
type = BIT;
align = 8;
......@@ -512,28 +482,29 @@ peripheral {
field {
name = "tx status current byte index";
description = "index of the current byte being serialized;\
the counting starts from 0 after the preamble...";
the counting starts from 0 after the Preamble(FSS) (index 0 is for the Control byte)\
and counts up to 262 for the max frame (counting stops before the CRC bytes)";
prefix = "curr_byte_indx";
type = SLV;
size = 16;
size = 9;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-------------------------------------------------------------------------------
-- fieldrive status signals --
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- FielDrive TXER, WDGN, CDN --
----------------------------------------------------------------------------------------------------
reg {
name = "fieldrive wdgn, cdn";
name = "FielDrive wdgn, cdn";
prefix = "fd";
field {
name = "fieldrive watchdog";
description = "read 1: the fd_wdgn has been activated\
name = "FielDrive watchdog";
description = "read 1: the fd_wdgn is active which means that a transmission >1024 bytes-long has been detected\
read 0: no problemo\
Note that if triggered, the fd_wdgn stays active until a fd_rstn";
Note that the fd_wdgn stays active until a FielDrive reset rst_fd";
prefix = "wdg";
type = BIT;
access_bus = READ_ONLY;
......@@ -541,7 +512,7 @@ peripheral {
};
field {
name = "fieldrive carrier detect";
name = "FielDrive carrier detect";
description = "read 1: carrier detect active\
read 0: no bus traffic";
prefix = "cd";
......@@ -552,15 +523,13 @@ peripheral {
};
reg {
name = "fieldrive wdg timestamp";
name = "FielDrive wdg timestamp";
prefix = "fd_wdg_tstamp";
field {
name = "fd_wdgn_tstamp";
description = "timestamp of the moment in the macrocycle when the fd_wdg\
was activated.\
The field is automatically cleared upon a new macrocycle or\
upon a rstn_fd or rstn_core";
description = "timestamp of the moment in the macrocycle (macrocycle_cnt) when the fd_wdg activation (rising edge) was detected.\
The field is automatically cleared upon a rst_fd OR rst_core";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -570,15 +539,15 @@ peripheral {
reg {
name = "fieldrive txer cnt";
name = "FielDrive txer cnt";
prefix = "fd_txer_cnt";
field {
name = "fd_txer_cnt";
description = "counter of the number of fd_txer rising edges that appear in this\
current macrocycle.\
The field is automatically cleared upon a new macrocycle or\
upon a rstn_fd or rstn_core";
description = "counter of the number of fd_txer rising edges that appear in the current macrocycle.\
The field is automatically cleared upon a new macrocycle OR upon a rst_fd OR rst_core.\
Note that a fd_txer indicates underload/overload of the bus (like for example when the\
WorldFIP cable has been disconnected) OR transmission without a Manchester-edge-detection after the duration of 4 bits.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -588,15 +557,13 @@ peripheral {
reg {
name = "fieldrive txer tstamp";
name = "FielDrive txer tstamp";
prefix = "fd_txer_tstamp";
field {
name = "fd_txer_tstamp";
description = "timestamp of the last moment in the macrocycle when the fd_txer\
was activated.\
The field is automatically cleared upon a new macrocycle or\
upon a rstn_fd or rstn_core";
description = "timestamp of the last moment in the macrocycle when the fd_txer was activated.\
The field is automatically cleared upon a new macrocycle OR upon a rst_fd OR rst_core";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -604,9 +571,9 @@ peripheral {
};
};
-------------------------------------------------------------------------------
-- tx ctrl --
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- RX CTRL --
----------------------------------------------------------------------------------------------------
reg {
name = "rx ctrl";
prefix = "rx_ctrl";
......@@ -614,9 +581,9 @@ peripheral {
field {
name = "rx rst";
description = "write 1: generates a 1-tick-long reset to the deserializer\
note: there is no need to clear the field before writing another '1'\
note: the deserializer is automatically hw-reset when the serializer is active";
description = "write 1: generates a 1-clk-tick-long reset to the deserializer\
note: there is no need to clear the bit before writing another '1'\
note: the deserializer is automatically hw-reset when the serializer is active.";
prefix = "rst";
type = MONOSTABLE;
......@@ -625,19 +592,18 @@ peripheral {
};
};
-------------------------------------------------------------------------------
-- rx status --
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- RX STATUS --
----------------------------------------------------------------------------------------------------
reg {
name = "rx status";
prefix = "rx_stat";
field {
name = "rx preamble detected";
description = "indication that the deserializer has detected a preamble;\
the bit stays active until a reset of the deserializer (this takes place\
automatically upon the activation of the serializer, or upon a rx_ctrl_rst\
or upon a core_rstn)";
name = "rx Preamble(FSS) detected";
description = "indication that the deserializer has detected a Preamble(FSS);\
the bit stays active until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core)";
prefix = "pream_ok";
type = BIT;
access_bus = READ_ONLY;
......@@ -647,10 +613,12 @@ peripheral {
field {
name = "rx frame ok";
description = "indication that the deserializer has finished with the reception of a complete frame;\
the preamble, CRC and postambe of the frame are all ok\
the bit stays high until a reset of the deserializer (this takes place\
automatically upon the activation of the serializer, or upon a rx_ctrl_rst\
or upon a rstn_core)";
the Preamble(FSS), CRC and Postambe(FES) of the frame are all ok.\
The bit stays high until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core).\
Upon the activation of the rx_frame_ok the processor should read the bytes_num register\
and then the corresponding amount of rx_payld_regs. The content of these registers remains stable\
until a reset of the deserializer OR a new rx_frame_ok; this is at minimum 23.2 us (i.e. (min node turnaround timee = 4 us) + (RP_FIN duration = 19.2 us)).";
prefix = "frame_ok";
type = BIT;
access_bus = READ_ONLY;
......@@ -659,9 +627,9 @@ peripheral {
field {
name = "rx frame crc error";
description = "indication that the deserializer has detected a frame with CRC error\
the bit stays high until a reset of the deserializer (this takes place\
automatically upon the activation of the serializer, or upon a rx_rst)";
description = "indication that the deserializer has detected a frame with CRC error;\
The bit stays high until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core).";
prefix = "frame_crc_err";
type = BIT;
access_bus = READ_ONLY;
......@@ -670,13 +638,14 @@ peripheral {
field {
name = "rx number of payload bytes";
description = "number of payload bytes that have been received by the deserializer\
upon the rx_frame_ok activation.\
description = "number of payload bytes that have been received by the deserializer upon the rx_frame_ok activation.\
The counter includes all the bytes that come after the Control byte and before the CRC bytes.\
note that for the max WorldFIP frame size = 262 bytes (without preamble, Control, CRC, postamble)";
note that for the max WorldFIP frame size, the number of payload bytes = 262 bytes (without Preamble, Control, CRC, Postamble).\
The register keeps its value until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core).";
prefix = "bytes_num";
type = SLV;
size = 16;
size = 9;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
......@@ -690,12 +659,13 @@ peripheral {
field {
name = "current word index";
description = "index of the current 32-bit-word being deserialized;\
word 1: LSB is the Control byte; the other 3 bytes are to be ignored\
word 2: contains the first 4 payload bytes..etc\
The max frame size is 66 words.\
The last word may also include CRC bytes;\
for that, upon the rx_frame_ok, the rx_bytes_num indicates the\
exact number of payload bytes to be read";
Note that in word 1: LSB is the Control byte; the other 3 bytes are to be ignored\
then word 2: contains the first 4 payload bytes..etc\
The max frame size is 67 words (including the word for the Control byte).\
The last word may also include CRC bytes; for that, upon the rx_frame_ok,\
the rx_bytes_num indicates the exact number of payload bytes to be read;\
The register keeps its value until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core).";
type = SLV;
size = 7;
access_bus = READ_ONLY;
......@@ -704,12 +674,12 @@ peripheral {
};
reg {
name = "rx number of frames with CRC error";
name = "rx num of frames with CRC error";
prefix = "rx_stat_crc_err_cnt";
field {
name = "rx number of frames with CRC error";
description = "number of frames with CRC error since the startup or a core_rstn";
description = "number of frames with CRC error since the application startup OR a rst_core";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -717,9 +687,9 @@ peripheral {
};
};
-------------------------------------------------------------------------------
-- rx payload bytes --
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- RX FRAME PAYLOAD --
----------------------------------------------------------------------------------------------------
reg {
name = "rx payload ctrl byte";
......@@ -1741,9 +1711,9 @@ peripheral {
};
};
-------------------------------------------------------------------------------
-- tx payload --
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- TX FRAME PAYLOAD --
----------------------------------------------------------------------------------------------------
reg {
name = "tx ctrl byte";
......
rtl/wbgen/fmc_masterfip_csr.h → rtl/wbgen/masterfip_wbgen2_csr.h
View file @ 86ec47a0
/*
Register definitions for slave core: FMC masterFIP core registers
* File : fmc_masterfip_csr.h
* Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
* Created : 10/17/16 12:35:48
* File : masterfip_wbgen2_csr.h
* Author : auto-generated by wbgen2 from masterfip_csr.wb
* Created : 02/09/17 10:52:07
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_FMC_MASTERFIP_CSR_WB
#define __WBGEN2_REGDEFS_FMC_MASTERFIP_CSR_WB
#ifndef __WBGEN2_REGDEFS_MASTERFIP_CSR_WB
#define __WBGEN2_REGDEFS_MASTERFIP_CSR_WB
#include <inttypes.h>
......@@ -34,65 +34,61 @@
/* definitions for register: rst */
/* definitions for field: reset of the masterFIP core in reg: rst */
#define MRFIP_RST_CORE WBGEN2_GEN_MASK(0, 1)
#define MASTERFIP_RST_CORE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: reset of the fieldrive chip in reg: rst */
#define MRFIP_RST_FD WBGEN2_GEN_MASK(1, 1)
/* definitions for field: reset of the FielDrive chip in reg: rst */
#define MASTERFIP_RST_FD WBGEN2_GEN_MASK(1, 1)
/* definitions for register: id */
/* definitions for register: core id */
/* definitions for register: dbg */
/* definitions for register: leds and debug */
/* definitions for register: mezzanine temperature */
/* definitions for field: rx act green led in reg: leds and debug */
#define MASTERFIP_LED_RX_ACT WBGEN2_GEN_MASK(0, 1)
/* definitions for register: mezzanine unique id lsb */
/* definitions for field: rx err red led in reg: leds and debug */
#define MASTERFIP_LED_RX_ERR WBGEN2_GEN_MASK(1, 1)
/* definitions for register: mezzanine unique id msb */
/* definitions for field: tx act green led in reg: leds and debug */
#define MASTERFIP_LED_TX_ACT WBGEN2_GEN_MASK(2, 1)
/* definitions for register: adc */
/* definitions for field: tx err red led in reg: leds and debug */
#define MASTERFIP_LED_TX_ERR WBGEN2_GEN_MASK(3, 1)
/* definitions for field: 1v8_shdn_n in reg: adc */
#define MRFIP_ADC_1V8_SHDN_N WBGEN2_GEN_MASK(0, 1)
/* definitions for field: write 1 to indicate that the ext sync is used in reg: leds and debug */
#define MASTERFIP_LED_EXT_SYNC_USED WBGEN2_GEN_MASK(4, 1)
/* definitions for field: m5v_shdn_n in reg: adc */
#define MRFIP_ADC_M5V_SHDN_N WBGEN2_GEN_MASK(1, 1)
/* definitions for field: ext sync act green led in reg: leds and debug */
#define MASTERFIP_LED_EXT_SYNC_ACT WBGEN2_GEN_MASK(5, 1)
/* definitions for field: 5v_en_n in reg: adc */
#define MRFIP_ADC_5V_EN_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: ext sync err red led in reg: leds and debug */
#define MASTERFIP_LED_EXT_SYNC_ERR WBGEN2_GEN_MASK(6, 1)
/* definitions for field: prim_conn_n in reg: adc */
#define MRFIP_ADC_PRIM_CONN_N WBGEN2_GEN_MASK(8, 1)
/* definitions for field: dbg in reg: leds and debug */
#define MASTERFIP_LED_DBG_MASK WBGEN2_GEN_MASK(8, 24)
#define MASTERFIP_LED_DBG_SHIFT 8
#define MASTERFIP_LED_DBG_W(value) WBGEN2_GEN_WRITE(value, 8, 24)
#define MASTERFIP_LED_DBG_R(reg) WBGEN2_GEN_READ(reg, 8, 24)
/* definitions for field: sec_conn_n in reg: adc */
#define MRFIP_ADC_SEC_CONN_N WBGEN2_GEN_MASK(9, 1)
/* definitions for register: fmc temperature */
/* definitions for register: dac */
/* definitions for register: fmc unique id lsb */
/* definitions for field: value in reg: dac */
#define MRFIP_DAC_CONFIG_VALUE_MASK WBGEN2_GEN_MASK(0, 16)
#define MRFIP_DAC_CONFIG_VALUE_SHIFT 0
#define MRFIP_DAC_CONFIG_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define MRFIP_DAC_CONFIG_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: fmc unique id msb */
/* definitions for field: load in reg: dac */
#define MRFIP_DAC_CONFIG_LOAD WBGEN2_GEN_MASK(16, 1)
/* definitions for register: ext sync ctrl */
/* definitions for register: ext sync */
/* definitions for field: termination enable in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_TERM_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: termination enable in reg: ext sync */
#define MRFIP_EXT_SYNC_TERM_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: transceiver direction in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_DIR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: transceiver direction in reg: ext sync */
#define MRFIP_EXT_SYNC_DIR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: transceiver output enable negative logic in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_OE_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: transceiver output enable negative logic in reg: ext sync */
#define MRFIP_EXT_SYNC_OE_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: test pulse in reg: ext sync */
#define MRFIP_EXT_SYNC_TST_N WBGEN2_GEN_MASK(3, 1)
/* definitions for field: pulses counter reset in reg: ext sync */
#define MRFIP_EXT_SYNC_P_CNT_RST WBGEN2_GEN_MASK(8, 1)
/* definitions for field: pulses counter reset in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_P_CNT_RST WBGEN2_GEN_MASK(8, 1)
/* definitions for register: ext sync pulses cnt */
......@@ -101,111 +97,111 @@
/* definitions for register: macrocycle lgth */
/* definitions for field: macrocycle lgth in reg: macrocycle lgth */
#define MRFIP_MACROCYC_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MRFIP_MACROCYC_LGTH_SHIFT 0
#define MRFIP_MACROCYC_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MRFIP_MACROCYC_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
#define MASTERFIP_MACROCYC_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MASTERFIP_MACROCYC_LGTH_SHIFT 0
#define MASTERFIP_MACROCYC_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MASTERFIP_MACROCYC_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: macrocycle cnt start in reg: macrocycle lgth */
#define MRFIP_MACROCYC_START WBGEN2_GEN_MASK(31, 1)
#define MASTERFIP_MACROCYC_START WBGEN2_GEN_MASK(31, 1)
/* definitions for register: macrocycle time cnt */
/* definitions for register: macrocycles number cnt */
/* definitions for register: turnaround lgth */
/* definitions for field: turnaround time in reg: turnaround lgth */
#define MRFIP_TURNAR_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MRFIP_TURNAR_LGTH_SHIFT 0
#define MRFIP_TURNAR_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MRFIP_TURNAR_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
#define MASTERFIP_TURNAR_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MASTERFIP_TURNAR_LGTH_SHIFT 0
#define MASTERFIP_TURNAR_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MASTERFIP_TURNAR_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: turnaround cnt start in reg: turnaround lgth */
#define MRFIP_TURNAR_START WBGEN2_GEN_MASK(31, 1)
#define MASTERFIP_TURNAR_START WBGEN2_GEN_MASK(31, 1)
/* definitions for register: turnaround time cnt */
/* definitions for register: silence lgth */
/* definitions for field: silence time in reg: silence lgth */
#define MRFIP_SILEN_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MRFIP_SILEN_LGTH_SHIFT 0
#define MRFIP_SILEN_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MRFIP_SILEN_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
#define MASTERFIP_SILEN_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MASTERFIP_SILEN_LGTH_SHIFT 0
#define MASTERFIP_SILEN_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MASTERFIP_SILEN_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: silence cnt start in reg: silence lgth */
#define MRFIP_SILEN_START WBGEN2_GEN_MASK(31, 1)
/* definitions for register: macrocycle time cnt */
/* definitions for register: macrocycles number cnt */
/* definitions for register: turnaround time cnt */
#define MASTERFIP_SILEN_START WBGEN2_GEN_MASK(31, 1)
/* definitions for register: silence time cnt */
/* definitions for register: tx ctrl */
/* definitions for field: tx rst in reg: tx ctrl */
#define MRFIP_TX_CTRL_RST WBGEN2_GEN_MASK(0, 1)
#define MASTERFIP_TX_CTRL_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for field: tx strt in reg: tx ctrl */
#define MRFIP_TX_CTRL_START WBGEN2_GEN_MASK(1, 1)
#define MASTERFIP_TX_CTRL_START WBGEN2_GEN_MASK(1, 1)
/* definitions for field: tx number of bytes in reg: tx ctrl */
#define MRFIP_TX_CTRL_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MRFIP_TX_CTRL_BYTES_NUM_SHIFT 8
#define MRFIP_TX_CTRL_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MRFIP_TX_CTRL_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
#define MASTERFIP_TX_CTRL_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 9)
#define MASTERFIP_TX_CTRL_BYTES_NUM_SHIFT 8
#define MASTERFIP_TX_CTRL_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 9)
#define MASTERFIP_TX_CTRL_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 9)
/* definitions for register: tx status */
/* definitions for field: tx ended in reg: tx status */
#define MRFIP_TX_STAT_STOP WBGEN2_GEN_MASK(0, 1)
#define MASTERFIP_TX_STAT_STOP WBGEN2_GEN_MASK(0, 1)
/* definitions for field: tx enable in reg: tx status */
#define MRFIP_TX_STAT_ENA WBGEN2_GEN_MASK(8, 1)
#define MASTERFIP_TX_STAT_ENA WBGEN2_GEN_MASK(8, 1)
/* definitions for field: tx status current byte index in reg: tx status */
#define MRFIP_TX_STAT_CURR_BYTE_INDX_MASK WBGEN2_GEN_MASK(9, 16)
#define MRFIP_TX_STAT_CURR_BYTE_INDX_SHIFT 9
#define MRFIP_TX_STAT_CURR_BYTE_INDX_W(value) WBGEN2_GEN_WRITE(value, 9, 16)
#define MRFIP_TX_STAT_CURR_BYTE_INDX_R(reg) WBGEN2_GEN_READ(reg, 9, 16)
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_MASK WBGEN2_GEN_MASK(9, 9)
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_SHIFT 9
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_W(value) WBGEN2_GEN_WRITE(value, 9, 9)
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_R(reg) WBGEN2_GEN_READ(reg, 9, 9)
/* definitions for register: fieldrive wdgn, cdn */
/* definitions for register: FielDrive wdgn, cdn */
/* definitions for field: fieldrive watchdog in reg: fieldrive wdgn, cdn */
#define MRFIP_FD_WDG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FielDrive watchdog in reg: FielDrive wdgn, cdn */
#define MASTERFIP_FD_WDG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: fieldrive carrier detect in reg: fieldrive wdgn, cdn */
#define MRFIP_FD_CD WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FielDrive carrier detect in reg: FielDrive wdgn, cdn */
#define MASTERFIP_FD_CD WBGEN2_GEN_MASK(1, 1)
/* definitions for register: fieldrive wdg timestamp */
/* definitions for register: FielDrive wdg timestamp */
/* definitions for register: fieldrive txer cnt */
/* definitions for register: FielDrive txer cnt */
/* definitions for register: fieldrive txer tstamp */
/* definitions for register: FielDrive txer tstamp */
/* definitions for register: rx ctrl */
/* definitions for field: rx rst in reg: rx ctrl */
#define MRFIP_RX_CTRL_RST WBGEN2_GEN_MASK(0, 1)
#define MASTERFIP_RX_CTRL_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for register: rx status */
/* definitions for field: rx preamble detected in reg: rx status */
#define MRFIP_RX_STAT_PREAM_OK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: rx Preamble(FSS) detected in reg: rx status */
#define MASTERFIP_RX_STAT_PREAM_OK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: rx frame ok in reg: rx status */
#define MRFIP_RX_STAT_FRAME_OK WBGEN2_GEN_MASK(1, 1)
#define MASTERFIP_RX_STAT_FRAME_OK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: rx frame crc error in reg: rx status */
#define MRFIP_RX_STAT_FRAME_CRC_ERR WBGEN2_GEN_MASK(2, 1)
#define MASTERFIP_RX_STAT_FRAME_CRC_ERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: rx number of payload bytes in reg: rx status */
#define MRFIP_RX_STAT_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MRFIP_RX_STAT_BYTES_NUM_SHIFT 8
#define MRFIP_RX_STAT_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MRFIP_RX_STAT_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
#define MASTERFIP_RX_STAT_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 9)
#define MASTERFIP_RX_STAT_BYTES_NUM_SHIFT 8
#define MASTERFIP_RX_STAT_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 9)
#define MASTERFIP_RX_STAT_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 9)
/* definitions for register: rx current word index */
/* definitions for register: rx number of frames with CRC error */
/* definitions for register: rx num of frames with CRC error */
/* definitions for register: rx payload ctrl byte */
......@@ -479,331 +475,327 @@
/* definitions for register: tx payload reg67 */
/* [0x0]: REG rst */
#define MRFIP_REG_RST 0x00000000
/* [0x4]: REG id */
#define MRFIP_REG_ID 0x00000004
/* [0x8]: REG dbg */
#define MRFIP_REG_DBG 0x00000008
/* [0xc]: REG mezzanine temperature */
#define MRFIP_REG_DS1820_TEMPER 0x0000000c
/* [0x10]: REG mezzanine unique id lsb */
#define MRFIP_REG_DS1820_ID_LSB 0x00000010
/* [0x14]: REG mezzanine unique id msb */
#define MRFIP_REG_DS1820_ID_MSB 0x00000014
/* [0x18]: REG adc */
#define MRFIP_REG_ADC 0x00000018
/* [0x1c]: REG dac */
#define MRFIP_REG_DAC_CONFIG 0x0000001c
/* [0x20]: REG ext sync */
#define MRFIP_REG_EXT_SYNC 0x00000020
/* [0x24]: REG ext sync pulses cnt */
#define MRFIP_REG_EXT_SYNC_P_CNT 0x00000024
/* [0x28]: REG bus speed */
#define MRFIP_REG_SPEED 0x00000028
/* [0x2c]: REG macrocycle lgth */
#define MRFIP_REG_MACROCYC 0x0000002c
#define MASTERFIP_REG_RST 0x00000000
/* [0x4]: REG core id */
#define MASTERFIP_REG_ID 0x00000004
/* [0x8]: REG leds and debug */
#define MASTERFIP_REG_LED 0x00000008
/* [0xc]: REG fmc temperature */
#define MASTERFIP_REG_DS1820_TEMPER 0x0000000c
/* [0x10]: REG fmc unique id lsb */
#define MASTERFIP_REG_DS1820_ID_LSB 0x00000010
/* [0x14]: REG fmc unique id msb */
#define MASTERFIP_REG_DS1820_ID_MSB 0x00000014
/* [0x18]: REG ext sync ctrl */
#define MASTERFIP_REG_EXT_SYNC_CTRL 0x00000018
/* [0x1c]: REG ext sync pulses cnt */
#define MASTERFIP_REG_EXT_SYNC_P_CNT 0x0000001c
/* [0x20]: REG bus speed */
#define MASTERFIP_REG_SPEED 0x00000020
/* [0x24]: REG macrocycle lgth */
#define MASTERFIP_REG_MACROCYC 0x00000024
/* [0x28]: REG macrocycle time cnt */
#define MASTERFIP_REG_MACROCYC_TIME_CNT 0x00000028
/* [0x2c]: REG macrocycles number cnt */
#define MASTERFIP_REG_MACROCYC_NUM_CNT 0x0000002c
/* [0x30]: REG turnaround lgth */
#define MRFIP_REG_TURNAR 0x00000030
/* [0x34]: REG silence lgth */
#define MRFIP_REG_SILEN 0x00000034
/* [0x38]: REG macrocycle time cnt */
#define MRFIP_REG_MACROCYC_TIME_CNT 0x00000038
/* [0x3c]: REG macrocycles number cnt */
#define MRFIP_REG_MACROCYC_NUM_CNT 0x0000003c
/* [0x40]: REG turnaround time cnt */
#define MRFIP_REG_TURNAR_TIME_CNT 0x00000040
/* [0x44]: REG silence time cnt */
#define MRFIP_REG_SILEN_TIME_CNT 0x00000044
/* [0x48]: REG tx ctrl */
#define MRFIP_REG_TX_CTRL 0x00000048
/* [0x4c]: REG tx status */
#define MRFIP_REG_TX_STAT 0x0000004c
/* [0x50]: REG fieldrive wdgn, cdn */
#define MRFIP_REG_FD 0x00000050
/* [0x54]: REG fieldrive wdg timestamp */
#define MRFIP_REG_FD_WDG_TSTAMP 0x00000054
/* [0x58]: REG fieldrive txer cnt */
#define MRFIP_REG_FD_TXER_CNT 0x00000058
/* [0x5c]: REG fieldrive txer tstamp */
#define MRFIP_REG_FD_TXER_TSTAMP 0x0000005c
/* [0x60]: REG rx ctrl */
#define MRFIP_REG_RX_CTRL 0x00000060
/* [0x64]: REG rx status */
#define MRFIP_REG_RX_STAT 0x00000064
/* [0x68]: REG rx current word index */
#define MRFIP_REG_RX_STAT_CURR_WORD_INDX 0x00000068
/* [0x6c]: REG rx number of frames with CRC error */
#define MRFIP_REG_RX_STAT_CRC_ERR_CNT 0x0000006c
/* [0x70]: REG rx payload ctrl byte */
#define MRFIP_REG_RX_PAYLD_CTRL 0x00000070
/* [0x74]: REG rx payload reg1 */
#define MRFIP_REG_RX_PAYLD_REG1 0x00000074
/* [0x78]: REG rx payload reg2 */
#define MRFIP_REG_RX_PAYLD_REG2 0x00000078
/* [0x7c]: REG rx payload reg3 */
#define MRFIP_REG_RX_PAYLD_REG3 0x0000007c
/* [0x80]: REG rx payload reg4 */
#define MRFIP_REG_RX_PAYLD_REG4 0x00000080
/* [0x84]: REG rx payload reg5 */
#define MRFIP_REG_RX_PAYLD_REG5 0x00000084
/* [0x88]: REG rx payload reg6 */
#define MRFIP_REG_RX_PAYLD_REG6 0x00000088
/* [0x8c]: REG rx payload reg7 */
#define MRFIP_REG_RX_PAYLD_REG7 0x0000008c
/* [0x90]: REG rx payload reg8 */
#define MRFIP_REG_RX_PAYLD_REG8 0x00000090
/* [0x94]: REG rx payload reg9 */
#define MRFIP_REG_RX_PAYLD_REG9 0x00000094
/* [0x98]: REG rx payload reg10 */
#define MRFIP_REG_RX_PAYLD_REG10 0x00000098
/* [0x9c]: REG rx payload reg11 */
#define MRFIP_REG_RX_PAYLD_REG11 0x0000009c
/* [0xa0]: REG rx payload reg12 */
#define MRFIP_REG_RX_PAYLD_REG12 0x000000a0
/* [0xa4]: REG rx payload reg13 */
#define MRFIP_REG_RX_PAYLD_REG13 0x000000a4
/* [0xa8]: REG rx payload reg14 */
#define MRFIP_REG_RX_PAYLD_REG14 0x000000a8
/* [0xac]: REG rx payload reg15 */
#define MRFIP_REG_RX_PAYLD_REG15 0x000000ac
/* [0xb0]: REG rx payload reg16 */
#define MRFIP_REG_RX_PAYLD_REG16 0x000000b0
/* [0xb4]: REG rx payload reg17 */
#define MRFIP_REG_RX_PAYLD_REG17 0x000000b4
/* [0xb8]: REG rx payload reg18 */
#define MRFIP_REG_RX_PAYLD_REG18 0x000000b8
/* [0xbc]: REG rx payload reg19 */
#define MRFIP_REG_RX_PAYLD_REG19 0x000000bc
/* [0xc0]: REG rx payload reg20 */
#define MRFIP_REG_RX_PAYLD_REG20 0x000000c0
/* [0xc4]: REG rx payload reg21 */
#define MRFIP_REG_RX_PAYLD_REG21 0x000000c4
/* [0xc8]: REG rx payload reg22 */
#define MRFIP_REG_RX_PAYLD_REG22 0x000000c8
/* [0xcc]: REG rx payload reg23 */
#define MRFIP_REG_RX_PAYLD_REG23 0x000000cc
/* [0xd0]: REG rx payload reg24 */
#define MRFIP_REG_RX_PAYLD_REG24 0x000000d0
/* [0xd4]: REG rx payload reg25 */
#define MRFIP_REG_RX_PAYLD_REG25 0x000000d4
/* [0xd8]: REG rx payload reg26 */
#define MRFIP_REG_RX_PAYLD_REG26 0x000000d8
/* [0xdc]: REG rx payload reg27 */
#define MRFIP_REG_RX_PAYLD_REG27 0x000000dc
/* [0xe0]: REG rx payload reg28 */
#define MRFIP_REG_RX_PAYLD_REG28 0x000000e0
/* [0xe4]: REG rx payload reg29 */
#define MRFIP_REG_RX_PAYLD_REG29 0x000000e4
/* [0xe8]: REG rx payload reg30 */
#define MRFIP_REG_RX_PAYLD_REG30 0x000000e8
/* [0xec]: REG rx payload reg31 */
#define MRFIP_REG_RX_PAYLD_REG31 0x000000ec
/* [0xf0]: REG rx payload reg32 */
#define MRFIP_REG_RX_PAYLD_REG32 0x000000f0
/* [0xf4]: REG rx payload reg33 */
#define MRFIP_REG_RX_PAYLD_REG33 0x000000f4
/* [0xf8]: REG rx payload reg34 */
#define MRFIP_REG_RX_PAYLD_REG34 0x000000f8
/* [0xfc]: REG rx payload reg35 */
#define MRFIP_REG_RX_PAYLD_REG35 0x000000fc
/* [0x100]: REG rx payload reg36 */
#define MRFIP_REG_RX_PAYLD_REG36 0x00000100
/* [0x104]: REG rx payload reg37 */
#define MRFIP_REG_RX_PAYLD_REG37 0x00000104
/* [0x108]: REG rx payload reg38 */
#define MRFIP_REG_RX_PAYLD_REG38 0x00000108
/* [0x10c]: REG rx payload reg39 */
#define MRFIP_REG_RX_PAYLD_REG39 0x0000010c
/* [0x110]: REG rx payload reg40 */
#define MRFIP_REG_RX_PAYLD_REG40 0x00000110
/* [0x114]: REG rx payload reg41 */
#define MRFIP_REG_RX_PAYLD_REG41 0x00000114
/* [0x118]: REG rx payload reg42 */
#define MRFIP_REG_RX_PAYLD_REG42 0x00000118
/* [0x11c]: REG rx payload reg43 */
#define MRFIP_REG_RX_PAYLD_REG43 0x0000011c
/* [0x120]: REG rx payload reg44 */
#define MRFIP_REG_RX_PAYLD_REG44 0x00000120
/* [0x124]: REG rx payload reg45 */
#define MRFIP_REG_RX_PAYLD_REG45 0x00000124
/* [0x128]: REG rx payload reg46 */
#define MRFIP_REG_RX_PAYLD_REG46 0x00000128
/* [0x12c]: REG rx payload reg47 */
#define MRFIP_REG_RX_PAYLD_REG47 0x0000012c
/* [0x130]: REG rx payload reg48 */
#define MRFIP_REG_RX_PAYLD_REG48 0x00000130
/* [0x134]: REG rx payload reg49 */
#define MRFIP_REG_RX_PAYLD_REG49 0x00000134
/* [0x138]: REG rx payload reg50 */
#define MRFIP_REG_RX_PAYLD_REG50 0x00000138
/* [0x13c]: REG rx payload reg51 */
#define MRFIP_REG_RX_PAYLD_REG51 0x0000013c
/* [0x140]: REG rx payload reg52 */
#define MRFIP_REG_RX_PAYLD_REG52 0x00000140
/* [0x144]: REG rx payload reg53 */
#define MRFIP_REG_RX_PAYLD_REG53 0x00000144
/* [0x148]: REG rx payload reg54 */
#define MRFIP_REG_RX_PAYLD_REG54 0x00000148
/* [0x14c]: REG rx payload reg55 */
#define MRFIP_REG_RX_PAYLD_REG55 0x0000014c
/* [0x150]: REG rx payload reg56 */
#define MRFIP_REG_RX_PAYLD_REG56 0x00000150
/* [0x154]: REG rx payload reg57 */
#define MRFIP_REG_RX_PAYLD_REG57 0x00000154
/* [0x158]: REG rx payload reg58 */
#define MRFIP_REG_RX_PAYLD_REG58 0x00000158
/* [0x15c]: REG rx payload reg59 */
#define MRFIP_REG_RX_PAYLD_REG59 0x0000015c
/* [0x160]: REG rx payload reg60 */
#define MRFIP_REG_RX_PAYLD_REG60 0x00000160
/* [0x164]: REG rx payload reg61 */
#define MRFIP_REG_RX_PAYLD_REG61 0x00000164
/* [0x168]: REG rx payload reg62 */
#define MRFIP_REG_RX_PAYLD_REG62 0x00000168
/* [0x16c]: REG rx payload reg63 */
#define MRFIP_REG_RX_PAYLD_REG63 0x0000016c
/* [0x170]: REG rx payload reg64 */
#define MRFIP_REG_RX_PAYLD_REG64 0x00000170
/* [0x174]: REG rx payload reg65 */
#define MRFIP_REG_RX_PAYLD_REG65 0x00000174
/* [0x178]: REG rx payload reg66 */
#define MRFIP_REG_RX_PAYLD_REG66 0x00000178
/* [0x17c]: REG rx payload reg67 */
#define MRFIP_REG_RX_PAYLD_REG67 0x0000017c
/* [0x180]: REG tx ctrl byte */
#define MRFIP_REG_TX_PAYLD_CTRL 0x00000180
/* [0x184]: REG tx payload reg1 */
#define MRFIP_REG_TX_PAYLD_REG1 0x00000184
/* [0x188]: REG tx payload reg2 */
#define MRFIP_REG_TX_PAYLD_REG2 0x00000188
/* [0x18c]: REG tx payload reg3 */
#define MRFIP_REG_TX_PAYLD_REG3 0x0000018c
/* [0x190]: REG tx payload reg4 */
#define MRFIP_REG_TX_PAYLD_REG4 0x00000190
/* [0x194]: REG tx payload reg5 */
#define MRFIP_REG_TX_PAYLD_REG5 0x00000194
/* [0x198]: REG tx payload reg6 */
#define MRFIP_REG_TX_PAYLD_REG6 0x00000198
/* [0x19c]: REG tx payload reg7 */
#define MRFIP_REG_TX_PAYLD_REG7 0x0000019c
/* [0x1a0]: REG tx payload reg8 */
#define MRFIP_REG_TX_PAYLD_REG8 0x000001a0
/* [0x1a4]: REG tx payload reg9 */
#define MRFIP_REG_TX_PAYLD_REG9 0x000001a4
/* [0x1a8]: REG tx payload reg10 */
#define MRFIP_REG_TX_PAYLD_REG10 0x000001a8
/* [0x1ac]: REG tx payload reg11 */
#define MRFIP_REG_TX_PAYLD_REG11 0x000001ac
/* [0x1b0]: REG tx payload reg12 */
#define MRFIP_REG_TX_PAYLD_REG12 0x000001b0
/* [0x1b4]: REG tx payload reg13 */
#define MRFIP_REG_TX_PAYLD_REG13 0x000001b4
/* [0x1b8]: REG tx payload reg14 */
#define MRFIP_REG_TX_PAYLD_REG14 0x000001b8
/* [0x1bc]: REG tx payload reg15 */
#define MRFIP_REG_TX_PAYLD_REG15 0x000001bc
/* [0x1c0]: REG tx payload reg16 */
#define MRFIP_REG_TX_PAYLD_REG16 0x000001c0
/* [0x1c4]: REG tx payload reg17 */
#define MRFIP_REG_TX_PAYLD_REG17 0x000001c4
/* [0x1c8]: REG tx payload reg18 */
#define MRFIP_REG_TX_PAYLD_REG18 0x000001c8
/* [0x1cc]: REG tx payload reg19 */
#define MRFIP_REG_TX_PAYLD_REG19 0x000001cc
/* [0x1d0]: REG tx payload reg20 */
#define MRFIP_REG_TX_PAYLD_REG20 0x000001d0
/* [0x1d4]: REG tx payload reg21 */
#define MRFIP_REG_TX_PAYLD_REG21 0x000001d4
/* [0x1d8]: REG tx payload reg22 */
#define MRFIP_REG_TX_PAYLD_REG22 0x000001d8
/* [0x1dc]: REG tx payload reg23 */
#define MRFIP_REG_TX_PAYLD_REG23 0x000001dc
/* [0x1e0]: REG tx payload reg24 */
#define MRFIP_REG_TX_PAYLD_REG24 0x000001e0
/* [0x1e4]: REG tx payload reg25 */
#define MRFIP_REG_TX_PAYLD_REG25 0x000001e4
/* [0x1e8]: REG tx payload reg26 */
#define MRFIP_REG_TX_PAYLD_REG26 0x000001e8
/* [0x1ec]: REG tx payload reg27 */
#define MRFIP_REG_TX_PAYLD_REG27 0x000001ec
/* [0x1f0]: REG tx payload reg28 */
#define MRFIP_REG_TX_PAYLD_REG28 0x000001f0
/* [0x1f4]: REG tx payload reg29 */
#define MRFIP_REG_TX_PAYLD_REG29 0x000001f4
/* [0x1f8]: REG tx payload reg30 */
#define MRFIP_REG_TX_PAYLD_REG30 0x000001f8
/* [0x1fc]: REG tx payload reg31 */
#define MRFIP_REG_TX_PAYLD_REG31 0x000001fc
/* [0x200]: REG tx payload reg32 */
#define MRFIP_REG_TX_PAYLD_REG32 0x00000200
/* [0x204]: REG tx payload reg33 */
#define MRFIP_REG_TX_PAYLD_REG33 0x00000204
/* [0x208]: REG tx payload reg34 */
#define MRFIP_REG_TX_PAYLD_REG34 0x00000208
/* [0x20c]: REG tx payload reg35 */
#define MRFIP_REG_TX_PAYLD_REG35 0x0000020c
/* [0x210]: REG tx payload reg36 */
#define MRFIP_REG_TX_PAYLD_REG36 0x00000210
/* [0x214]: REG tx payload reg37 */
#define MRFIP_REG_TX_PAYLD_REG37 0x00000214
/* [0x218]: REG tx payload reg38 */
#define MRFIP_REG_TX_PAYLD_REG38 0x00000218
/* [0x21c]: REG tx payload reg39 */
#define MRFIP_REG_TX_PAYLD_REG39 0x0000021c
/* [0x220]: REG tx payload reg40 */
#define MRFIP_REG_TX_PAYLD_REG40 0x00000220
/* [0x224]: REG tx payload reg41 */
#define MRFIP_REG_TX_PAYLD_REG41 0x00000224
/* [0x228]: REG tx payload reg42 */
#define MRFIP_REG_TX_PAYLD_REG42 0x00000228
/* [0x22c]: REG tx payload reg43 */
#define MRFIP_REG_TX_PAYLD_REG43 0x0000022c
/* [0x230]: REG tx payload reg44 */
#define MRFIP_REG_TX_PAYLD_REG44 0x00000230
/* [0x234]: REG tx payload reg45 */
#define MRFIP_REG_TX_PAYLD_REG45 0x00000234
/* [0x238]: REG tx payload reg46 */
#define MRFIP_REG_TX_PAYLD_REG46 0x00000238
/* [0x23c]: REG tx payload reg47 */
#define MRFIP_REG_TX_PAYLD_REG47 0x0000023c
/* [0x240]: REG tx payload reg48 */
#define MRFIP_REG_TX_PAYLD_REG48 0x00000240
/* [0x244]: REG tx payload reg49 */
#define MRFIP_REG_TX_PAYLD_REG49 0x00000244
/* [0x248]: REG tx payload reg50 */
#define MRFIP_REG_TX_PAYLD_REG50 0x00000248
/* [0x24c]: REG tx payload reg51 */
#define MRFIP_REG_TX_PAYLD_REG51 0x0000024c
/* [0x250]: REG tx payload reg52 */
#define MRFIP_REG_TX_PAYLD_REG52 0x00000250
/* [0x254]: REG tx payload reg53 */
#define MRFIP_REG_TX_PAYLD_REG53 0x00000254
/* [0x258]: REG tx payload reg54 */
#define MRFIP_REG_TX_PAYLD_REG54 0x00000258
/* [0x25c]: REG tx payload reg55 */
#define MRFIP_REG_TX_PAYLD_REG55 0x0000025c
/* [0x260]: REG tx payload reg56 */
#define MRFIP_REG_TX_PAYLD_REG56 0x00000260
/* [0x264]: REG tx payload reg57 */
#define MRFIP_REG_TX_PAYLD_REG57 0x00000264
/* [0x268]: REG tx payload reg58 */
#define MRFIP_REG_TX_PAYLD_REG58 0x00000268
/* [0x26c]: REG tx payload reg59 */
#define MRFIP_REG_TX_PAYLD_REG59 0x0000026c
/* [0x270]: REG tx payload reg60 */
#define MRFIP_REG_TX_PAYLD_REG60 0x00000270
/* [0x274]: REG tx payload reg61 */
#define MRFIP_REG_TX_PAYLD_REG61 0x00000274
/* [0x278]: REG tx payload reg62 */
#define MRFIP_REG_TX_PAYLD_REG62 0x00000278
/* [0x27c]: REG tx payload reg63 */
#define MRFIP_REG_TX_PAYLD_REG63 0x0000027c
/* [0x280]: REG tx payload reg64 */
#define MRFIP_REG_TX_PAYLD_REG64 0x00000280
/* [0x284]: REG tx payload reg65 */
#define MRFIP_REG_TX_PAYLD_REG65 0x00000284
/* [0x288]: REG tx payload reg66 */
#define MRFIP_REG_TX_PAYLD_REG66 0x00000288
/* [0x28c]: REG tx payload reg67 */
#define MRFIP_REG_TX_PAYLD_REG67 0x0000028c
#define MASTERFIP_REG_TURNAR 0x00000030
/* [0x34]: REG turnaround time cnt */
#define MASTERFIP_REG_TURNAR_TIME_CNT 0x00000034
/* [0x38]: REG silence lgth */
#define MASTERFIP_REG_SILEN 0x00000038
/* [0x3c]: REG silence time cnt */
#define MASTERFIP_REG_SILEN_TIME_CNT 0x0000003c
/* [0x40]: REG tx ctrl */
#define MASTERFIP_REG_TX_CTRL 0x00000040
/* [0x44]: REG tx status */
#define MASTERFIP_REG_TX_STAT 0x00000044
/* [0x48]: REG FielDrive wdgn, cdn */
#define MASTERFIP_REG_FD 0x00000048
/* [0x4c]: REG FielDrive wdg timestamp */
#define MASTERFIP_REG_FD_WDG_TSTAMP 0x0000004c
/* [0x50]: REG FielDrive txer cnt */
#define MASTERFIP_REG_FD_TXER_CNT 0x00000050
/* [0x54]: REG FielDrive txer tstamp */
#define MASTERFIP_REG_FD_TXER_TSTAMP 0x00000054
/* [0x58]: REG rx ctrl */
#define MASTERFIP_REG_RX_CTRL 0x00000058
/* [0x5c]: REG rx status */
#define MASTERFIP_REG_RX_STAT 0x0000005c
/* [0x60]: REG rx current word index */
#define MASTERFIP_REG_RX_STAT_CURR_WORD_INDX 0x00000060
/* [0x64]: REG rx num of frames with CRC error */
#define MASTERFIP_REG_RX_STAT_CRC_ERR_CNT 0x00000064
/* [0x68]: REG rx payload ctrl byte */
#define MASTERFIP_REG_RX_PAYLD_CTRL 0x00000068
/* [0x6c]: REG rx payload reg1 */
#define MASTERFIP_REG_RX_PAYLD_REG1 0x0000006c
/* [0x70]: REG rx payload reg2 */
#define MASTERFIP_REG_RX_PAYLD_REG2 0x00000070
/* [0x74]: REG rx payload reg3 */
#define MASTERFIP_REG_RX_PAYLD_REG3 0x00000074
/* [0x78]: REG rx payload reg4 */
#define MASTERFIP_REG_RX_PAYLD_REG4 0x00000078
/* [0x7c]: REG rx payload reg5 */
#define MASTERFIP_REG_RX_PAYLD_REG5 0x0000007c
/* [0x80]: REG rx payload reg6 */
#define MASTERFIP_REG_RX_PAYLD_REG6 0x00000080
/* [0x84]: REG rx payload reg7 */
#define MASTERFIP_REG_RX_PAYLD_REG7 0x00000084
/* [0x88]: REG rx payload reg8 */
#define MASTERFIP_REG_RX_PAYLD_REG8 0x00000088
/* [0x8c]: REG rx payload reg9 */
#define MASTERFIP_REG_RX_PAYLD_REG9 0x0000008c
/* [0x90]: REG rx payload reg10 */
#define MASTERFIP_REG_RX_PAYLD_REG10 0x00000090
/* [0x94]: REG rx payload reg11 */
#define MASTERFIP_REG_RX_PAYLD_REG11 0x00000094
/* [0x98]: REG rx payload reg12 */
#define MASTERFIP_REG_RX_PAYLD_REG12 0x00000098
/* [0x9c]: REG rx payload reg13 */
#define MASTERFIP_REG_RX_PAYLD_REG13 0x0000009c
/* [0xa0]: REG rx payload reg14 */
#define MASTERFIP_REG_RX_PAYLD_REG14 0x000000a0
/* [0xa4]: REG rx payload reg15 */
#define MASTERFIP_REG_RX_PAYLD_REG15 0x000000a4
/* [0xa8]: REG rx payload reg16 */
#define MASTERFIP_REG_RX_PAYLD_REG16 0x000000a8
/* [0xac]: REG rx payload reg17 */
#define MASTERFIP_REG_RX_PAYLD_REG17 0x000000ac
/* [0xb0]: REG rx payload reg18 */
#define MASTERFIP_REG_RX_PAYLD_REG18 0x000000b0
/* [0xb4]: REG rx payload reg19 */
#define MASTERFIP_REG_RX_PAYLD_REG19 0x000000b4
/* [0xb8]: REG rx payload reg20 */
#define MASTERFIP_REG_RX_PAYLD_REG20 0x000000b8
/* [0xbc]: REG rx payload reg21 */
#define MASTERFIP_REG_RX_PAYLD_REG21 0x000000bc
/* [0xc0]: REG rx payload reg22 */
#define MASTERFIP_REG_RX_PAYLD_REG22 0x000000c0
/* [0xc4]: REG rx payload reg23 */
#define MASTERFIP_REG_RX_PAYLD_REG23 0x000000c4
/* [0xc8]: REG rx payload reg24 */
#define MASTERFIP_REG_RX_PAYLD_REG24 0x000000c8
/* [0xcc]: REG rx payload reg25 */
#define MASTERFIP_REG_RX_PAYLD_REG25 0x000000cc
/* [0xd0]: REG rx payload reg26 */
#define MASTERFIP_REG_RX_PAYLD_REG26 0x000000d0
/* [0xd4]: REG rx payload reg27 */
#define MASTERFIP_REG_RX_PAYLD_REG27 0x000000d4
/* [0xd8]: REG rx payload reg28 */
#define MASTERFIP_REG_RX_PAYLD_REG28 0x000000d8
/* [0xdc]: REG rx payload reg29 */
#define MASTERFIP_REG_RX_PAYLD_REG29 0x000000dc
/* [0xe0]: REG rx payload reg30 */
#define MASTERFIP_REG_RX_PAYLD_REG30 0x000000e0
/* [0xe4]: REG rx payload reg31 */
#define MASTERFIP_REG_RX_PAYLD_REG31 0x000000e4
/* [0xe8]: REG rx payload reg32 */
#define MASTERFIP_REG_RX_PAYLD_REG32 0x000000e8
/* [0xec]: REG rx payload reg33 */
#define MASTERFIP_REG_RX_PAYLD_REG33 0x000000ec
/* [0xf0]: REG rx payload reg34 */
#define MASTERFIP_REG_RX_PAYLD_REG34 0x000000f0
/* [0xf4]: REG rx payload reg35 */
#define MASTERFIP_REG_RX_PAYLD_REG35 0x000000f4
/* [0xf8]: REG rx payload reg36 */
#define MASTERFIP_REG_RX_PAYLD_REG36 0x000000f8
/* [0xfc]: REG rx payload reg37 */
#define MASTERFIP_REG_RX_PAYLD_REG37 0x000000fc
/* [0x100]: REG rx payload reg38 */
#define MASTERFIP_REG_RX_PAYLD_REG38 0x00000100
/* [0x104]: REG rx payload reg39 */
#define MASTERFIP_REG_RX_PAYLD_REG39 0x00000104
/* [0x108]: REG rx payload reg40 */
#define MASTERFIP_REG_RX_PAYLD_REG40 0x00000108
/* [0x10c]: REG rx payload reg41 */
#define MASTERFIP_REG_RX_PAYLD_REG41 0x0000010c
/* [0x110]: REG rx payload reg42 */
#define MASTERFIP_REG_RX_PAYLD_REG42 0x00000110
/* [0x114]: REG rx payload reg43 */
#define MASTERFIP_REG_RX_PAYLD_REG43 0x00000114
/* [0x118]: REG rx payload reg44 */
#define MASTERFIP_REG_RX_PAYLD_REG44 0x00000118
/* [0x11c]: REG rx payload reg45 */
#define MASTERFIP_REG_RX_PAYLD_REG45 0x0000011c
/* [0x120]: REG rx payload reg46 */
#define MASTERFIP_REG_RX_PAYLD_REG46 0x00000120
/* [0x124]: REG rx payload reg47 */
#define MASTERFIP_REG_RX_PAYLD_REG47 0x00000124
/* [0x128]: REG rx payload reg48 */
#define MASTERFIP_REG_RX_PAYLD_REG48 0x00000128
/* [0x12c]: REG rx payload reg49 */
#define MASTERFIP_REG_RX_PAYLD_REG49 0x0000012c
/* [0x130]: REG rx payload reg50 */
#define MASTERFIP_REG_RX_PAYLD_REG50 0x00000130
/* [0x134]: REG rx payload reg51 */
#define MASTERFIP_REG_RX_PAYLD_REG51 0x00000134
/* [0x138]: REG rx payload reg52 */
#define MASTERFIP_REG_RX_PAYLD_REG52 0x00000138
/* [0x13c]: REG rx payload reg53 */
#define MASTERFIP_REG_RX_PAYLD_REG53 0x0000013c
/* [0x140]: REG rx payload reg54 */
#define MASTERFIP_REG_RX_PAYLD_REG54 0x00000140
/* [0x144]: REG rx payload reg55 */
#define MASTERFIP_REG_RX_PAYLD_REG55 0x00000144
/* [0x148]: REG rx payload reg56 */
#define MASTERFIP_REG_RX_PAYLD_REG56 0x00000148
/* [0x14c]: REG rx payload reg57 */
#define MASTERFIP_REG_RX_PAYLD_REG57 0x0000014c
/* [0x150]: REG rx payload reg58 */
#define MASTERFIP_REG_RX_PAYLD_REG58 0x00000150
/* [0x154]: REG rx payload reg59 */
#define MASTERFIP_REG_RX_PAYLD_REG59 0x00000154
/* [0x158]: REG rx payload reg60 */
#define MASTERFIP_REG_RX_PAYLD_REG60 0x00000158
/* [0x15c]: REG rx payload reg61 */
#define MASTERFIP_REG_RX_PAYLD_REG61 0x0000015c
/* [0x160]: REG rx payload reg62 */
#define MASTERFIP_REG_RX_PAYLD_REG62 0x00000160
/* [0x164]: REG rx payload reg63 */
#define MASTERFIP_REG_RX_PAYLD_REG63 0x00000164
/* [0x168]: REG rx payload reg64 */
#define MASTERFIP_REG_RX_PAYLD_REG64 0x00000168
/* [0x16c]: REG rx payload reg65 */
#define MASTERFIP_REG_RX_PAYLD_REG65 0x0000016c
/* [0x170]: REG rx payload reg66 */
#define MASTERFIP_REG_RX_PAYLD_REG66 0x00000170
/* [0x174]: REG rx payload reg67 */
#define MASTERFIP_REG_RX_PAYLD_REG67 0x00000174
/* [0x178]: REG tx ctrl byte */
#define MASTERFIP_REG_TX_PAYLD_CTRL 0x00000178
/* [0x17c]: REG tx payload reg1 */
#define MASTERFIP_REG_TX_PAYLD_REG1 0x0000017c
/* [0x180]: REG tx payload reg2 */
#define MASTERFIP_REG_TX_PAYLD_REG2 0x00000180
/* [0x184]: REG tx payload reg3 */
#define MASTERFIP_REG_TX_PAYLD_REG3 0x00000184
/* [0x188]: REG tx payload reg4 */
#define MASTERFIP_REG_TX_PAYLD_REG4 0x00000188
/* [0x18c]: REG tx payload reg5 */
#define MASTERFIP_REG_TX_PAYLD_REG5 0x0000018c
/* [0x190]: REG tx payload reg6 */
#define MASTERFIP_REG_TX_PAYLD_REG6 0x00000190
/* [0x194]: REG tx payload reg7 */
#define MASTERFIP_REG_TX_PAYLD_REG7 0x00000194
/* [0x198]: REG tx payload reg8 */
#define MASTERFIP_REG_TX_PAYLD_REG8 0x00000198
/* [0x19c]: REG tx payload reg9 */
#define MASTERFIP_REG_TX_PAYLD_REG9 0x0000019c
/* [0x1a0]: REG tx payload reg10 */
#define MASTERFIP_REG_TX_PAYLD_REG10 0x000001a0
/* [0x1a4]: REG tx payload reg11 */
#define MASTERFIP_REG_TX_PAYLD_REG11 0x000001a4
/* [0x1a8]: REG tx payload reg12 */
#define MASTERFIP_REG_TX_PAYLD_REG12 0x000001a8
/* [0x1ac]: REG tx payload reg13 */
#define MASTERFIP_REG_TX_PAYLD_REG13 0x000001ac
/* [0x1b0]: REG tx payload reg14 */
#define MASTERFIP_REG_TX_PAYLD_REG14 0x000001b0
/* [0x1b4]: REG tx payload reg15 */
#define MASTERFIP_REG_TX_PAYLD_REG15 0x000001b4
/* [0x1b8]: REG tx payload reg16 */
#define MASTERFIP_REG_TX_PAYLD_REG16 0x000001b8
/* [0x1bc]: REG tx payload reg17 */
#define MASTERFIP_REG_TX_PAYLD_REG17 0x000001bc
/* [0x1c0]: REG tx payload reg18 */
#define MASTERFIP_REG_TX_PAYLD_REG18 0x000001c0
/* [0x1c4]: REG tx payload reg19 */
#define MASTERFIP_REG_TX_PAYLD_REG19 0x000001c4
/* [0x1c8]: REG tx payload reg20 */
#define MASTERFIP_REG_TX_PAYLD_REG20 0x000001c8
/* [0x1cc]: REG tx payload reg21 */
#define MASTERFIP_REG_TX_PAYLD_REG21 0x000001cc
/* [0x1d0]: REG tx payload reg22 */
#define MASTERFIP_REG_TX_PAYLD_REG22 0x000001d0
/* [0x1d4]: REG tx payload reg23 */
#define MASTERFIP_REG_TX_PAYLD_REG23 0x000001d4
/* [0x1d8]: REG tx payload reg24 */
#define MASTERFIP_REG_TX_PAYLD_REG24 0x000001d8
/* [0x1dc]: REG tx payload reg25 */
#define MASTERFIP_REG_TX_PAYLD_REG25 0x000001dc
/* [0x1e0]: REG tx payload reg26 */
#define MASTERFIP_REG_TX_PAYLD_REG26 0x000001e0
/* [0x1e4]: REG tx payload reg27 */
#define MASTERFIP_REG_TX_PAYLD_REG27 0x000001e4
/* [0x1e8]: REG tx payload reg28 */
#define MASTERFIP_REG_TX_PAYLD_REG28 0x000001e8
/* [0x1ec]: REG tx payload reg29 */
#define MASTERFIP_REG_TX_PAYLD_REG29 0x000001ec
/* [0x1f0]: REG tx payload reg30 */
#define MASTERFIP_REG_TX_PAYLD_REG30 0x000001f0
/* [0x1f4]: REG tx payload reg31 */
#define MASTERFIP_REG_TX_PAYLD_REG31 0x000001f4
/* [0x1f8]: REG tx payload reg32 */
#define MASTERFIP_REG_TX_PAYLD_REG32 0x000001f8
/* [0x1fc]: REG tx payload reg33 */
#define MASTERFIP_REG_TX_PAYLD_REG33 0x000001fc
/* [0x200]: REG tx payload reg34 */
#define MASTERFIP_REG_TX_PAYLD_REG34 0x00000200
/* [0x204]: REG tx payload reg35 */
#define MASTERFIP_REG_TX_PAYLD_REG35 0x00000204
/* [0x208]: REG tx payload reg36 */
#define MASTERFIP_REG_TX_PAYLD_REG36 0x00000208
/* [0x20c]: REG tx payload reg37 */
#define MASTERFIP_REG_TX_PAYLD_REG37 0x0000020c
/* [0x210]: REG tx payload reg38 */
#define MASTERFIP_REG_TX_PAYLD_REG38 0x00000210
/* [0x214]: REG tx payload reg39 */
#define MASTERFIP_REG_TX_PAYLD_REG39 0x00000214
/* [0x218]: REG tx payload reg40 */
#define MASTERFIP_REG_TX_PAYLD_REG40 0x00000218
/* [0x21c]: REG tx payload reg41 */
#define MASTERFIP_REG_TX_PAYLD_REG41 0x0000021c
/* [0x220]: REG tx payload reg42 */
#define MASTERFIP_REG_TX_PAYLD_REG42 0x00000220
/* [0x224]: REG tx payload reg43 */
#define MASTERFIP_REG_TX_PAYLD_REG43 0x00000224
/* [0x228]: REG tx payload reg44 */
#define MASTERFIP_REG_TX_PAYLD_REG44 0x00000228
/* [0x22c]: REG tx payload reg45 */
#define MASTERFIP_REG_TX_PAYLD_REG45 0x0000022c
/* [0x230]: REG tx payload reg46 */
#define MASTERFIP_REG_TX_PAYLD_REG46 0x00000230
/* [0x234]: REG tx payload reg47 */
#define MASTERFIP_REG_TX_PAYLD_REG47 0x00000234
/* [0x238]: REG tx payload reg48 */
#define MASTERFIP_REG_TX_PAYLD_REG48 0x00000238
/* [0x23c]: REG tx payload reg49 */
#define MASTERFIP_REG_TX_PAYLD_REG49 0x0000023c
/* [0x240]: REG tx payload reg50 */
#define MASTERFIP_REG_TX_PAYLD_REG50 0x00000240
/* [0x244]: REG tx payload reg51 */
#define MASTERFIP_REG_TX_PAYLD_REG51 0x00000244
/* [0x248]: REG tx payload reg52 */
#define MASTERFIP_REG_TX_PAYLD_REG52 0x00000248
/* [0x24c]: REG tx payload reg53 */
#define MASTERFIP_REG_TX_PAYLD_REG53 0x0000024c
/* [0x250]: REG tx payload reg54 */
#define MASTERFIP_REG_TX_PAYLD_REG54 0x00000250
/* [0x254]: REG tx payload reg55 */
#define MASTERFIP_REG_TX_PAYLD_REG55 0x00000254
/* [0x258]: REG tx payload reg56 */
#define MASTERFIP_REG_TX_PAYLD_REG56 0x00000258
/* [0x25c]: REG tx payload reg57 */
#define MASTERFIP_REG_TX_PAYLD_REG57 0x0000025c
/* [0x260]: REG tx payload reg58 */
#define MASTERFIP_REG_TX_PAYLD_REG58 0x00000260
/* [0x264]: REG tx payload reg59 */
#define MASTERFIP_REG_TX_PAYLD_REG59 0x00000264
/* [0x268]: REG tx payload reg60 */
#define MASTERFIP_REG_TX_PAYLD_REG60 0x00000268
/* [0x26c]: REG tx payload reg61 */
#define MASTERFIP_REG_TX_PAYLD_REG61 0x0000026c
/* [0x270]: REG tx payload reg62 */
#define MASTERFIP_REG_TX_PAYLD_REG62 0x00000270
/* [0x274]: REG tx payload reg63 */
#define MASTERFIP_REG_TX_PAYLD_REG63 0x00000274
/* [0x278]: REG tx payload reg64 */
#define MASTERFIP_REG_TX_PAYLD_REG64 0x00000278
/* [0x27c]: REG tx payload reg65 */
#define MASTERFIP_REG_TX_PAYLD_REG65 0x0000027c
/* [0x280]: REG tx payload reg66 */
#define MASTERFIP_REG_TX_PAYLD_REG66 0x00000280
/* [0x284]: REG tx payload reg67 */
#define MASTERFIP_REG_TX_PAYLD_REG67 0x00000284
#endif
rtl/wbgen/fmc_masterfip_csr.htm → rtl/wbgen/masterfip_wbgen2_csr.html
View file @ 86ec47a0
This source diff could not be displayed because it is too large. You can view the blob instead.
sim/spec/data_vectors/masterFIP_test.vec
View file @ 86ec47a0
......@@ -30,223 +30,227 @@ wait %d900
-------------------------------------------------------------------------------
--------------- RESETS ---------------
-- reset inactive
wr 0000000000030000 F CAFE0003
wr 0000000000010000 F CAFE0000
wait %d20
-- reset active
wr 0000000000030000 F CAFE0000
wait %d20
-- core and FD reset active
wr 000000000010000 F CAFE0003
wait %d40
-- FD reset active
wr 0000000000010000 F CAFE0002
wait %d40
-- reset inactive
wr 0000000000030000 F CAFE0003
wr 0000000000010000 F CAFE0000
wait %d20
----- CHECK COUNTERS FUNCTINALITY -----
-- macrocycle cnt start
--wr 000000000003001C F 80004880
--wr 000000000001001C F 80004880
--wait %d20
--wr 000000000003001C F 00002A6D
--wr 000000000001001C F 00002A6D
-- turnar counter top
--wr 0000000000030020 F 000007D0
--wr 0000000000010020 F 000007D0
--wait %d20
-- silen counter top
--wr 0000000000030024 F 00000FA0
--wr 000000000010024 F 00000FA0
--wait %d20
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000030048 F 00000001
wr 0000000000010040 F 00000001
wait %d10
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030180 F 00000003
wr 0000000000010178 F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 0000000000030184 F 00000305
wr 000000000001017C F 00000305
wait %d20
-- tx_start
wr 0000000000030048 F 00000202
wr 0000000000010040 F 00000202
wait %d20000
--------------- RP_DAT ---------------
-- tx_rst
wr 0000000000030048 F 00000001
wr 0000000000010040 F 00000001
wait %d10
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d20
-- control byte of rp_dat
wr 0000000000030180 F 00000002
wr 0000000000010178 F 00000002
wait %d20
-- data bytes
wr 0000000000030184 F BBAA0340
wr 000000000001017C F BBAA0340
wait %d20
wr 0000000000030188 F EEDDCC05
wr 0000000000010180 F EEDDCC05
wait %d20
-- tx_start
wr 0000000000030048 F 00000502
wr 0000000000010040 F 00000502
wait %d20000
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d20000
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000030048 F 00000001
wr 0000000000010040 F 00000001
wait %d10
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030180 F 00000003
wr 0000000000010178 F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 0000000000030184 F 00000310 -------------------------0314
wr 000000000001017C F 00000310 -------------------------0314
wait %d20
-- tx_start
wr 0000000000030048 F 00000202
wr 0000000000010040 F 00000202
wait %d200
-- deactivate tx_start
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
-- release rx_rst
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d40000
-- read received data
rd 0000000000030070 F 00000002
rd 0000000000010070 F 00000002
wait %d20
rd 0000000000030048 F 03800550
rd 0000000000010040 F 03800550
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 0000000000030048 F 00000001
wr 0000000000010040 F 00000001
wait %d10
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030180 F 00000003
wr 0000000000010178 F 00000003
wait %d20
-- data bytes varid = 0603 for agent to produce
wr 0000000000030184 F 00000306
wr 000000000001017C F 00000306
wait %d20
-- tx_start
wr 0000000000030048 F 00000202
wr 0000000000010040 F 00000202
wait %d20
-- deactivate tx_start
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
-- release rx_rst
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d40000
-- read received data
rd 0000000000030070 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
rd 0000000000010070 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
wait %d20
rd 0000000000030058 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
rd 0000000000010058 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
wait %d20
rd 000000000003005C F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
rd 000000000001005C F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
wait %d20
rd 0000000000030060 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010060 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030068 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010068 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003006C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 000000000001006C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030070 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010070 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030074 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010074 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030078 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010078 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003007C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 000000000001007C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030080 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010080 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030084 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010084 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030088 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010088 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003008C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 000000000001008C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030090 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010090 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030094 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010094 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030098 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010098 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003009C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 000000000001009C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300A0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100A0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300A4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100A4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300A8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100A8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300AC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100AC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300B0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100B0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300B4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100B4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300B8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100B8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300BC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100BC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300C0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100C0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300C4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100C4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300C8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100C8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300CC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100CC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300D0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100D0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300D4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100D4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300D8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100D8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300DC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100DC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
wait %d40000
--------------- RP_FIN ---------------
-- control byte of rp_fin
wr 0000000000030180 F 00000040
wr 0000000000010178 F 00000040
wait %d20
-- rx_rst
wr 0000000000030048 F 00000001
wr 0000000000010040 F 00000001
wait %d20
-- tx_start
wr 0000000000030048 F 00000002
wr 0000000000010040 F 00000002
wait %d20000
\ No newline at end of file
sim/spec/testbench/tb_masterFIP.vhd
View file @ 86ec47a0
......@@ -24,23 +24,35 @@ use IEEE.numeric_std.all;
library nanoFIP_lib;
use nanoFIP_lib.all;
library work;
use work.wishbone_pkg.all;
use work.spec_node_pkg.all;
use work.wrn_mqueue_pkg.all;
use work.wr_node_pkg.all;
use work.masterFIP_pkg.all;
use work.masterfip_wbgen2_pkg.all;
use work.gencores_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity tb_masterFIP is
end tb_masterFIP;
architecture behavioral of tb_masterFIP is
component spec_masterFIP
component spec_masterfip_mt
generic(
g_span : integer :=32;
g_width : integer :=32;
values_for_simul : boolean :=FALSE
--g_span : integer :=32;
--g_width : integer :=32;
g_simulation : boolean :=TRUE
);
port(
-- interface with GNUM circuit
rst_n_a_i : in std_logic;
l_rst_n_i : in std_logic;
-- P2L Direction
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_clkp_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clkn_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i: in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
......@@ -50,8 +62,8 @@ architecture behavioral of tb_masterFIP is
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
-- L2P Direction
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_clkp_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clkn_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o: out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
......@@ -60,13 +72,13 @@ architecture behavioral of tb_masterFIP is
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i: in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
--irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
ext_sync_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
......@@ -79,10 +91,10 @@ architecture behavioral of tb_masterFIP is
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
pcb_ver_i : in std_logic_vector(3 downto 0);
prsnt_m2c_n_i : in std_logic;
fmc_prsnt_m2c_n_i : in std_logic;
clk_20m_vcxo_i : in std_logic
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic
);
end component;
......@@ -365,6 +377,8 @@ signal spec_led_red : std_logic;
signal consu_data : std_logic_vector (15 downto 0);
signal nanoFIP_rxcdn, nanoFIP_txena, nanoFIP_txck, nanoFIP_rstno ,nanoFIP_wdgn : std_logic;
signal nanoFIP_clk : std_logic;
signal clk_125m_pllref_p : std_logic := '1';
signal clk_125m_pllref_n : std_logic := '0';
signal ext_sync : std_logic := '0';
......@@ -436,7 +450,7 @@ signal spare : std_logic;
signal m_id : std_logic_vector (3 downto 0); --! Model identification settings
signal c_id : std_logic_vector (3 downto 0); --! Constructor identification settings
signal p3_lgth : std_logic_vector (2 downto 0); --! Produced variable data length
signal slone : std_logic; --! Stand-alone mode
signal slone : std_logic; --! Stand-alone mode
signal nostat : std_logic; --! No NanoFIP status transmission
-----------------------------------------------------------------------------
......@@ -450,17 +464,17 @@ signal spare : std_logic;
begin
dut: spec_masterFIP
dut: spec_masterfip_mt
generic map(
g_span => 32,
g_width => 32,
values_for_simul => TRUE
--g_span => 32,
--g_width => 32,
g_simulation => TRUE
)
port map(
-- interface with GNUM circuit
rst_n_a_i => rst_n,
p2l_clk_p_i => p2l_clkp,
p2l_clk_n_i => p2l_clkn,
l_rst_n_i => rst_n,
p2l_clkp_i => p2l_clkp,
p2l_clkn_i => p2l_clkn,
p2l_data_i => p2l_data,
p2l_dframe_i => p2l_dframe,
p2l_valid_i => p2l_valid,
......@@ -469,8 +483,8 @@ begin
p_wr_rdy_o => p_wr_rdy,
rx_error_o => rx_error,
vc_rdy_i => vc_rdy,
l2p_clk_p_o => l2p_clkp,
l2p_clk_n_o => l2p_clkn,
l2p_clkp_o => l2p_clkp,
l2p_clkn_o => l2p_clkn,
l2p_data_o => l2p_data,
l2p_dframe_o => l2p_dframe,
l2p_valid_o => l2p_valid,
......@@ -480,7 +494,7 @@ begin
p_rd_d_rdy_i => p_rd_d_rdy,
tx_error_i => tx_error,
ext_sync_i => ext_sync,
ext_sync_i => ext_sync,
speed_b0_i => '1',
speed_b1_i => '0',
......@@ -495,10 +509,10 @@ begin
fd_txena_o => fd_txena,
-- other signals on the spec card
pcb_ver_i => (others => '0'),
prsnt_m2c_n_i => '0',
fmc_prsnt_m2c_n_i => '0',
clk_20m_vcxo_i => spec_clk_i);
clk_125m_pllref_p_i => clk_125m_pllref_p,
clk_125m_pllref_n_i => clk_125m_pllref_n);
......@@ -729,8 +743,9 @@ begin
spec_clock: process
begin
spec_clk_i <= not (spec_clk_i) after 1 ns;
wait for spec_clk_period/2;
clk_125m_pllref_p <= not (clk_125m_pllref_p) after 1 ns;
clk_125m_pllref_n <= not (clk_125m_pllref_n) after 1 ns;
wait for pll_clk_period/2;
end process;
-- nanoFIP_clock: process
......
syn/spec/spec_masterfip.xise
View file @ 86ec47a0
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/spec/tb_masterFIP.fdo
View file @ 86ec47a0
######################################################################
##
## Filename: tb_masterFIP.fdo
## Created on: Thu Oct 20 12:14:30 W. Europe Daylight Time 2016
## Created on: Fri Feb 10 15:02:25 W. Europe Standard Time 2017
##
## Auto generated by Project Navigator for Behavioral Simulation
##
......@@ -20,19 +20,141 @@ vlib work
#
# Compile sources
#
vcom -explicit -93 "../../rtl/from_nanofip/wf_package.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_register.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_private_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/inferred_sync_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/generic_shiftreg_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_eb_cycle_gen.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_lr_wbgen2_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_csr_wbgen2_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_framer.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_package.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_wishbone_slave.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_slot.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_etherbone_output.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_lm32_wrapper.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_lr_wb.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_package.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/dualram_512x8.vhd"
vcom -explicit -93 "../../rtl/mf_wbgen2_pkg.vhd"
vcom -explicit -93 "../../rtl/masterfip_wbgen2_pkg.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_incr_counter.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_decr_counter.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_crc.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/wb_remapper.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/smem/wrn_shared_mem.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_remote.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_host.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_csr_wb.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_cb.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_incr_counter.vhd"
vlib nanoFIP_lib
......@@ -48,17 +170,25 @@ vcom -explicit -93 "../../rtl/from_nanofip/wf_tx_osc.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_rx_osc.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_rx_deserializer.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_rx_deglitcher.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_core.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wr_core.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd"
vcom -explicit -93 "../../top/spec/spec_reset_gen.vhd"
vcom -explicit -93 "../../sim/spec/testbench/tb_package.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd"
......@@ -84,31 +214,20 @@ vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_cons_bytes_processor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/textutil.vhd"
vcom -explicit -93 "../../sim/spec/testbench/encounter.vhd"
vcom -explicit -93 "../../rtl/masterfip_wbgen2_csr.vhd"
vcom -explicit -93 "../../rtl/masterfip_tx.vhd"
vcom -explicit -93 "../../rtl/masterfip_rx.vhd"
vcom -explicit -93 "../../rtl/incr_counter.vhd"
vcom -explicit -93 "../../rtl/fmc_masterfip_csr.vhd"
vcom -explicit -93 "../../rtl/decr_counter.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_core_with_etherbone.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd"
vcom -explicit -93 "../../top/spec/synthesis_descriptor.vhd"
vcom -explicit -93 "../../top/spec/spec_reset_gen.vhd"
vcom -explicit -93 "../../sim/spec/testbench/wishbone_monitor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/wishbone_interface.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_sequencer.vhd"
......@@ -134,10 +253,8 @@ vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_c
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/mem_model.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/cmd_router1.vhd"
vcom -explicit -93 "../../rtl/fmc_masterFIP_core.vhd"
vcom -explicit -93 "../../rtl/carrier_info.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 "../../top/spec/spec_masterFIP.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_template.vhd"
vcom -explicit -93 "../../top/spec_mt/spec_masterfip_mt.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_interface.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/nanofip.vhd"
......
syn/spec_mt/spec_masterfip_mt.xise
View file @ 86ec47a0
This source diff could not be displayed because it is too large. You can view the blob instead.
top/spec/spec_masterfip.ucf
View file @ 86ec47a0
......@@ -71,8 +71,8 @@ NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_tst_n_o" LOC = U8;
NET "ext_sync_tst_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_o" LOC = W6;
NET "ext_sync_oe_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_n_o" LOC = W6;
NET "ext_sync_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
......
top/spec/spec_masterfip.vhd
View file @ 86ec47a0
......@@ -90,7 +90,6 @@ use work.masterFIP_pkg.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.synthesis_descriptor.all;
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -99,29 +98,24 @@ use UNISIM.vcomponents.all;
--=================================================================================================
entity spec_masterfip is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
values_for_simul : boolean := FALSE); -- set to TRUE in test-bench instantiation
(--g_span : integer := 32; -- address span in bus interfaces
--g_width : integer := 32; -- data width in bus interfaces
g_simulation : boolean := FALSE); -- set to TRUE in test-bench instantiation
port
(-- SPEC carrier
clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
carrier_onewire_b : inout std_logic; -- 1-wire
button1_i : in std_logic := '1'; -- reset button
button2_i : in std_logic := '1'; -- not used button
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
led_green_o : out std_logic; -- LEDs carrier front pannel
led_red_o : out std_logic;
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic; -- mezzanine presence
fmc_prsnt_m2c_n_i : in std_logic; -- mezzanine presence
-- Interface with GN4124
rst_n_a_i : in std_logic;
l_rst_n_i : in std_logic;
-- P2L Direction
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_clkp_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clkn_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0);-- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
......@@ -131,8 +125,8 @@ entity spec_masterfip is
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
-- L2P Direction
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+ (freq set in GN4124 config registers)
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock- (freq set in GN4124 config registers)
l2p_clkp_o : out std_logic; -- Transmitter Source Synchronous Clock+ (freq set in GN4124 config registers)
l2p_clkn_o : out std_logic; -- Transmitter Source Synchronous Clock- (freq set in GN4124 config registers)
l2p_data_o : out std_logic_vector(15 downto 0);-- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
......@@ -159,7 +153,7 @@ entity spec_masterfip is
ext_sync_term_en_o : out std_logic; -- External synch pulse transceiver
ext_sync_dir_o : out std_logic;
ext_sync_oe_o : out std_logic;
ext_sync_oe_n_o : out std_logic;
ext_sync_tst_n_o : out std_logic;
ext_sync_i : in std_logic;
......@@ -204,12 +198,10 @@ architecture rtl of spec_masterfip is
constant c_MASTER_GENNUM : integer := 0;
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(2 downto 0) :=
(0 => f_sdb_embed_device (c_ONEWIRE_SDB_DEVICE, x"00010000"),
1 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
2 => f_sdb_embed_device (c_MASTERFIP_SDB_DEVICE, x"00030000"),
3 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
4 => f_sdb_embed_synthesis (c_SDB_SYNTHESIS_INFO));
2 => f_sdb_embed_device (c_MASTERFIP_SDB_DEVICE, x"00030000"));
---------------------------------------------------------------------------------------------------
......@@ -217,9 +209,9 @@ architecture rtl of spec_masterfip is
---------------------------------------------------------------------------------------------------
-- clocks
signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal clk_100m_sys, pllout_clk_sys : std_logic;
signal pllout_clk_sys_fb : std_logic;
signal clk_125m_pllref : std_logic;
signal sys_locked, pll_status : std_logic;
-- reset
signal rst_sys, rst_sys_n : std_logic;
......@@ -235,7 +227,7 @@ architecture rtl of spec_masterfip is
-- SPEC 1-wire
signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
-- aux
signal aux : std_logic_vector(7 downto 0);
signal aux : std_logic_vector(31 downto 0);
-- LEDs
signal led_clk_100m_divider : unsigned(22 downto 0);
signal led_clk_100m_aux : std_logic_vector(7 downto 0);
......@@ -251,51 +243,53 @@ begin
-- 100 MHz universal clk generation --
---------------------------------------------------------------------------------------------------
cmp_spec_clk_ibuf : IBUFG
port map
(I => clk_20m_vcxo_i,
O => clk_20m_vcxo_buf);
U_Buf_CLK_PLL : IBUFGDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => true -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sys_clk_pll : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10, -- 100 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 25,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map
(CLKFBOUT => pllout_clk_sys_fb,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_sys_fb,
CLKIN => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_sys_100m_buf : BUFG
port map
(O => clk_100m_sys,
I => pllout_clk_sys);
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys, -- 100 MHz
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
cmp_clk_sys_buf : BUFG
port map (
O => clk_100m_sys,
I => pllout_clk_sys);
---------------------------------------------------------------------------------------------------
-- RESET --
......@@ -304,14 +298,29 @@ begin
cmp_spec_rst_gen : spec_reset_gen
port map
(clk_sys_i => clk_100m_sys,
rst_pcie_n_a_i => rst_n_a_i, -- reset from GN4124 chip
rst_button_n_a_i => button1_i, -- reset from SPEC button
rst_pcie_n_a_i => l_rst_n_i, -- reset from GN4124 chip
rst_button_n_a_i => '1', -- reset from SPEC button
rst_n_o => rst_sys_n);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_sys <= not rst_sys_n;
---------------------------------------------------------------------------------------------------
-- Fixed signals --
---------------------------------------------------------------------------------------------------
ext_sync_dir_o <= '0'; -- Direction fixed to: B -> A
ext_sync_oe_n_o <= '0'; -- Output fixed to: enabled
-- To be removed on hw V3
ext_sync_tst_n_o <= 'Z'; -- OFF
adc_prim_conn_n_o <= 'Z'; -- OFF
adc_sec_conn_n_o <= 'Z'; -- OFF
adc_1v8_shdn_n_o <= '0'; -- OFF
adc_m5v_shdn_n_o <= '0'; -- OFF
adc_5v_en_n_o <= '1'; -- OFF
---------------------------------------------------------------------------------------------------
-- CSR WISHBONE CROSSBAR --
---------------------------------------------------------------------------------------------------
......@@ -344,11 +353,11 @@ begin
cmp_gn4124_core: gn4124_core
port map
(rst_n_a_i => rst_n_a_i,
(rst_n_a_i => l_rst_n_i,
status_o => gn4124_status,
-- P2L Direction Source Sync DDR related signals
p2l_clk_p_i => p2l_clk_p_i,
p2l_clk_n_i => p2l_clk_n_i,
p2l_clk_p_i => p2l_clkp_i,
p2l_clk_n_i => p2l_clkn_i,
p2l_data_i => p2l_data_i,
p2l_dframe_i => p2l_dframe_i,
p2l_valid_i => p2l_valid_i,
......@@ -358,8 +367,8 @@ begin
p_wr_rdy_o => p_wr_rdy_o,
rx_error_o => rx_error_o,
-- L2P Direction Source Sync DDR related signals
l2p_clk_p_o => l2p_clk_p_o,
l2p_clk_n_o => l2p_clk_n_o,
l2p_clk_p_o => l2p_clkp_o,
l2p_clk_n_o => l2p_clkn_o,
l2p_data_o => l2p_data_o ,
l2p_dframe_o => l2p_dframe_o,
l2p_valid_o => l2p_valid_o,
......@@ -429,17 +438,15 @@ begin
values_for_simul => FALSE)
port map
(clk_i => clk_100m_sys,
rst_i => rst_sys,
rst_n_i => rst_sys_n,
-- Bus speed
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- One Wire
onewire_b => carrier_onewire_b,
-- FielDrive
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rxcdn_a_i => fd_rxcdn_i,
fd_rxd_a_i => fd_rxd_i,
fd_txer_a_i => fd_txer_i,
fd_wdgn_a_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
......@@ -447,15 +454,8 @@ begin
-- External synchronisation pulse transceiver
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_dir_o => ext_sync_dir_o,
ext_sync_oe_o => ext_sync_oe_o,
ext_sync_tst_n_o => ext_sync_tst_n_o,
ext_sync_i => ext_sync_i,
-- Power supplies for the ADC
adc_1v8_shdn_n_o => adc_1v8_shdn_n_o,
adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
adc_5v_en_n_o => adc_5v_en_n_o,
adc_prim_conn_n_o => adc_prim_conn_n_o,
adc_sec_conn_n_o => adc_sec_conn_n_o,
ext_sync_oe_n_o => ext_sync_oe_n_o,
ext_sync_a_i => ext_sync_i,
-- WISHBONE interface with the GN4124 core
wb_adr_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).adr,
wb_dat_i => cnx_master_out(c_WB_SLAVE_MASTERFIP).dat,
......@@ -466,8 +466,8 @@ begin
wb_dat_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).dat,
wb_ack_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).stall,
-- Aux
aux_o => aux);
-- LEDs
leds_o => aux);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
......@@ -502,75 +502,6 @@ begin
extended_o => rx_act);
---------------------------------------------------------------------------------------------------
-- SPEC 1-wire --
---------------------------------------------------------------------------------------------------
-- cmp_carrier_onewire : xwb_onewire_master
-- generic map
-- (g_interface_mode => CLASSIC,
-- g_address_granularity => BYTE,
-- g_num_ports => 1,
-- g_ow_btp_normal => "5.0",
-- g_ow_btp_overdrive => "1.0")
-- port map
-- (clk_sys_i => clk_100m_sys,
-- rst_n_i => rst_sys_n,
-- slave_i => cnx_master_out(c_WB_SLAVE_SPEC_ONEWIRE),
-- slave_o => cnx_master_in(c_WB_SLAVE_SPEC_ONEWIRE),
-- desc_o => open,
-- owr_pwren_o => open,
-- owr_en_o => carrier_owr_en,
-- owr_i => carrier_owr_i);
--
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- carrier_onewire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
-- carrier_owr_i(0) <= carrier_onewire_b;
---------------------------------------------------------------------------------------------------
-- Carrier CSR information --
---------------------------------------------------------------------------------------------------
-- Information on carrier type, mezzanine presence, pcb version
cmp_carrier_csr : carrier_info
port map
(rst_n_i => rst_sys_n,
clk_sys_i => clk_100m_sys,
wb_adr_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).stall,
carrier_info_carrier_pcb_rev_i => pcb_ver_i,
carrier_info_carrier_reserved_i => (others => '0'),
carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_info_stat_p2l_pll_lck_i => gn4124_status(0),
carrier_info_stat_sys_pll_lck_i => pll_status,
carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_reserved_i => (others => '0'),
carrier_info_ctrl_led_green_o => open,
carrier_info_ctrl_led_red_o => open,
carrier_info_ctrl_dac_clr_n_o => open,
carrier_info_ctrl_reserved_o => open,
carrier_info_rst_fmc0_n_o => open,
carrier_info_rst_fmc0_n_i => '1',
carrier_info_rst_fmc0_n_load_o => open,
carrier_info_rst_reserved_o => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).rty <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_INFO).int <= '0';
---------------------------------------------------------------------------------------------------
-- SPEC LEDs --
---------------------------------------------------------------------------------------------------
......@@ -593,21 +524,22 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
led_green_o <= led_clk_100m_aux(0);
led_red_o <= '1';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
spec_red_led: gc_extend_pulse
generic map
(g_width => 5000000)
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_sys_n,
pulse_i => (aux(0)),
extended_o => led_red_o);
led_tx_act_n_o <= aux(0); -- R5
led_tx_err_n_o <= aux(1); -- R8
led_rx_act_n_o <= aux(2); -- R6
led_rx_err_n_o <= aux(3); -- R9
-- spec_red_led: gc_extend_pulse
-- generic map
-- (g_width => 5000000)
-- port map
-- (clk_i => clk_100m_sys,
-- rst_n_i => rst_sys_n,
-- pulse_i => (aux(0)),
-- extended_o => led_red_o);
led_tx_act_n_o <= '1';--aux(0); -- R5
led_tx_err_n_o <= 'Z';--aux(1); -- R8
led_rx_act_n_o <= '0';--aux(2); -- R6
led_rx_err_n_o <= '0';--aux(3); -- R9
......
top/spec/synthesis_descriptor.vhd deleted 100644 → 0
View file @ 3de128f4
-------------------------------------------------------------------------------
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec_masterFIP ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20160128",
syn_username => "egousiou ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "http://svn.ohwr.org/projects/masterFIP "
);
end package synthesis_descriptor;
top/spec_mt/spec_masterfip_mt.ucf
View file @ 86ec47a0
#bank 0
NET "CLK_20M_VCXO_I" LOC = H12;
NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
NET "FMC_SCL_B" LOC = F7;
NET "FMC_SCL_B" IOSTANDARD = "LVCMOS25";
NET "FMC_SDA_B" LOC = F8;
NET "FMC_SDA_B" IOSTANDARD = "LVCMOS25";
NET "l_rst_n_i" LOC = N20;
NET "l_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "GPIO_b[1]" LOC = U16;
NET "GPIO_b[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO_b[0]" LOC = AB19;
NET "GPIO_b[0]" IOSTANDARD = "LVCMOS25";
NET "L2P_CLKN_o" LOC = K22;
NET "L2P_CLKN_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP_o" LOC = K21;
NET "L2P_CLKP_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME_o" LOC = U22;
NET "L2P_DFRAME_o" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB_o" LOC = U20;
NET "L2P_EDB_o" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY_i" LOC = U19;
NET "L2P_RDY_i" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID_o" LOC = T18;
NET "L2P_VALID_o" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY_i[0]" LOC = R20;
NET "L_WR_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY_i[1]" LOC = T22;
NET "L_WR_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN_i" LOC = M19;
NET "P2L_CLKN_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP_i" LOC = M20;
NET "P2L_CLKP_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME_i" LOC = J22;
NET "P2L_DFRAME_i" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY_o" LOC = J16;
NET "P2L_RDY_o" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID_i" LOC = L19;
NET "P2L_VALID_i" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY_i[0]" LOC = N16;
NET "P_RD_D_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY_i[1]" LOC = P19;
NET "P_RD_D_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY_o[0]" LOC = L15;
NET "P_WR_RDY_o[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY_o[1]" LOC = K16;
NET "P_WR_RDY_o[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ_i[0]" LOC = M22;
NET "P_WR_REQ_i[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ_i[1]" LOC = M21;
NET "P_WR_REQ_i[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR_o" LOC = J17;
NET "RX_ERROR_o" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR_i" LOC = M17;
NET "TX_ERROR_i" IOSTANDARD = "SSTL18_I";
NET "VC_RDY_i[0]" LOC = B21;
NET "VC_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY_i[1]" LOC = B22;
NET "VC_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[0]" LOC = P16;
NET "L2P_DATA_o[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[1]" LOC = P21;
NET "L2P_DATA_o[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[2]" LOC = P18;
NET "L2P_DATA_o[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[3]" LOC = T20;
NET "L2P_DATA_o[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[4]" LOC = V21;
NET "L2P_DATA_o[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[5]" LOC = V19;
NET "L2P_DATA_o[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[6]" LOC = W22;
NET "L2P_DATA_o[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[7]" LOC = Y22;
NET "L2P_DATA_o[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[8]" LOC = P22;
NET "L2P_DATA_o[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[9]" LOC = R22;
NET "L2P_DATA_o[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[10]" LOC = T21;
NET "L2P_DATA_o[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[11]" LOC = T19;
NET "L2P_DATA_o[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[12]" LOC = V22;
NET "L2P_DATA_o[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[13]" LOC = V20;
NET "L2P_DATA_o[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[14]" LOC = W20;
NET "L2P_DATA_o[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[15]" LOC = Y21;
NET "L2P_DATA_o[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[0]" LOC = K20;
NET "P2L_DATA_i[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[1]" LOC = H22;
NET "P2L_DATA_i[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[2]" LOC = H21;
NET "P2L_DATA_i[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[3]" LOC = L17;
NET "P2L_DATA_i[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[4]" LOC = K17;
NET "P2L_DATA_i[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[5]" LOC = G22;
NET "P2L_DATA_i[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[6]" LOC = G20;
NET "P2L_DATA_i[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[7]" LOC = K18;
NET "P2L_DATA_i[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[8]" LOC = K19;
NET "P2L_DATA_i[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[9]" LOC = H20;
NET "P2L_DATA_i[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[10]" LOC = J19;
NET "P2L_DATA_i[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[11]" LOC = E22;
NET "P2L_DATA_i[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[12]" LOC = E20;
NET "P2L_DATA_i[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[13]" LOC = F22;
NET "P2L_DATA_i[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[14]" LOC = F21;
NET "P2L_DATA_i[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[15]" LOC = H19;
NET "P2L_DATA_i[15]" IOSTANDARD = "SSTL18_I";
NET "LED_RED_O" LOC = D5;
NET "LED_RED_O" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN_O" LOC = E5;
NET "LED_GREEN_O" IOSTANDARD = "LVCMOS25";
NET "dac_cs_n_o[0]" LOC = A3;
NET "dac_cs_n_o[0]" IOSTANDARD = "LVCMOS25";
......@@ -167,20 +152,16 @@ NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc_prsnt_m2c_l_i" LOC = AB14;
NET "fmc_prsnt_m2c_l_i" IOSTANDARD = "LVCMOS25";
NET "fmc_prsnt_m2c_n_i" LOC = AB14;
NET "fmc_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot
#----------------------------------------
NET "mezz_onewire_b" LOC = "C18";
NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fmc_onewire_b" LOC = "C18";
NET "fmc_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
......@@ -254,11 +235,11 @@ NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_n_o" LOC = W10;
NET "led_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_act_n_o" LOC = W10;
NET "led_sync_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_out_of_sync_n_o" LOC = Y10;
NET "led_out_of_sync_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_err_n_o" LOC = Y10;
NET "led_sync_err_n_o" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2015/07/27
......@@ -266,10 +247,10 @@ NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "cmp_mock_turtle/U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_mock_turtle/U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "l_rst_n" TIG;
NET "cmp_mock_turtle/U_GN4124_Core/rst_*" TIG;
\ No newline at end of file
NET "l_rst_n_i" TIG;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
\ No newline at end of file
top/spec_mt/spec_masterfip_mt.vhd
View file @ 86ec47a0
--_________________________________________________________________________________________________
-- |
-- |Mock Turtle SPEC masterFIP| |
-- |SPEC masterFIP| |
-- |
-- CERN, BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- spec_masterfip_mt |
-- spec_masterfip |
-- |
---------------------------------------------------------------------------------------------------
-- File spec_masterfip.vhd |
-- |
-- Standard VHDL'93 |
-- |
-- Description Top level of the masterFIP design on a SPEC carrier. |
-- Figure 1 shows the architecture of the unit......
-- |
-- Figure 1 shows the architecture of the unit......
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Tomasz Włostowski (Tomasz.Włostowski@cern.ch |
-- Date 02/2016 |
-- |
---------------------------------------------------------------------------------------------------
......@@ -48,299 +42,316 @@ use work.spec_node_pkg.all;
use work.wrn_mqueue_pkg.all;
use work.wr_node_pkg.all;
use work.masterFIP_pkg.all;
use work.mrfip_wbgen2_pkg.all;
use work.masterfip_wbgen2_pkg.all;
use work.gencores_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity spec_masterfip_mt is
generic (g_simulation : boolean := false);
port
(-- Clocks
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic;
-- GENNUM interface
L_RST_N : in std_logic; -- local bus reset
gpio : inout std_logic_vector(1 downto 0); -- general purpose interface
p2l_rdy : out std_logic; -- pcie to local [inbound data] - rx
p2l_clkn : in std_logic;
p2l_clkp : in std_logic;
p2l_data : in std_logic_vector(15 downto 0);
p2l_dframe : in std_logic;
p2l_valid : in std_logic;
p_wr_req : in std_logic_vector(1 downto 0); -- inbound buffer request/status
p_wr_rdy : out std_logic_vector(1 downto 0);
rx_error : out std_logic;
l2p_data : out std_logic_vector(15 downto 0);-- local to parallel [outbound data] - tx
l2p_dframe : out std_logic;
l2p_valid : out std_logic;
l2p_clkn : out std_logic;
l2p_clkp : out std_logic;
l2p_edb : out std_logic;
l2p_rdy : in std_logic; -- outbound buffer status
l_wr_rdy : in std_logic_vector(1 downto 0);
p_rd_d_rdy : in std_logic_vector(1 downto 0);
tx_error : in std_logic;
vc_rdy : in std_logic_vector(1 downto 0);
-- SPEC LEDs
led_red : out std_logic;
led_green : out std_logic;
-- SPEC EEPROM (driven by the MT core)
fmc_scl_b : inout std_logic;
fmc_sda_b : inout std_logic;
-- SPEC 1-wire (driven by the MT core)
carrier_onewire_b : inout std_logic;
fmc_prsnt_m2c_l_i : in std_logic;
-- WorldFIP bus speed
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
-- Mezzanine 1-wire
mezz_onewire_b : inout std_logic;
-- WorldFIP external synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enable 50 Ohms termination of the pulse
ext_sync_dir_o : out std_logic; -- transceiver direction
ext_sync_oe_n_o : out std_logic; -- transceiver output enable
ext_sync_tst_n_o : out std_logic; -- emulation of the LEMO input
ext_sync_i : in std_logic; -- sync pulse
-- WorldFIP FielDrive
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
-- WorldFIP diagnostics ADC power supplies
(-- Carrier signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference,
clk_125m_pllref_n_i : in std_logic; -- used in MT to generate 100 MHz
-- GENNUM interface
l_rst_n_i : in std_logic; -- reset from GENNUM (RSTOUT18_N)
gpio_b : inout std_logic_vector(1 downto 0); -- general purpose interface
-- -- PCIe to Local [Inbound Data] - RX
p2l_rdy_o : out std_logic; -- rx buffer full flag
p2l_clkn_i : in std_logic; -- receiver source synch clock-
p2l_clkp_i : in std_logic; -- receiver source synch clock+
p2l_data_i : in std_logic_vector(15 downto 0);-- parallel receive data
p2l_dframe_i : in std_logic; -- receive frame
p2l_valid_i : in std_logic; -- receive data valid
-- -- Inbound Buffer Request/Status
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe write request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe write ready
rx_error_o : out std_logic; -- receive error
-- -- Local to Parallel [Outbound Data] - TX
l2p_data_o : out std_logic_vector(15 downto 0);-- parallel transmit data
l2p_dframe_o : out std_logic; -- transmit data frame
l2p_valid_o : out std_logic; -- transmit data valid
l2p_clkn_o : out std_logic; -- transmitter source synch clock-
l2p_clkp_o : out std_logic; -- transmitter source synch clock+
l2p_edb_o : out std_logic; -- packet termination and discard
-- -- Outbound Buffer Status
l2p_rdy_i : in std_logic; -- tx buffer full flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local read resp data ready
tx_error_i : in std_logic; -- transmit error
vc_rdy_i : in std_logic_vector(1 downto 0); -- channel ready
-- DAC I2C (driven by MT for max stability on the 100 MHz clk)
dac_cs_n_o : out std_logic_vector(1 downto 0); -- 0: select SPEC 25MHz OSC5 VCXO
dac_sclk_o : out std_logic; -- 1: select SPEC 20MHz OSC1 VCXO
dac_din_o : out std_logic;
-- SPEC LEDs
led_red_o : out std_logic;
led_green_o : out std_logic;
-- FMC signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FMC presence
fmc_prsnt_m2c_n_i : in std_logic; -- FMC presence (used by MT)
-- FMC 1-wire
fmc_onewire_b : inout std_logic; -- temper and unique id
-- WorldFIP bus speed -- 31K25bps: speed_b1=0, speed_b0=0
speed_b0_i : in std_logic; -- 1Mbps : speed_b1=0, speed_b0=1
speed_b1_i : in std_logic; -- 2M5bps : speed_b1=1, speed_b0=0
-- 5Mbps : speed_b1=1, speed_b0=1
-- WorldFIP FielDrive
fd_rstn_o : out std_logic; -- reset
fd_rxcdn_i : in std_logic; -- rx carrier detect
fd_rxd_i : in std_logic; -- rx data
fd_txer_i : in std_logic; -- tx error
fd_wdgn_i : in std_logic; -- tx watchdog
fd_txck_o : out std_logic; -- tx clk
fd_txd_o : out std_logic; -- tx data
fd_txena_o : out std_logic; -- tx enable
-- External synchronisation pulse (input signal and transceiver control)
ext_sync_term_en_o : out std_logic; -- enable 50 Ohm termin of the pulse
ext_sync_dir_o : out std_logic := '0'; -- direction fixed B -> A
ext_sync_oe_n_o : out std_logic := '0'; -- output fixed to enabled
ext_sync_i : in std_logic; -- sync pulse
-- FMC Front panel LEDs
led_rx_act_n_o : out std_logic;
led_rx_err_n_o : out std_logic;
led_tx_act_n_o : out std_logic;
led_tx_err_n_o : out std_logic;
led_sync_act_n_o : out std_logic;
led_sync_err_n_o : out std_logic;
-- To be removed on hw V3
ext_sync_tst_n_o : out std_logic;
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
adc_prim_conn_n_o : out std_logic;
adc_sec_conn_n_o : out std_logic;
-- DAC configuration (so that the MT-generated 100 MHz clk has its max stability)
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
-- WorldFIP LEDs
led_tx_err_n_o : out std_logic;
led_tx_act_n_o : out std_logic;
led_rx_err_n_o : out std_logic;
led_rx_act_n_o : out std_logic;
led_out_of_sync_n_o : out std_logic;
led_sync_n_o : out std_logic);
adc_sec_conn_n_o : out std_logic);
end spec_masterfip_mt;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of spec_masterfip_mt is
-- Mock Turtle constants
-- eva: check comments on the WRNC..
-- HMQ out : 6
-- HMQ in : 2
constant c_hmq_config : t_wrn_mqueue_config :=
(out_slot_count => 8,
out_slot_config =>
(0 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP periodic consumed variables
1 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP aperiodic consumed variables
2 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP aperiodic messages
3 => (width => 128, entries => 4), -- output of the MT CPU1 with WorldFIP SMMPS periodic variables
4 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP SMMPS aperiodic variables
5 => (width => 128, entries => 4), -- output of the MT CPU0 with IRQs to the application (variable/messages programmed with an irq flag)
6 => (width => 128, entries => 4), -- output of the MT CPU0 command response
7 => (width => 128, entries => 4), -- output of the MT CPU1 command response
others => (0, 0)),
in_slot_count => 2,
in_slot_config =>
(0 => (width => 128, entries => 4), -- input to MT CPU0 with commands from the host for the bus configuration (commands like: PROGRAM_BA,HW_RESET, BA_START, BA_RUNNING)
1 => (width => 128, entries => 4), -- input to MT CPU1 with commands from the host for the control of CPU0 (handles commands like: BA_STOP,SET_VAR_PAYLOAD, SET_MSG_PAYLOAD, GET_REPORT, GET_PRESENT_LIST, GET_IDENT_VAR)
-- (change of payload, stop BA, reset CPU0 etc through shared mem, host asking for report)
others => (0, 0)));
-- RMQs not used
constant c_rmq_config : t_wrn_mqueue_config :=
---------------------------------------------------------------------------------------------------
-- Mock Turtle CONSTANTS --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- HMQ
constant C_HMQ_CONFIG : t_wrn_mqueue_config :=
(out_slot_count => 8,
out_slot_config =>
(0 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP period cons vars
1 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP aperiod cons vars
2 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP aperiod msgs
3 => (width => 128, entries => 4), -- output of the MT CPU1 with WorldFIP SMMPS period vars
4 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP SMMPS aperiod vars
5 => (width => 128, entries => 4), -- output of the MT CPU0 with IRQs to the application (var/msg programmed with an irq flag)
6 => (width => 128, entries => 4), -- output of the MT CPU0 command-response
7 => (width => 128, entries => 4), -- output of the MT CPU1 command-response
others => (0, 0)),
in_slot_count => 2,
in_slot_config =>
(0 => (width => 128, entries => 4), -- input to MT CPU0 with commands from the host for the bus config (commands like: PROGRAM_BA, HW_RESET, BA_START, BA_RUNNING)
1 => (width => 128, entries => 4), -- input to MT CPU1 with commands from the host for the control of CPU0 (commands like: BA_STOP, SET_VAR_PAYLOAD, SET_MSG_PAYLOAD, GET_REPORT, GET_PRESENT_LIST, GET_IDENT_VAR)
others => (0, 0))); -- (change of payload, stop BA, reset CPU0 etc through shared mem, host asking for report)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- RMQs not used!
constant C_RMQ_CONFIG : t_wrn_mqueue_config :=
(out_slot_count => 0,
out_slot_config => (others => (0, 0)),
in_slot_count => 0,
in_slot_config => (others => (0, 0)));
constant c_node_config : t_wr_node_config :=
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
constant C_NODE_CONFIG : t_wr_node_config :=
(app_id => x"0f1dc03e",
cpu_count => 2,
cpu_memsizes => (65536+32768, 8192, 0, 0, 0, 0, 0, 0), -- bytes
hmq_config => c_hmq_config,
rmq_config => c_rmq_config,
shared_mem_size => 65536); -- bytes
cpu_memsizes => (65536+32768, 8192, 0, 0, 0, 0, 0, 0), -- in bytes
hmq_config => C_HMQ_CONFIG,
rmq_config => C_RMQ_CONFIG,
shared_mem_size => 65536); -- in bytes
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- crossbar constants
constant c_slave_addr : t_wishbone_address_array(0 downto 0):= ( 0 => x"00000000" );
constant c_slave_mask : t_wishbone_address_array(0 downto 0):= ( 0 => x"00000000" );
constant C_SLAVE_ADDR : t_wishbone_address_array(0 downto 0):= ( 0 => x"00000000" );
constant C_SLAVE_MASK : t_wishbone_address_array(0 downto 0):= ( 0 => x"00000000" );
-- clock, reset
signal clk_sys : std_logic;
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- clk, reset
signal clk_100m_sys : std_logic;
signal rst_n_sys, rst_sys : std_logic;
-- Mock Turtle
signal fmc_dp_wb_out : t_wishbone_master_out_array(0 to 1);
signal fmc_dp_wb_in : t_wishbone_master_in_array(0 to 1);
signal fmc_core_wb_out : t_wishbone_master_out_array(0 to 2);
signal fmc_core_wb_in : t_wishbone_master_in_array(0 to 2);
signal fmc_wb_muxed_out : t_wishbone_master_out;
signal fmc_wb_muxed_in : t_wishbone_master_in;
signal cpu0_gpio_oen : std_logic_vector(31 downto 0);
signal cpu0_gpio_out : std_logic_vector(31 downto 0);
signal cpu0_gpio_in : std_logic_vector(31 downto 0);
-- keep VHDL happy... :-(
signal dummy : std_logic_vector(31 downto 0);
signal dummy2 : std_logic_vector(31 downto 0);
-- LEDs
signal led_clk_40m_divider : unsigned(22 downto 0);
signal led_clk_40m_aux : std_logic_vector(7 downto 0);
signal led_divider : unsigned(22 downto 0);
signal spec_led : std_logic_vector(7 downto 0);
signal rx_err, rx_act, fd_txena : std_logic;
signal aux : std_logic_vector(7 downto 0);
signal leds : std_logic_vector(31 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Fixed signals --
---------------------------------------------------------------------------------------------------
ext_sync_dir_o <= '0'; -- Direction fixed to: B -> A
ext_sync_oe_n_o <= '0'; -- Output fixed to: enabled
-- To be removed on hw V3
ext_sync_tst_n_o <= 'Z'; -- OFF
adc_prim_conn_n_o <= 'Z'; -- OFF
adc_sec_conn_n_o <= 'Z'; -- OFF
adc_1v8_shdn_n_o <= '0'; -- OFF
adc_m5v_shdn_n_o <= '0'; -- OFF
adc_5v_en_n_o <= '1'; -- OFF
---------------------------------------------------------------------------------------------------
-- Mock Turtle core --
---------------------------------------------------------------------------------------------------
cmp_mock_turtle : spec_node_template
generic map
(g_simulation => g_simulation,
g_with_wr_phy => false,
g_with_wr_phy => false, -- no White Rabbit support, dah
g_with_white_rabbit => false,
g_double_wrnode_core_clock => false,
g_system_clock_freq => 100000000, -- both CPUs at 100 MHz
g_wr_node_config => c_node_config)
g_system_clock_freq => 100000000, -- both CPUs at 100 MHz
g_wr_node_config => C_NODE_CONFIG)
port map
(rst_n_sys_o => rst_n_sys,
clk_sys_o => clk_sys,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
(clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
rst_n_sys_o => rst_n_sys, -- PCIe rst, synced with clk_sys
clk_sys_o => clk_100m_sys, -- 100 MHz; one clk domain in the whole design
-- PCIe interface
l_rst_n => l_rst_n,
gpio => gpio,
p2l_rdy => p2l_rdy,
p2l_clkn => p2l_clkn,
p2l_clkp => p2l_clkp,
p2l_data => p2l_data,
p2l_dframe => p2l_dframe,
p2l_valid => p2l_valid,
p_wr_req => p_wr_req,
p_wr_rdy => p_wr_rdy,
rx_error => rx_error,
l2p_data => l2p_data,
l2p_dframe => l2p_dframe,
l2p_valid => l2p_valid,
l2p_clkn => l2p_clkn,
l2p_clkp => l2p_clkp,
l2p_edb => l2p_edb,
l2p_rdy => l2p_rdy,
l_wr_rdy => l_wr_rdy,
p_rd_d_rdy => p_rd_d_rdy,
tx_error => tx_error,
vc_rdy => vc_rdy,
led_red => led_red,
led_green => led_green,
sfp_mod_def0_b => dummy2(0),
-- FMC EEPROM
fmc_scl_b => fmc_scl_b,
fmc_sda_b => fmc_sda_b,
-- SPEC other signals
carrier_onewire_b => carrier_onewire_b,
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_l_i,
-- WISHBONE connection of the masterFIP_core to the CPUs
dp_master_o(0) => fmc_dp_wb_out(0),
dp_master_o(1) => fmc_dp_wb_out(1),
dp_master_i(0) => fmc_dp_wb_in(0),
dp_master_i(1) => fmc_dp_wb_in(1),
-- other
fmc0_clk_aux_i => '0',
fmc0_host_irq_i => '0');
-----------------------------------------------------
rst_sys <= not rst_n_sys;
l_rst_n => l_rst_n_i,
gpio => gpio_b,
p2l_rdy => p2l_rdy_o,
p2l_clkn => p2l_clkn_i,
p2l_clkp => p2l_clkp_i,
p2l_data => p2l_data_i,
p2l_dframe => p2l_dframe_i,
p2l_valid => p2l_valid_i,
p_wr_req => p_wr_req_i,
p_wr_rdy => p_wr_rdy_o,
rx_error => rx_error_o,
l2p_data => l2p_data_o,
l2p_dframe => l2p_dframe_o,
l2p_valid => l2p_valid_o,
l2p_clkn => l2p_clkn_o,
l2p_clkp => l2p_clkp_o,
l2p_edb => l2p_edb_o,
l2p_rdy => l2p_rdy_i,
l_wr_rdy => l_wr_rdy_i,
p_rd_d_rdy => p_rd_d_rdy_i,
tx_error => tx_error_i,
vc_rdy => vc_rdy_i,
-- DAC interface
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o,
dac_cs1_n_o => dac_cs_n_o(0),
dac_cs2_n_o => dac_cs_n_o(1),
-- FMC presence
fmc_prsnt_m2c_l_i => fmc_prsnt_m2c_n_i,
-- WISHBONE connection of the fmc_masterFIP_core to the MT CPUs
dp_master_o(0) => fmc_core_wb_out(0), -- access from MT CPU0 at base address 100'000
dp_master_o(1) => fmc_core_wb_out(1),
dp_master_i(0) => fmc_core_wb_in(0), -- access from MT CPU1 at base address 100'000
dp_master_i(1) => fmc_core_wb_in(1),
-- WISHBONE connection of the fmc_masterFIP_core to the host
fmc0_host_wb_o => fmc_core_wb_out(2), -- access from PCIe host at base address 10'000
fmc0_host_wb_i => fmc_core_wb_in(2),
fmc0_host_irq_i => '0',
-- not used
clk_20m_vcxo_i => '0',
clk_125m_gtp_n_i => '0',
clk_125m_gtp_p_i => '1');
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
rst_sys <= not rst_n_sys;
---------------------------------------------------------------------------------------------------
-- Crossbar to masterFIP core --
---------------------------------------------------------------------------------------------------
-- crossbar to give access to the masterFIP_core to both CPU0 abnd CPU1
-- CPU1 will only be accessing the mf_dbg register only for debugging purposes
-- Crossbar to give access to the fmc_masterFIP_core to CPU0, CPU1 and directly to the PCIe host.
-- Note that to give access to the fmc_masterFIP_core to both CPU0 and CPU1, the SP of MT could
-- have been used instead of the DP and this crossbar; this though would have also affected
-- (potentially slowed down) the accesses to the MT Shared Memory.
-- Note also that CPU1 is only accessing the masterfip_leds register for debugging purposes.
-- The PCIe host is accessing the core directly only for testing purposes.
cmp_xwb_crossbar : xwb_crossbar
generic map
(g_num_masters => 2,
(g_num_masters => 3,
g_num_slaves => 1,
g_registered => true,
g_address => c_slave_addr,
g_mask => c_slave_mask)
g_address => C_SLAVE_ADDR,
g_mask => C_SLAVE_MASK)
port map
(clk_sys_i => clk_sys,
(clk_sys_i => clk_100m_sys,
rst_n_i => rst_n_sys,
slave_i(0) => fmc_dp_wb_out(0),
slave_i(1) => fmc_dp_wb_out(1),
slave_o(0) => fmc_dp_wb_in(0),
slave_o(1) => fmc_dp_wb_in(1),
slave_i(0) => fmc_core_wb_out(0),
slave_i(1) => fmc_core_wb_out(1),
slave_i(2) => fmc_core_wb_out(2),
slave_o(0) => fmc_core_wb_in(0),
slave_o(1) => fmc_core_wb_in(1),
slave_o(2) => fmc_core_wb_in(2),
master_o(0) => fmc_wb_muxed_out,
master_i(0) => fmc_wb_muxed_in);
master_i(0) => fmc_wb_muxed_in);
---------------------------------------------------------------------------------------------------
-- masterFIP core --
---------------------------------------------------------------------------------------------------
cmp_masterFIP_core : fmc_masterFIP_core
generic map
generic map
(g_span => 32,
g_width => 32,
values_for_simul => g_simulation)
port map
(clk_i => clk_sys,
rst_i => rst_sys,
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_n_sys,
-- FMC one-wire
onewire_b => fmc_onewire_b,
-- WorldFIP speed
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- FIELDRIVE
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_rxcdn_a_i => fd_rxcdn_i,
fd_rxd_a_i => fd_rxd_i,
fd_txer_a_i => fd_txer_i,
fd_wdgn_a_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena,
-- External Synch pulse
fd_txena_o => fd_txena_o,
-- External Synch
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_dir_o => ext_sync_dir_o,
ext_sync_oe_n_o => ext_sync_oe_n_o,
ext_sync_tst_n_o => ext_sync_tst_n_o,
ext_sync_i => ext_sync_i,
-- ADC relays and supplies
adc_1v8_shdn_n_o => adc_1v8_shdn_n_o,
adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
adc_5v_en_n_o => adc_5v_en_n_o,
adc_prim_conn_n_o => adc_prim_conn_n_o,
adc_sec_conn_n_o => adc_sec_conn_n_o,
-- DAC configuration
dac_cs_n_o => dac_cs_n_o,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o,
-- Mezzanine one-wire
onewire_b => mezz_onewire_b,
-- WISHBONE interface with
ext_sync_a_i => ext_sync_i,
ext_sync_dir_o => open, -- hard-wired to '0'
ext_sync_oe_n_o => open, -- hard-wired to '0'
-- LEDs
leds_o => leds,
-- WISHBONE interface with MT CPU0 and CPU1
wb_adr_i => fmc_wb_muxed_out.adr,
wb_dat_i => fmc_wb_muxed_out.dat,
wb_stb_i => fmc_wb_muxed_out.stb,
......@@ -349,65 +360,43 @@ begin
wb_sel_i => fmc_wb_muxed_out.sel,
wb_dat_o => fmc_wb_muxed_in.dat,
wb_ack_o => fmc_wb_muxed_in.ack,
wb_stall_o => fmc_wb_muxed_in.stall,
-- Aux
aux_o => aux);
-----------------------------------------------------
wb_stall_o => fmc_wb_muxed_in.stall);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- unused WISHBONE signals
fmc_wb_muxed_in.err <= '0';
fmc_wb_muxed_in.rty <= '0';
fmc_wb_muxed_in.int <= '0';
fd_txena_o <= fd_txena;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
led_rx_act_n_o <= leds(0); -- probe on R6
led_rx_err_n_o <= leds(1); -- probe on R9
led_tx_act_n_o <= leds(2); -- probe on R5
led_tx_err_n_o <= leds(3); -- probe on R8
led_sync_act_n_o <= leds(4); -- probe on R7
led_sync_err_n_o <= leds(5); -- probe on R2
---------------------------------------------------------------------------------------------------
-- SPEC front panel LEDs --
---------------------------------------------------------------------------------------------------
cmp_rx_err_extend_p : gc_extend_pulse
generic map (g_width => 50000)
port map
(clk_i => clk_sys,
rst_n_i => rst_n_sys,
pulse_i => aux(2),
extended_o => rx_err);
cmp_rx_act_extend_p : gc_extend_pulse
generic map (g_width => 50000)
port map
(clk_i => clk_sys,
rst_n_i => rst_n_sys,
pulse_i => aux(1),
extended_o => rx_act);
clk_40m_sys_drive_led: process (clk_sys)
drive_led_clk_sys: process (clk_100m_sys)
begin
if rising_edge(clk_sys) then
if rising_edge(clk_100m_sys) then
if(rst_n_sys = '0') then
led_clk_40m_aux <= "01111111";
led_clk_40m_divider <= (others => '0');
spec_led <= "01111111";
led_divider <= (others => '0');
else
led_clk_40m_divider <= led_clk_40m_divider+ 1;
if(led_clk_40m_divider = 0) then
led_clk_40m_aux <= led_clk_40m_aux(6 downto 0) & led_clk_40m_aux(7);
led_divider <= led_divider+ 1;
if(led_divider = 0) then
spec_led <= spec_led(6 downto 0) & spec_led(7);
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- masterFIP LEDs --
---------------------------------------------------------------------------------------------------
led_tx_act_n_o <= aux(0); -- probe on R5
led_tx_err_n_o <= aux(1); -- probe on R8
led_rx_act_n_o <= aux(2); -- probe on R6
led_rx_err_n_o <= aux(3); -- probe on R9
led_out_of_sync_n_o <= aux(4); -- probe on R7
led_sync_n_o <= aux(5); -- probe on R2
-- led_tx_err_n_o <= led_clk_40m_aux(0);
-- led_tx_err_n_o <= fd_txer_i;
-- led_tx_act_n_o <= fd_txena;
-- led_rx_err_n_o <= rx_err;
-- led_rx_act_n_o <= rx_act;
led_green_o <= spec_led(7);
led_red_o <= not rst_n_sys;
end rtl;
----------------------------------------------------------------------------------------------------
......
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