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MasterFIP - Gateware
Commit 88588a39 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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ise projects update

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Showing with 31 additions and 27 deletions
syn/spec/spec_masterfip.xise
View file @ 88588a39
...@@ -1324,8 +1324,8 @@ ...@@ -1324,8 +1324,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_onewire_interf" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_onewire_interf" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
...@@ -1348,7 +1348,7 @@ ...@@ -1348,7 +1348,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_onewire_interf" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_masterFIP" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
syn/spec_mt/spec_masterfip_mt.xise
View file @ 88588a39
...@@ -549,7 +549,7 @@ ...@@ -549,7 +549,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="99"/> <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/> <association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/> <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
...@@ -594,7 +594,7 @@ ...@@ -594,7 +594,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="92"/> <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file> </file>
<file xil_pn:name="../../rtl/fmc_masterfip_csr.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/fmc_masterfip_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="184"/> <association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/> <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
...@@ -627,7 +627,7 @@ ...@@ -627,7 +627,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="90"/> <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/> <association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/> <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
...@@ -642,7 +642,7 @@ ...@@ -642,7 +642,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/> <association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_framer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_tx_framer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/> <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
...@@ -654,10 +654,10 @@ ...@@ -654,10 +654,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="149"/> <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file> </file>
<file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="185"/> <association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/> <association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/> <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
...@@ -666,10 +666,10 @@ ...@@ -666,10 +666,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_core_with_etherbone.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_core_with_etherbone.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="188"/> <association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/> <association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_csr_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_csr_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="133"/> <association xil_pn:name="Implementation" xil_pn:seqID="133"/>
...@@ -729,7 +729,7 @@ ...@@ -729,7 +729,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="16"/> <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="186"/> <association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file> </file>
<file xil_pn:name="../../rtl/from_nanofip/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/from_nanofip/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/> <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
...@@ -852,7 +852,7 @@ ...@@ -852,7 +852,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/> <association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/> <association xil_pn:name="Implementation" xil_pn:seqID="124"/>
...@@ -936,7 +936,7 @@ ...@@ -936,7 +936,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_template.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_template.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/> <association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...@@ -984,7 +984,7 @@ ...@@ -984,7 +984,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file> </file>
<file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="183"/> <association xil_pn:name="Implementation" xil_pn:seqID="184"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...@@ -1017,7 +1017,7 @@ ...@@ -1017,7 +1017,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="78"/> <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file> </file>
<file xil_pn:name="../../rtl/masterfip_rx.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/masterfip_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="182"/> <association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/> <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
...@@ -1059,10 +1059,10 @@ ...@@ -1059,10 +1059,10 @@
<association xil_pn:name="Implementation" xil_pn:seqID="88"/> <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/> <association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file> </file>
<file xil_pn:name="../../rtl/fmc_masterFIP_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/fmc_masterFIP_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/> <association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...@@ -1134,7 +1134,7 @@ ...@@ -1134,7 +1134,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="178"/> <association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/> <association xil_pn:name="Implementation" xil_pn:seqID="188"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/> <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
...@@ -1206,7 +1206,7 @@ ...@@ -1206,7 +1206,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="128"/> <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file> </file>
<file xil_pn:name="../../rtl/masterfip_tx.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/masterfip_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="181"/> <association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="137"/> <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
...@@ -1306,12 +1306,16 @@ ...@@ -1306,12 +1306,16 @@
</file> </file>
<file xil_pn:name="../../top/spec_mt/spec_masterfip_mt.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../top/spec_mt/spec_masterfip_mt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="339"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="339"/>
<association xil_pn:name="Implementation" xil_pn:seqID="198"/> <association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file> </file>
<file xil_pn:name="../../top/spec_mt/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../top/spec_mt/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="340"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="340"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../rtl/onewire_interf.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="355"/>
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
......
top/spec_mt/spec_masterfip_mt.vhd
View file @ 88588a39
...@@ -391,12 +391,12 @@ begin ...@@ -391,12 +391,12 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- masterFIP LEDs -- -- masterFIP LEDs --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
led_tx_act_n_o <= aux(0); -- R5 led_tx_act_n_o <= aux(0); -- probe on R5
led_tx_err_n_o <= aux(1); -- R8 led_tx_err_n_o <= aux(1); -- probe on R8
led_rx_act_n_o <= aux(2); -- R6 led_rx_act_n_o <= aux(2); -- probe on R6
led_rx_err_n_o <= aux(3); -- R9 led_rx_err_n_o <= aux(3); -- probe on R9
led_out_of_sync_n_o <= aux(4); -- R7 led_out_of_sync_n_o <= aux(4); -- probe on R7
led_sync_n_o <= aux(5); -- R2 led_sync_n_o <= aux(5); -- probe on R2
-- led_tx_err_n_o <= led_clk_40m_aux(0); -- led_tx_err_n_o <= led_clk_40m_aux(0);
-- led_tx_err_n_o <= fd_txer_i; -- led_tx_err_n_o <= fd_txer_i;
-- led_tx_act_n_o <= fd_txena; -- led_tx_act_n_o <= fd_txena;
......
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