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MasterFIP - Gateware
Commit a6c43633 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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added fd_cdn register; added wbgen2_pkg; restructuring

parent bf741228
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rtl/fmc_masterFIP_core.vhd
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rtl/fmc_masterfip_csr.vhd
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rtl/masterFIP_pkg.vhd
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rtl/masterfip_rx.vhd
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...@@ -302,15 +302,27 @@ begin ...@@ -302,15 +302,27 @@ begin
rx_frame_o <= (others =>(others =>'0')); rx_frame_o <= (others =>(others =>'0'));
else else
-- upon rx_fss_crc_fes_ok_p, the last 32bit word will contain for sure CRC0 and CRC1
-- and it may also contain one or two bytes of data.
-- the last word will always include as last bytes, byte1 and byte0: the two CRC bytes.
-- it could also include one or two useful data bytes
if rx_fss_crc_fes_ok_p = '1' then if rx_fss_crc_fes_ok_p = '1' then
-- upon rx_fss_crc_fes_ok_p, the last 32bit word will contain for sure CRC0, CRC1 and FES if word32_num = 0 then -- only in the case of RP_FIN, where there are not enough bytes to create a word; needed for keeping the MT sw generic
-- and it may also contain up to one byte of data.
if (rx_byte_index-3) mod 4 = 1 then
word32_num <= word32_num + 1; word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3; -- byte3 is the data byte; the other ones can be "0" rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3; --
elsif (rx_byte_index-2) mod 4 = 3 then -- [CRC|CRC|BYTE|BYTE]
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3; -- byte 3 and byte 2 are useful
elsif (rx_byte_index-2) mod 4 = 2 then -- [0|CRC|CRC|BYTE]
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= "00000000" & byte0 & byte1 & byte2;-- one useful data byte: byte2 last byte
-- for [CRC|BYTE|BYTE|BYTE] upon rx_fss_crc_fes_ok_p a new word has been created
end if; end if;
elsif (rx_byte_ready_p = '1' and (rx_byte_index_d1) > 0 and (rx_byte_index_d1) mod 4 = 0) then -- for all the other bytes
elsif (rx_byte_ready_p = '1' and (rx_byte_index_d1) > 0 and (rx_byte_index_d1) mod 4 = 0) then
word32_num <= word32_num + 1; word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3; rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3;
end if; end if;
...@@ -318,6 +330,7 @@ begin ...@@ -318,6 +330,7 @@ begin
end if; end if;
end process; end process;
rx_word_index_o <= std_logic_vector(to_unsigned(word32_num,7)); rx_word_index_o <= std_logic_vector(to_unsigned(word32_num,7));
end architecture struc; end architecture struc;
......
rtl/mf_wbgen2_pkg.vhd 0 → 100644
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rtl/wbgen/fmc_masterfip_csr.h
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rtl/wbgen/fmc_masterfip_csr.htm
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rtl/wbgen/fmc_masterfip_csr.wb
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...@@ -68,6 +68,55 @@ peripheral { ...@@ -68,6 +68,55 @@ peripheral {
}; };
-------------------------------------------------------------------------------
-- one wire --
-------------------------------------------------------------------------------
reg {
name = "mezzanine temperature";
description = "raw temperature data from the one wire DS18B20U+;\
the register is 2-bytes long; it translates to oC as follows:\
temp = ((byte1 << 8) | byte0) / 16.0";
prefix = "ds1820_temper";
field {
name = "ds1820 temperature";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "mezzanine unique id lsb";
description = "id (lsb) read from the one wire DS18B20U+";
prefix = "ds1820_id_lsb";
field {
name = "ds1820 id lsb";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "mezzanine unique id msb";
description = "id (msb) read from the one wire DS18B20U+";
prefix = "ds1820_id_msb";
field {
name = "ds1820 id msb";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- ADC power supplies -- -- ADC power supplies --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -264,7 +313,7 @@ peripheral { ...@@ -264,7 +313,7 @@ peripheral {
description = "duration of the macrocycle in number of 10ns-clk-ticks"; description = "duration of the macrocycle in number of 10ns-clk-ticks";
prefix = "lgth"; prefix = "lgth";
type = SLV; type = SLV;
size = 31; size = 32;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
...@@ -288,7 +337,7 @@ peripheral { ...@@ -288,7 +337,7 @@ peripheral {
description = "turnaround time (i.e. time between two frames sent by the masterFIP) in number of 10ns-clk-ticks"; description = "turnaround time (i.e. time between two frames sent by the masterFIP) in number of 10ns-clk-ticks";
prefix = "lgth"; prefix = "lgth";
type = SLV; type = SLV;
size = 31; size = 32;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
...@@ -312,7 +361,7 @@ peripheral { ...@@ -312,7 +361,7 @@ peripheral {
description = "silence time (i.e. time that the masterFIP waits for a response frame) number of 10ns-clk-ticks"; description = "silence time (i.e. time that the masterFIP waits for a response frame) number of 10ns-clk-ticks";
prefix = "lgth"; prefix = "lgth";
type = SLV; type = SLV;
size = 31; size = 32;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
...@@ -336,7 +385,7 @@ peripheral { ...@@ -336,7 +385,7 @@ peripheral {
name = "macrocycle time counter"; name = "macrocycle time counter";
description = "current value of the macrocycle time counter"; description = "current value of the macrocycle time counter";
type = SLV; type = SLV;
size = 31; size = 32;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
...@@ -365,7 +414,7 @@ peripheral { ...@@ -365,7 +414,7 @@ peripheral {
name = "turnaround time counter"; name = "turnaround time counter";
description = "current value of the turnaround time counter"; description = "current value of the turnaround time counter";
type = SLV; type = SLV;
size = 31; size = 32;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
...@@ -379,7 +428,7 @@ peripheral { ...@@ -379,7 +428,7 @@ peripheral {
name = "silence time counter"; name = "silence time counter";
description = "current value of the silence time counter"; description = "current value of the silence time counter";
type = SLV; type = SLV;
size = 31; size = 32;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
...@@ -477,33 +526,49 @@ peripheral { ...@@ -477,33 +526,49 @@ peripheral {
-- fieldrive status signals -- -- fieldrive status signals --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
reg { reg {
name = "fieldrive wdgn"; name = "fieldrive wdgn, cdn";
prefix = "fd_wdgn"; prefix = "fd";
field { field {
name = "fd_wdgn_tstamp"; name = "fieldrive watchdog";
description = "timestamp of the moment in the macrocycle when the fd_wdgn\ description = "read 1: the fd_wdgn has been activated\
was activated.\ read 0: no problemo\
The field is automatically cleared upon a new macrocycle or\ Note that if triggered, the fd_wdgn stays active until a fd_rstn";
upon a rstn_fd or rstn_core"; prefix = "wdg";
prefix = "tstamp"; type = BIT;
type = SLV;
size = 31;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
field { field {
name = "fd_wdg_act"; name = "fieldrive carrier detect";
description = "read 1: the fd_wdgn has been activated\ description = "read 1: carrier detect active\
read 0: no problemo\ read 0: no bus traffic";
Note that if triggered, the fd_wdgn stays active until a fd_rstn"; prefix = "cd";
prefix = "act";
type = BIT; type = BIT;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
}; };
reg {
name = "fieldrive wdg timestamp";
prefix = "fd_wdg_tstamp";
field {
name = "fd_wdgn_tstamp";
description = "timestamp of the moment in the macrocycle when the fd_wdg\
was activated.\
The field is automatically cleared upon a new macrocycle or\
upon a rstn_fd or rstn_core";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg { reg {
name = "fieldrive txer cnt"; name = "fieldrive txer cnt";
prefix = "fd_txer_cnt"; prefix = "fd_txer_cnt";
...@@ -533,14 +598,14 @@ peripheral { ...@@ -533,14 +598,14 @@ peripheral {
The field is automatically cleared upon a new macrocycle or\ The field is automatically cleared upon a new macrocycle or\
upon a rstn_fd or rstn_core"; upon a rstn_fd or rstn_core";
type = SLV; type = SLV;
size = 31; size = 32;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
}; };
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- deserializer ctrl -- -- tx ctrl --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
reg { reg {
name = "rx ctrl"; name = "rx ctrl";
...@@ -561,7 +626,7 @@ peripheral { ...@@ -561,7 +626,7 @@ peripheral {
}; };
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- deserializer status -- -- rx status --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
reg { reg {
name = "rx status"; name = "rx status";
...@@ -604,9 +669,11 @@ peripheral { ...@@ -604,9 +669,11 @@ peripheral {
}; };
field { field {
name = "rx number of data bytes"; name = "rx number of payload bytes";
description = "number of bytes that have been received by the deserializer upon the rx_frame_ok activation\ description = "number of payload bytes that have been received by the deserializer\
note that the max WorldFIP frame size = 263 bytes (without preamble, CRC, postamble)"; upon the rx_frame_ok activation.\
The counter includes all the bytes that come after the CTRL byte and before the CRC bytes.\
note that for the max WorldFIP frame size = 262 bytes (without preamble, CTRL, CRC, postamble)";
prefix = "bytes_num"; prefix = "bytes_num";
type = SLV; type = SLV;
size = 16; size = 16;
...@@ -617,16 +684,34 @@ peripheral { ...@@ -617,16 +684,34 @@ peripheral {
}; };
reg { reg {
name = "rx status current byte index"; name = "rx current word index";
prefix = "rx_stat_curr_byte_indx"; prefix = "rx_stat_curr_word_indx";
field { field {
name = "current byte index"; name = "current word index";
description = "index of the current byte being deserialized;\ description = "index of the current 32-bit-word being deserialized;\
the counting starts from 0 after the preamble and\ word 1: LSB is the CTRL byte; the other 3 bytes are to be ignored\
it also includes the CRC and postamble bytes"; word 2: contains the first 4 payload bytes..etc\
The max frame size is 66 words.\
The last word may also include CRC bytes;\
for that, upon the rx_frame_ok, the rx_bytes_num indicates the\
exact number of payload bytes to be read";
type = SLV; type = SLV;
size = 16; size = 7;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx number of frames with CRC error";
prefix = "rx_stat_crc_err_cnt";
field {
name = "rx number of frames with CRC error";
description = "number of frames with CRC error since the startup or a core_rstn";
type = SLV;
size = 32;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
...@@ -2678,58 +2763,4 @@ peripheral { ...@@ -2678,58 +2763,4 @@ peripheral {
-------------------------------------------------------------------------------
-- one wire --
-------------------------------------------------------------------------------
reg {
name = "onewire temperature";
description = "raw temperature data from the one wire DS18B20U+;\
the register is 2-bytes long; it translates to oC as follows:\
temp = ((byte1 << 8) | byte0) / 16.0";
prefix = "onewire_temper";
field {
name = "onewire temperature";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "onewire id lsb";
description = "id (lsb) read from the one wire DS18B20U+";
prefix = "onewire_id_lsb";
field {
name = "onewire id lsb";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "onewire id msb";
description = "id (msb) read from the one wire DS18B20U+";
prefix = "onewire_id_msb";
field {
name = "onewire id msb";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
}; };
\ No newline at end of file
sim/spec/data_vectors/board_settings_config.txt
View file @ a6c43633
...@@ -7,8 +7,8 @@ sd1 -- m_id_2 can take the values (gnd, vcc, sd0, sd1) ...@@ -7,8 +7,8 @@ sd1 -- m_id_2 can take the values (gnd, vcc, sd0, sd1)
sd0 -- m_id_1 can take the values (gnd, vcc, sd0, sd1) sd0 -- m_id_1 can take the values (gnd, vcc, sd0, sd1)
vcc -- m_id_0 can take the values (gnd, vcc, sd0, sd1) vcc -- m_id_0 can take the values (gnd, vcc, sd0, sd1)
1 -- nostat: nanoFIP status enabled(0), nanoFIP status disabled(1) 1 -- nostat: nanoFIP status enabled(0), nanoFIP status disabled(1)
001 -- produced variable length: 2 bytes(000), 8 bytes(001), 16 bytes(010), 32 bytes(011), 64 bytes(100), 124 bytes(101) 000 -- produced variable length: 2 bytes(000), 8 bytes(001), 16 bytes(010), 32 bytes(011), 64 bytes(100), 124 bytes(101)
01 -- rate: 31.25 kbits(00), 1 Mbit(01), 2.5 Mbits(10) 01 -- rate: 31.25 kbits(00), 1 Mbit(01), 2.5 Mbits(10)
0 -- mode (slone): memory mode(0), stand alone(1) 0 -- mode (slone): memory mode(0), stand alone(1)
03 -- station_adr (8-bit bus in hexadecimal format) 03 -- station_adr (8-bit bus in hexadecimal format)
20000 ms -- time for which the configuration above is valid 20000 ms -- time for which the configuration above is validboard
\ No newline at end of file
sim/spec/data_vectors/masterFIP_test.vec
View file @ a6c43633
...@@ -60,110 +60,109 @@ wait %d20 ...@@ -60,110 +60,109 @@ wait %d20
--------------- ID_DAT --------------- --------------- ID_DAT ---------------
-- tx_rst -- tx_rst
wr 000000000003003C F 00000001 wr 0000000000030048 F 00000001
wait %d10 wait %d10
wr 000000000003003C F 00000000 wr 0000000000030048 F 00000000
wait %d20 wait %d20
-- control byte of id_dat -- control byte of id_dat
wr 000000000003016C F 00000003 wr 0000000000030180 F 00000003
wait %d20 wait %d20
-- data bytes varid = 0503 for agent to consume -- data bytes varid = 0503 for agent to consume
wr 0000000000030170 F 00000305 wr 0000000000030184 F 00000305
wait %d20 wait %d20
-- tx_start -- tx_start
wr 000000000003003C F 00000202 wr 0000000000030048 F 00000202
wait %d20000 wait %d20000
--------------- RP_DAT --------------- --------------- RP_DAT ---------------
-- tx_rst -- tx_rst
wr 000000000003003C F 00000001 wr 0000000000030048 F 00000001
wait %d10 wait %d10
wr 000000000003003C F 00000000 wr 0000000000030048 F 00000000
wait %d20 wait %d20
-- control byte of rp_dat -- control byte of rp_dat
wr 000000000003016C F 00000002 wr 0000000000030180 F 00000002
wait %d20 wait %d20
-- data bytes -- data bytes
wr 0000000000030170 F BBAA0940 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940 wr 0000000000030184 F BBAA0340
wait %d20 wait %d20
wr 0000000000030174 F FFEEDDCC -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC wr 0000000000030188 F EEDDCC05
wait %d20
wr 0000000000030178 F 00052B1A -- for 2 data bytes: 00000000 | for 8 data bytes: 00052B1A
wait %d20 wait %d20
-- tx_start -- tx_start
wr 000000000003003C F 00000B02 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02 wr 0000000000030048 F 00000502
wait %d20000 wait %d20000
wr 000000000003003C F 00000000 wr 0000000000030048 F 00000000
wait %d20000 wait %d20000
--------------- ID_DAT --------------- --------------- ID_DAT ---------------
-- tx_rst -- tx_rst
wr 000000000003003C F 00000001 wr 0000000000030048 F 00000001
wait %d10 wait %d10
wr 000000000003003C F 00000000 wr 0000000000030048 F 00000000
wait %d20 wait %d20
-- control byte of id_dat -- control byte of id_dat
wr 000000000003016C F 00000003 wr 0000000000030180 F 00000003
wait %d20 wait %d20
-- data bytes varid = 1403 for agent to send identification -- data bytes varid = 1403 for agent to send identification
wr 0000000000030170 F 00000314 -------------------------0314 wr 0000000000030184 F 00000310 -------------------------0314
wait %d20 wait %d20
-- tx_start -- tx_start
wr 000000000003003C F 00000202 wr 0000000000030048 F 00000202
wait %d200 wait %d200
-- deactivate tx_start -- deactivate tx_start
wr 000000000003003C F 00000000 wr 0000000000030048 F 00000000
-- release rx_rst -- release rx_rst
wr 0000000000030048 F 00000000 wr 0000000000030048 F 00000000
wait %d40000 wait %d40000
-- read received data -- read received data
rd 0000000000030054 F 00000002 rd 0000000000030070 F 00000002
wait %d20 wait %d20
rd 0000000000030048 F 03800550 rd 0000000000030048 F 03800550
wait %d40000 wait %d40000
--------------- ID_DAT --------------- --------------- ID_DAT ---------------
tx_rst tx_rst
wr 000000000003003C F 00000001 wr 0000000000030048 F 00000001
wait %d10 wait %d10
wr 000000000003003C F 00000000 wr 0000000000030048 F 00000000
wait %d20 wait %d20
-- control byte of id_dat -- control byte of id_dat
wr 000000000003016C F 00000003 wr 0000000000030180 F 00000003
wait %d20 wait %d20
-- data bytes varid = 0603 for agent to produce -- data bytes varid = 0603 for agent to produce
wr 0000000000030170 F 00000306 wr 0000000000030184 F 00000306
wait %d20 wait %d20
-- tx_start -- tx_start
wr 000000000003003C F 00000202 wr 0000000000030048 F 00000202
wait %d20 wait %d20
-- deactivate tx_start -- deactivate tx_start
wr 000000000003003C F 00000000 wr 0000000000030048 F 00000000
-- release rx_rst -- release rx_rst
wr 0000000000030048 F 00000000 wr 0000000000030048 F 00000000
wait %d40000 wait %d40000
-- read received data -- read received data
rd 0000000000030054 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF rd 0000000000030070 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
wait %d20 wait %d20
rd 0000000000030058 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF rd 0000000000030058 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
wait %d20 wait %d20
...@@ -241,7 +240,7 @@ wait %d40000 ...@@ -241,7 +240,7 @@ wait %d40000
--------------- RP_FIN --------------- --------------- RP_FIN ---------------
-- control byte of rp_fin -- control byte of rp_fin
wr 000000000003016C F 00000040 wr 0000000000030180 F 00000040
wait %d20 wait %d20
-- rx_rst -- rx_rst
...@@ -249,5 +248,5 @@ wr 0000000000030048 F 00000001 ...@@ -249,5 +248,5 @@ wr 0000000000030048 F 00000001
wait %d20 wait %d20
-- tx_start -- tx_start
wr 000000000003003C F 00000002 wr 0000000000030048 F 00000002
wait %d20000 wait %d20000
\ No newline at end of file
sim/spec/testbench/tb_masterFIP.vhd
View file @ a6c43633
...@@ -424,7 +424,7 @@ signal spare : std_logic; ...@@ -424,7 +424,7 @@ signal spare : std_logic;
signal adr : std_logic_vector(9 downto 0); signal adr : std_logic_vector(9 downto 0);
signal cyc : std_logic; signal cyc : std_logic;
signal dat_to_fip : std_logic_vector(15 downto 0); signal dat_to_fip, dat_to_fip_tmp : std_logic_vector(15 downto 0);
signal rst : std_logic := '0'; signal rst : std_logic := '0';
signal stb : std_logic; signal stb : std_logic;
...@@ -506,8 +506,8 @@ begin ...@@ -506,8 +506,8 @@ begin
port map( port map(
uclk_i => nanoFIP_clk, uclk_i => nanoFIP_clk,
c_id_i => c_id, c_id_i => "1011",
m_id_i => m_id, m_id_i => "0101",
p3_lgth_i => p3_lgth, p3_lgth_i => p3_lgth,
rate_i => rate, rate_i => rate,
subs_i => subs, subs_i => subs,
...@@ -557,6 +557,7 @@ begin ...@@ -557,6 +557,7 @@ begin
jc_tdi_o => open, jc_tdi_o => open,
jc_tck_o => open); jc_tck_o => open);
dat_to_fip <= dat_to_fip_tmp when slone = '0' else dat_from_fip;
user_logic: user_interface user_logic: user_interface
port map( port map(
...@@ -579,7 +580,7 @@ begin ...@@ -579,7 +580,7 @@ begin
adr_o => adr, adr_o => adr,
cyc_o => cyc, cyc_o => cyc,
dat_o => dat_to_fip, dat_o => dat_to_fip_tmp,
rst_o => rst, rst_o => rst,
stb_o => stb, stb_o => stb,
wclk_o => wclk, wclk_o => wclk,
......
sim/spec/testbench/user_interface.vhd
View file @ a6c43633
...@@ -40,31 +40,6 @@ end user_interface; ...@@ -40,31 +40,6 @@ end user_interface;
architecture archi of user_interface is architecture archi of user_interface is
component slone_interface
port(
launch_slone_read : in std_logic;
launch_slone_write : in std_logic;
uclk : in std_logic;
ureset : in std_logic;
dat_o : out std_logic_vector(15 downto 0);
slone_access_read : out std_logic;
slone_access_write : out std_logic
);
end component;
component slone_monitor
port(
dat_i : in std_logic_vector(15 downto 0);
dat_o : in std_logic_vector(15 downto 0);
slone_access_read : in std_logic;
slone_access_write : in std_logic;
uclk : in std_logic;
ureset : in std_logic;
var_id : in std_logic_vector(1 downto 0)
);
end component;
component user_sequencer component user_sequencer
port( port(
uclk_period : in time; uclk_period : in time;
...@@ -78,8 +53,7 @@ architecture archi of user_interface is ...@@ -78,8 +53,7 @@ architecture archi of user_interface is
p3_lgth_i : in std_logic_vector(2 downto 0); p3_lgth_i : in std_logic_vector(2 downto 0);
block_size : out std_logic_vector(6 downto 0); block_size : out std_logic_vector(6 downto 0);
launch_slone_read : out std_logic;
launch_slone_write : out std_logic;
launch_wb_read : out std_logic; launch_wb_read : out std_logic;
launch_wb_write : out std_logic; launch_wb_write : out std_logic;
transfer_length : out std_logic_vector(6 downto 0); transfer_length : out std_logic_vector(6 downto 0);
...@@ -88,23 +62,6 @@ architecture archi of user_interface is ...@@ -88,23 +62,6 @@ architecture archi of user_interface is
); );
end component; end component;
component user_access_monitor is
port(
cyc : in std_logic;
uclk_period : in time;
urstn_from_nf : in std_logic;
slone_access_read : in std_logic;
slone_access_write : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
var_id : in std_logic_vector(1 downto 0);
var1_acc_o : out std_logic;
var2_acc_o : out std_logic;
var3_acc_o : out std_logic
);
end component;
component wishbone_interface component wishbone_interface
port( port(
...@@ -244,15 +201,6 @@ begin ...@@ -244,15 +201,6 @@ begin
wait for config_validity_time - preset_length; wait for config_validity_time - preset_length;
end process; end process;
slone_output_detector: process
begin
if launch_slone_write ='1' then
slone_output <= TRUE;
elsif memory_output then
slone_output <= FALSE;
end if;
wait until uclk ='1';
end process;
memory_output_detector: process memory_output_detector: process
begin begin
...@@ -264,30 +212,6 @@ begin ...@@ -264,30 +212,6 @@ begin
wait until wclk ='1'; wait until wclk ='1';
end process; end process;
sa_interface: slone_interface
port map(
launch_slone_read => launch_slone_read,
launch_slone_write => launch_slone_write,
uclk => uclk,
ureset => ureset,
dat_o => data_from_slone,
slone_access_read => slone_access_read,
slone_access_write => slone_access_write
);
sa_monitor: slone_monitor
port map(
dat_i => dat_i,
dat_o => data_from_slone,
slone_access_read => slone_access_read,
slone_access_write => slone_access_write,
uclk => uclk,
ureset => ureset,
var_id => var_id
);
user_sequence: user_sequencer user_sequence: user_sequencer
port map( port map(
uclk_period => uclk_period, uclk_period => uclk_period,
...@@ -300,8 +224,7 @@ begin ...@@ -300,8 +224,7 @@ begin
p3_lgth_i => p3_lgth_i, p3_lgth_i => p3_lgth_i,
block_size => block_size, block_size => block_size,
launch_slone_read => launch_slone_read,
launch_slone_write => launch_slone_write,
launch_wb_read => launch_wb_read, launch_wb_read => launch_wb_read,
launch_wb_write => launch_wb_write, launch_wb_write => launch_wb_write,
transfer_length => transfer_length, transfer_length => transfer_length,
...@@ -310,22 +233,6 @@ begin ...@@ -310,22 +233,6 @@ begin
); );
user_acc_monitor: user_access_monitor
port map(
cyc => cyc,
uclk_period => uclk_period,
urstn_from_nf => urstn_from_nf,
slone_access_read => slone_access_read,
slone_access_write => slone_access_write,
var1_rdy_i => var1_rdy_i,
var2_rdy_i => var2_rdy_i,
var3_rdy_i => var3_rdy_i,
var_id => var_id,
var1_acc_o => var1_acc_o,
var2_acc_o => var2_acc_o,
var3_acc_o => var3_acc_o
);
wb_interface: wishbone_interface wb_interface: wishbone_interface
port map( port map(
...@@ -382,8 +289,13 @@ begin ...@@ -382,8 +289,13 @@ begin
stb_o <= stb; stb_o <= stb;
we_o <= we; we_o <= we;
dat_o <= data_from_slone when slone_output dat_o <= x"00" & data_from_wb when memory_output
else x"00" & data_from_wb when memory_output
else (others=>'0'); else (others=>'0');
var1_acc_o <= launch_wb_read;
var2_acc_o <= '0';
var3_acc_o <= launch_wb_write;
end archi; end archi;
sim/spec/testbench/user_sequencer.vhd
View file @ a6c43633
...@@ -32,8 +32,6 @@ entity user_sequencer is ...@@ -32,8 +32,6 @@ entity user_sequencer is
p3_lgth_i : in std_logic_vector(2 downto 0); p3_lgth_i : in std_logic_vector(2 downto 0);
block_size : out std_logic_vector(6 downto 0); block_size : out std_logic_vector(6 downto 0);
launch_slone_read : out std_logic;
launch_slone_write : out std_logic;
launch_wb_read : out std_logic; launch_wb_read : out std_logic;
launch_wb_write : out std_logic; launch_wb_write : out std_logic;
transfer_length : out std_logic_vector(6 downto 0); transfer_length : out std_logic_vector(6 downto 0);
...@@ -198,9 +196,6 @@ begin ...@@ -198,9 +196,6 @@ begin
end process; end process;
launch_slone_read <= '0'; -- slone data are automatically copied from in to out
launch_slone_write <= '0'; -- slone data are automatically copied from in to out
launch_wb_read <= var1_rdy_p;-- or var2_rdy_i; --launch_wb_rd; launch_wb_read <= var1_rdy_p;-- or var2_rdy_i; --launch_wb_rd;
launch_wb_write <= transport var1_rdy_p after 10 us; launch_wb_write <= transport var1_rdy_p after 10 us;
...@@ -222,15 +217,9 @@ begin ...@@ -222,15 +217,9 @@ begin
var_id <= "00"; -- not used var_id <= "00"; -- not used
reporting: process(launch_slone_rd, launch_slone_wr, launch_wb_rd, launch_wb_wr) reporting: process(launch_wb_rd, launch_wb_wr)
begin begin
if launch_slone_rd ='1' then if launch_wb_rd ='1' then
report LF & " User logic reads 2 bytes from the 16-bit stand-alone bus"& LF;
elsif launch_slone_wr ='1' then
report LF & " User logic writes 2 bytes on the 16-bit stand-alone bus"& LF;
elsif launch_wb_rd ='1' then
if transfer_offst = 0 then if transfer_offst = 0 then
report LF & " User logic reads " & integer'image(transfer_lgth) & report LF & " User logic reads " & integer'image(transfer_lgth) &
" bytes of user data plus the length byte and the PDU type byte" & " bytes of user data plus the length byte and the PDU type byte" &
......
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