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MasterFIP - Gateware
Commit aae395c5 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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updated testbench to support nanofip in memory mode

parent 71c1e137
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sim/spec/data_vectors/WFIP_communication_config.txt 0 → 100644
View file @ aae395c5
1 -- bit rate: 31.25 kbit/s(0), 1 Mbit/s(1), 2.5 Mbit/s(2)
10001110111001111 -- gx bit polynomial for CRC
101010101XX10XX0 -- FSS value
1XXXX101 -- FES value
03 -- id_dat frame control byte
02 -- rp_dat frame control byte
14 -- Presence Variable address
10 -- Identification Variable address
91 -- Broadcast Variable address
05 -- Consumed Variable address
06 -- Produced Variable address
E0 -- Reset Variable address
40 -- pdu_type byte
05 -- mps byte
2000 ms -- time for which the configuration above is valid
sim/spec/data_vectors/board_settings_config.txt 0 → 100644
View file @ aae395c5
vcc -- c_id_3 can take the values (gnd, vcc, sd0, sd1)
sd0 -- c_id_2 can take the values (gnd, vcc, sd0, sd1)
sd1 -- c_id_1 can take the values (gnd, vcc, sd0, sd1)
gnd -- c_id_0 can take the values (gnd, vcc, sd0, sd1)
gnd -- m_id_3 can take the values (gnd, vcc, sd0, sd1)
sd1 -- m_id_2 can take the values (gnd, vcc, sd0, sd1)
sd0 -- m_id_1 can take the values (gnd, vcc, sd0, sd1)
vcc -- m_id_0 can take the values (gnd, vcc, sd0, sd1)
1 -- nostat: nanoFIP status enabled(0), nanoFIP status disabled(1)
000 -- produced variable length: 2 bytes(000), 8 bytes(001), 16 bytes(010), 32 bytes(011), 64 bytes(100), 124 bytes(101)
01 -- rate: 31.25 kbits(00), 1 Mbit(01), 2.5 Mbits(10)
0 -- mode (slone): memory mode(0), stand alone(1)
03 -- station_adr (8-bit bus in hexadecimal format)
20000 ms -- time for which the configuration above is valid
sim/spec/data_vectors/errors_config.txt 0 → 100644
View file @ aae395c5
FALSE -- Truncate preamble
FALSE -- Insert violation error for one clk cycle
0 ps -- Jitter error inserted on the manchester encoded signal
0 -- Number of bits per byte truncated in reception (integer 1 to 8)
0 ps -- TXERR error length
0 ps -- WDGN error length
20000 ms --++ time for which the configuration above is valid
sim/spec/data_vectors/masterFIP_test.vec
View file @ aae395c5
-------------------------------------------------------------------------------
-- masterFIP_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
......@@ -14,6 +14,7 @@ init
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
......@@ -57,7 +58,7 @@ wait %d20
--------------- ID_DAT ---------------
tx_rst
-- tx_rst
wr 0000000000030034 F 00000001
wait %d10
wr 0000000000030034 F 00000000
......@@ -77,7 +78,7 @@ wait %d20000
--------------- RP_DAT ---------------
tx_rst
-- tx_rst
wr 0000000000030034 F 00000001
wait %d10
wr 0000000000030034 F 00000000
......@@ -88,11 +89,11 @@ wr 0000000000030154 F 00000002
wait %d20
-- data bytes
wr 0000000000030158 F BBAA0340
wr 0000000000030158 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wait %d20
wr 000000000003015c F EEDDCC05
wr 000000000003015c F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
wait %d20
wr 0000000000030160 F 0A090807
wr 0000000000030160 F 0A05A2A1
wait %d20
wr 0000000000030164 F 0E0D0C0B
wait %d20
......@@ -100,12 +101,12 @@ wr 0000000000030168 F 06060605
wait %d20
-- tx_start
wr 0000000000030034 F 00000502
wr 0000000000030034 F 00000502 -- for 2 data bytes: 0502 | for 8 data bytes: 0B02
wait %d40000
--------------- ID_DAT ---------------
tx_rst
-- tx_rst
wr 0000000000030034 F 00000001
wait %d10
wr 0000000000030034 F 00000000
......@@ -116,7 +117,7 @@ wr 0000000000030154 F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 0000000000030158 F 00000306
wr 0000000000030158 F 00000314
wait %d20
-- tx_start
......@@ -133,8 +134,45 @@ wait %d40000
-- read received data
rd 0000000000030048 F 00000002
wait %d20
rd 000000000003004c F 00000050
rd 000000000003004c F 03800550
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 0000000000030034 F 00000001
wait %d10
wr 0000000000030034 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030154 F 00000003
wait %d20
-- data bytes varid = 0603 for agent to produce
wr 0000000000030158 F 00000306
wait %d20
-- tx_start
wr 0000000000030034 F 00000202
wait %d20
-- deactivate tx_start
wr 0000000000030034 F 00000000
-- release rx_rst
wr 0000000000030040 F 00000000
wait %d40000
-- read received data
rd 0000000000030048 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
wait %d400
rd 000000000003004c F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
wait %d400
rd 0000000000030050 F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
wait %d400
rd 0000000000030054 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d400
wait %d40000
--------------- RP_FIN ---------------
-- control byte of rp_fin
......
sim/spec/data_vectors/user_logic_config.txt 0 → 100644
View file @ aae395c5
25 ns -- User clock period (should not be modified during test)
25 ns -- Wishbone interface clock period (should not be modified during test)
3 us -- Power-on reset length
1 us -- User reset length
1 us -- Wishbone interface reset length
20000 ms -- validity time: time for which the configuration above is valid
sim/spec/data_vectors/user_sequence.txt 0 → 100644
View file @ aae395c5
## Sequence of Wishbone transfers separated by stand-by times. The transfer parameters must be separated by comas, without spaces.
## The order and values must be as follows: rd_wr: (0) for read / (1) for write, variable: (1) for consumed / (2) for broadcast / (3) for produced,
## data transfer size: integer from 1 to 124, transfer offset: integer from 1 to 124, transfer block size: integer from 1 to 124.
350 us -- stand-by time
0,1,8,0,0 -- reading VAR1 from memory
350 us -- stand-by time
1,3,8,0,0 -- writting VAR3 in memory
20383 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory
431 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory
495 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory
623 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory
879 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory
1359 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory
383 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory
431 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory
495 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory
623 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory
879 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory
2687 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,1,124,0,0 -- reading VAR1 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
1359 us -- stand-by time
0,2,124,0,0 -- reading VAR2 from memory
2000 ms -- final stand-by time to end the simulation
sim/spec/testbench/acam_data_model.vhd deleted 100644 → 0
View file @ 71c1e137
-- Created by : G. Penacoba
-- Creation Date: June 2011
-- Description: reproduced roughly the functionality of the acam:
-- handles the FIFO and the data communication handshake
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity acam_data_model is
port(
start01_i : in std_logic_vector(16 downto 0);
timestamp_for_fifo1 : in std_logic_vector(27 downto 0);
timestamp_for_fifo2 : in std_logic_vector(27 downto 0);
address_i : in std_logic_vector(3 downto 0);
cs_n_i : in std_logic;
oe_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
data_bus_o : out std_logic_vector(27 downto 0);
ef1_o : out std_logic;
ef2_o : out std_logic;
lf1_o : out std_logic;
lf2_o : out std_logic
);
end acam_data_model;
architecture behavioral of acam_data_model is
component acam_fifo_model
generic(
size : integer;
full_threshold : integer;
empty_threshold : integer
);
port(
data_input : in std_logic_vector(27 downto 0);
rd_fifo : in std_logic;
data_output : out std_logic_vector(27 downto 0);
empty : out std_logic;
full : out std_logic
);
end component;
constant ts_ad : time:= 2000 ps; -- minimum address setup time
constant th_ad : time:= 0 ps; -- minimum address hold time
constant tpw_rl : time:= 6000 ps; -- minimum read low time
constant tpw_rh : time:= 6000 ps; -- minimum read high time
constant tpw_wl : time:= 6000 ps; -- minimum write low time
constant tpw_wh : time:= 6000 ps; -- minimum write high time
constant tv_dr : time:= 11800 ps; -- maximum read data valid time
constant th_dr : time:= 4000 ps; -- minimum read data hold time
constant ts_dw : time:= 5000 ps; -- minimum write data setup time
constant th_dw : time:= 4000 ps; -- minimum write data hold time
constant ts_csn : time:= 0 ps; -- minimum chip select setup time
constant th_csn : time:= 0 ps; -- minimum chip select hold time
constant ts_ef : time:= 11800 ps; -- maximum empty flag set time
signal address : std_logic_vector(3 downto 0);
signal cs_n : std_logic;
signal oe_n : std_logic;
signal rd_n : std_logic;
signal wr_n : std_logic;
signal data_bus : std_logic_vector(27 downto 0):= (others =>'Z');
signal ef1 : std_logic;
signal ef2 : std_logic;
signal lf1 : std_logic;
signal lf2 : std_logic;
signal address_change_time : time:= 0 ps;
signal data_change_time : time:= 0 ps;
signal cs_falling_time : time:= 0 ps;
signal cs_rising_time : time:= 0 ps;
signal rd_falling_time : time:= 0 ps;
signal rd_rising_time : time:= 0 ps;
signal wr_falling_time : time:= 0 ps;
signal wr_rising_time : time:= 0 ps;
signal start01 : std_logic_vector(16 downto 0);
signal data_for_bus : std_logic_vector(27 downto 0);
signal data_from_fifo1 : std_logic_vector(27 downto 0);
signal data_from_fifo2 : std_logic_vector(27 downto 0);
signal rd_fifo1 : std_logic;
signal rd_fifo2 : std_logic;
begin
read: process
begin
wait until rd_n ='0';
if cs_n ='0' then
wait for tv_dr;
data_bus <= data_for_bus;
end if;
wait until rd_n ='1';
if cs_n ='0' then
wait for th_dr;
data_bus <= (others =>'Z');
end if;
end process;
data_mux: process(address, data_from_fifo1, data_from_fifo2, start01, rd_n, cs_n)
begin
case address is
when x"8" =>
data_for_bus <= data_from_fifo1;
if rd_n ='0' and cs_n ='0' then
rd_fifo1 <= '1';
rd_fifo2 <= '0';
else
rd_fifo1 <= '0';
rd_fifo2 <= '0';
end if;
when x"9" =>
data_for_bus <= data_from_fifo2;
if rd_n ='0' and cs_n ='0' then
rd_fifo1 <= '0';
rd_fifo2 <= '1';
else
rd_fifo1 <= '0';
rd_fifo2 <= '0';
end if;
when x"A" =>
data_for_bus <= "00000000000" & start01;
rd_fifo1 <= '0';
rd_fifo2 <= '0';
when others =>
data_for_bus <= (others => 'Z');
rd_fifo1 <= '0';
rd_fifo2 <= '0';
end case;
end process;
interface_fifo1: acam_fifo_model
generic map(
size => 256,
full_threshold => 10,
empty_threshold => 1
)
port map(
data_input => timestamp_for_fifo1,
rd_fifo => rd_fifo1,
data_output => data_from_fifo1,
empty => ef1,
full => lf1
);
interface_fifo2: acam_fifo_model
generic map(
size => 256,
full_threshold => 10,
empty_threshold => 1
)
port map(
data_input => timestamp_for_fifo2,
rd_fifo => rd_fifo2,
data_output => data_from_fifo2,
empty => ef2,
full => lf2
);
start01 <= start01_i;
address <= address_i;
cs_n <= cs_n_i;
oe_n <= oe_n_i;
rd_n <= rd_n_i;
wr_n <= wr_n_i;
data_bus_o <= data_bus;
ef1_o <= ef1;
ef2_o <= ef2;
lf1_o <= lf1;
lf2_o <= lf2;
address_timing: process(address)
begin
address_change_time <= now;
end process;
data_timing: process(address)
begin
data_change_time <= now;
end process;
read_timing: process(rd_n)
begin
if falling_edge(rd_n) then
rd_falling_time <= now;
end if;
if rising_edge(rd_n) then
rd_rising_time <= now;
end if;
end process;
write_timing: process(wr_n)
begin
if falling_edge(wr_n) then
wr_falling_time <= now;
end if;
if rising_edge(wr_n) then
wr_rising_time <= now;
end if;
end process;
chip_select_timing: process(cs_n)
begin
if falling_edge(cs_n) then
cs_falling_time <= now;
end if;
if rising_edge(cs_n) then
cs_rising_time <= now;
end if;
end process;
reporting_read_times: process(rd_falling_time, rd_rising_time)
begin
if rd_rising_time - rd_falling_time < tpw_rl
and rd_rising_time - rd_falling_time > 0 ps
and now /= 0 ps then
report LF & " #### Timing error in read signal when reading: minimum low time not respected" & LF
severity warning;
end if;
if rd_falling_time - rd_rising_time < tpw_rh
and rd_falling_time - rd_rising_time > 0 ps
and now /= 0 ps then
report LF & " #### Timing error in read signal when reading: minimum high time not respected" & LF
severity warning;
end if;
end process;
reporting_write_times: process(wr_falling_time, wr_rising_time)
begin
if wr_rising_time - wr_falling_time < tpw_wl
and wr_rising_time - wr_falling_time > 0 ps
and now /= 0 ps then
report LF & " #### Timing error in read signal when writing: minimum low time not respected" & LF
severity warning;
end if;
if wr_falling_time - wr_rising_time < tpw_wh
and wr_falling_time - wr_rising_time > 0 ps
and now /= 0 ps then
report " #### Timing error in read signal when writing: minimum high time not respected" & LF
severity warning;
end if;
end process;
reporting_setup_rd: process(rd_falling_time)
begin
if rd_falling_time - address_change_time < ts_ad and now /= 0 ps then
report LF & " #### Timing error in address bus when reading: minimum setup time not respected" & LF
severity warning;
end if;
if rd_falling_time - cs_falling_time < ts_csn and now /= 0 ps then
report LF & " #### Timing error in chip select signal when reading: minimum setup time not respected" & LF
severity warning;
end if;
end process;
reporting_setup_wr: process(wr_falling_time)
begin
if wr_falling_time - address_change_time < ts_ad and now /= 0 ps then
report LF & " #### Timing error in address bus when writing: minimum setup time not respected" & LF
severity warning;
end if;
if wr_falling_time - cs_falling_time < ts_csn then
report LF & " #### Timing error in chip select signal when writing: minimum setup time not respected" & LF
severity warning;
end if;
end process;
reporting_hold_ad: process(address_change_time)
begin
if address_change_time - rd_rising_time < th_ad and now /= 0 ps then
report LF & " #### Timing error in address bus when reading: minimum hold time not respected" & LF
severity warning;
end if;
if address_change_time - wr_rising_time < th_ad and now /= 0 ps then
report LF & " #### Timing error in address bus when writing: minimum hold time not respected" & LF
severity warning;
end if;
end process;
reporting_hold_cs: process(cs_rising_time)
begin
if cs_rising_time - rd_rising_time < th_csn and now /= 0 ps then
report LF & " #### Timing error in chip select signal when reading: minimum hold time not respected" & LF
severity warning;
end if;
if cs_rising_time - wr_rising_time < th_csn and now /= 0 ps then
report LF & " #### Timing error in chip select signal when writing: minimum hold time not respected" & LF
severity warning;
end if;
end process;
reporting_data_setup_wr: process(wr_rising_time)
begin
if wr_rising_time - data_change_time < ts_dw and now /= 0 ps then
report LF & " #### Timing error in data bus when writing: minimum setup time not respected" & LF
severity warning;
end if;
end process;
reporting_data_hold_wr: process(data_change_time)
begin
if data_change_time - wr_rising_time < th_dw and now /= 0 ps then
report LF & " #### Timing error in data bus when writing: minimum hold time not respected" & LF
severity warning;
end if;
end process;
end behavioral;
sim/spec/testbench/acam_fifo_model.vhd deleted 100644 → 0
View file @ 71c1e137
-- Created by : G. Penacoba
-- Creation Date: June 2011
-- Description: reproduces roughly the functionality of the acam:
-- handles the FIFO and the data communication handshake
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity acam_fifo_model is
generic(
size : integer;
full_threshold : integer;
empty_threshold : integer
);
port(
data_input : in std_logic_vector(27 downto 0);
rd_fifo : in std_logic;
data_output : out std_logic_vector(27 downto 0);
empty : out std_logic;
full : out std_logic
);
end acam_fifo_model;
architecture behavioral of acam_fifo_model is
constant ts_ef : time:= 11800 ps; -- maximum empty flag set time
subtype index is natural range size-1 downto 0;
subtype memory_cell is std_logic_vector(27 downto 0);
type memory_block is array (natural range size-1 downto 0) of memory_cell;
signal fifo : memory_block;
signal wr_pointer : index:= 0;
signal rd_pointer : index:= 0;
signal level : index:= 0;
begin
writing: process(data_input)
begin
if now /= 0 ps then
fifo(wr_pointer) <= data_input;
if wr_pointer = size-1 then
wr_pointer <= 0;
else
wr_pointer <= wr_pointer + 1;
end if;
end if;
end process;
reading: process(rd_fifo)
begin
if rising_edge(rd_fifo) then
data_output <= fifo(rd_pointer);
if rd_pointer = size-1 then
rd_pointer <= 0 after ts_ef;
else
rd_pointer <= rd_pointer + 1 after ts_ef;
end if;
end if;
-- if falling_edge(rd_fifo) then
-- if rd_pointer = size-1 then
-- rd_pointer <= 0;
-- else
-- rd_pointer <= rd_pointer + 1;
-- end if;
-- end if;
end process;
flags: process(level)
begin
if level > full_threshold then
full <= '1';
else
full <= '0';
end if;
if level < empty_threshold then
empty <= '1';
else
empty <= '0';
end if;
end process;
filling_level: process(rd_pointer, wr_pointer)
begin
if wr_pointer >= rd_pointer then
level <= wr_pointer - rd_pointer;
else
level <= wr_pointer + 256 - rd_pointer;
end if;
end process;
-- process(level)
-- begin
-- report " filling level " & integer'image(level) & LF &
-- " rd_pointer " & integer'image(rd_pointer) & LF &
-- " wr_pointer " & integer'image(wr_pointer) & LF;
-- end process;
corruption_reporting_reading: process(rd_pointer)
begin
if now /= 0 ps then
if rd_pointer = wr_pointer then
report LF & " #### Interface FIFO is empty: no further reading should be performed" & LF
severity warning;
end if;
end if;
end process;
corruption_reporting_writing: process(wr_pointer)
begin
if now /= 0 ps then
if rd_pointer = wr_pointer then
report LF & " #### Interface FIFO is full: no further writing should be performed" & LF
severity warning;
end if;
end if;
end process;
end behavioral;
sim/spec/testbench/acam_model.vhd deleted 100644 → 0
View file @ 71c1e137
-- Creation Date: May 2011
-- Description: reproduced roughly the functionality of the acam:
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity acam_model is
generic(
start_retrig_period : time:= 3200 ns;
refclk_period : time:= 32 ns
);
port(
tstart_i : in std_logic;
tstop1_i : in std_logic;
tstop2_i : in std_logic;
tstop3_i : in std_logic;
tstop4_i : in std_logic;
tstop5_i : in std_logic;
startdis_i : in std_logic;
stopdis_i : in std_logic;
int_flag_o : out std_logic;
err_flag_o : out std_logic;
address_i : in std_logic_vector(3 downto 0);
cs_n_i : in std_logic;
oe_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
data_bus_io : inout std_logic_vector(27 downto 0);
ef1_o : out std_logic;
ef2_o : out std_logic;
lf1_o : out std_logic;
lf2_o : out std_logic
);
end acam_model;
architecture behavioral of acam_model is
component acam_timing_model
generic(
refclk_period : time:= 32 ns;
start_retrig_period : time:= 3200 ns
);
port(
tstart_i : in std_logic;
tstop1_i : in std_logic;
tstop2_i : in std_logic;
tstop3_i : in std_logic;
tstop4_i : in std_logic;
tstop5_i : in std_logic;
startdis_i : in std_logic;
stopdis_i : in std_logic;
err_flag_o : out std_logic;
int_flag_o : out std_logic;
start01_o : out std_logic_vector(16 downto 0);
timestamp_for_fifo1 : out std_logic_vector(27 downto 0);
timestamp_for_fifo2 : out std_logic_vector(27 downto 0)
);
end component;
component acam_data_model
port(
start01_i : in std_logic_vector(16 downto 0);
timestamp_for_fifo1 : in std_logic_vector(27 downto 0);
timestamp_for_fifo2 : in std_logic_vector(27 downto 0);
address_i : in std_logic_vector(3 downto 0);
cs_n_i : in std_logic;
oe_n_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
data_bus_o : out std_logic_vector(27 downto 0);
ef1_o : out std_logic;
ef2_o : out std_logic;
lf1_o : out std_logic;
lf2_o : out std_logic
);
end component;
signal timestamp_for_fifo1 : std_logic_vector(27 downto 0);
signal timestamp_for_fifo2 : std_logic_vector(27 downto 0);
signal start01 : std_logic_vector(16 downto 0);
begin
timing_block: acam_timing_model
generic map(
refclk_period => refclk_period,
start_retrig_period => start_retrig_period
)
port map(
tstart_i => tstart_i,
tstop1_i => tstop1_i,
tstop2_i => tstop2_i,
tstop3_i => tstop3_i,
tstop4_i => tstop4_i,
tstop5_i => tstop5_i,
startdis_i => startdis_i,
stopdis_i => stopdis_i,
err_flag_o => err_flag_o,
int_flag_o => int_flag_o,
start01_o => start01,
timestamp_for_fifo1 => timestamp_for_fifo1,
timestamp_for_fifo2 => timestamp_for_fifo2
);
data_block: acam_data_model
port map(
start01_i => start01,
timestamp_for_fifo1 => timestamp_for_fifo1,
timestamp_for_fifo2 => timestamp_for_fifo2,
address_i => address_i,
cs_n_i => cs_n_i,
oe_n_i => oe_n_i,
rd_n_i => rd_n_i,
wr_n_i => wr_n_i,
data_bus_o => data_bus_io,
ef1_o => ef1_o,
ef2_o => ef2_o,
lf1_o => lf1_o,
lf2_o => lf2_o
);
end behavioral;
sim/spec/testbench/acam_timing_model.vhd deleted 100644 → 0
View file @ 71c1e137
-- Created by : G. Penacoba
-- Creation Date: May 2011
-- Description: reproduced roughly the functionality of the acam:
-- measures the time between input pulses.
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity acam_timing_model is
generic(
refclk_period : time:= 32 ns;
start_retrig_period : time:= 3200 ns
);
port(
tstart_i : in std_logic;
tstop1_i : in std_logic;
tstop2_i : in std_logic;
tstop3_i : in std_logic;
tstop4_i : in std_logic;
tstop5_i : in std_logic;
startdis_i : in std_logic;
stopdis_i : in std_logic;
err_flag_o : out std_logic;
int_flag_o : out std_logic;
start01_o : out std_logic_vector(16 downto 0);
timestamp_for_fifo1 : out std_logic_vector(27 downto 0);
timestamp_for_fifo2 : out std_logic_vector(27 downto 0)
);
end acam_timing_model;
architecture behavioral of acam_timing_model is
constant resolution : time:= 81 ps;
signal tstart : std_logic;
signal tstop1 : std_logic;
signal tstop2 : std_logic;
signal tstop3 : std_logic;
signal tstop4 : std_logic;
signal tstop5 : std_logic;
signal startdis : std_logic;
signal stopdis : std_logic;
signal intflag : std_logic;
signal start01_reg : std_logic_vector(16 downto 0);
signal start01 : time:= 0 ps;
signal start_trig : time:= 0 ps;
signal stop1_trig : time:= 0 ps;
signal stop2_trig : time:= 0 ps;
signal stop3_trig : time:= 0 ps;
signal stop4_trig : time:= 0 ps;
signal stop5_trig : time:= 0 ps;
signal stop1 : time:= 0 ps;
signal stop2 : time:= 0 ps;
signal stop3 : time:= 0 ps;
signal stop4 : time:= 0 ps;
signal stop5 : time:= 0 ps;
signal start_nb1 : integer:=0;
signal start_nb2 : integer:=0;
signal start_nb3 : integer:=0;
signal start_nb4 : integer:=0;
signal start_nb5 : integer:=0;
signal start_retrig_nb : integer:=0;
signal start_retrig_p : std_logic;
begin
listening: process (tstart, tstop1, tstop2, tstop3, tstop4, tstop5)
begin
if rising_edge(tstart) then
if startdis ='0' then
start_trig <= now;
end if;
end if;
if rising_edge(tstop1) then
if stopdis ='0' then
stop1_trig <= now;
end if;
end if;
if rising_edge(tstop2) then
if stopdis ='0' then
stop2_trig <= now;
end if;
end if;
if rising_edge(tstop3) then
if stopdis ='0' then
stop3_trig <= now;
end if;
end if;
if rising_edge(tstop4) then
if stopdis ='0' then
stop4_trig <= now;
end if;
end if;
if rising_edge(tstop5) then
if stopdis ='0' then
stop5_trig <= now;
end if;
end if;
end process;
measuring1: process(stop1_trig)
begin
if start_retrig_nb > 1 then
stop1 <= (stop1_trig-start_trig-start01)-((start_retrig_nb-1)*start_retrig_period);
elsif start_retrig_nb = 1 then
stop1 <= (stop1_trig-start_trig-start01);
else
stop1 <= (stop1_trig-start_trig);
end if;
start_nb1 <= start_retrig_nb mod 256;
end process;
measuring2: process(stop2_trig)
begin
if start_retrig_nb > 1 then
stop2 <= (stop2_trig-start_trig-start01)-((start_retrig_nb-1)*start_retrig_period);
elsif start_retrig_nb = 1 then
stop2 <= (stop2_trig-start_trig-start01);
else
stop2 <= (stop2_trig-start_trig);
end if;
start_nb2 <= start_retrig_nb mod 256;
end process;
measuring3: process(stop3_trig)
begin
if start_retrig_nb > 1 then
stop3 <= (stop3_trig-start_trig-start01)-((start_retrig_nb-1)*start_retrig_period);
elsif start_retrig_nb = 1 then
stop3 <= (stop3_trig-start_trig-start01);
else
stop3 <= (stop3_trig-start_trig);
end if;
start_nb3 <= start_retrig_nb mod 256;
end process;
measuring4: process(stop4_trig)
begin
if start_retrig_nb > 1 then
stop4 <= (stop4_trig-start_trig-start01)-((start_retrig_nb-1)*start_retrig_period);
elsif start_retrig_nb = 1 then
stop4 <= (stop4_trig-start_trig-start01);
else
stop4 <= (stop4_trig-start_trig);
end if;
start_nb4 <= start_retrig_nb mod 256;
end process;
measuring5: process(stop5_trig)
begin
if start_retrig_nb > 1 then
stop5 <= (stop5_trig-start_trig-start01)-((start_retrig_nb-1)*start_retrig_period);
elsif start_retrig_nb = 1 then
stop5 <= (stop5_trig-start_trig-start01);
else
stop5 <= (stop5_trig-start_trig);
end if;
start_nb5 <= start_retrig_nb mod 256;
end process;
measuring_start01: process(start_retrig_p)
begin
if rising_edge(start_retrig_p) then
if start_retrig_nb = 0 then
start01 <= now - start_trig;
end if;
end if;
end process;
writing_fifo1: process (tstop1, tstop2, tstop3, tstop4)
begin
if falling_edge(tstop1) then
timestamp_for_fifo1(27 downto 26) <= "00";
timestamp_for_fifo1(25 downto 18) <= std_logic_vector(to_unsigned(start_nb1,8));
timestamp_for_fifo1(17) <= '1';
timestamp_for_fifo1(16 downto 0) <= std_logic_vector(to_unsigned(stop1/resolution,17));
start01_reg <= std_logic_vector(to_unsigned(start01/resolution,17));
report " Timestamp for interface FIFO 1:" & LF &
"===============================" & LF &
"Channel 1" & LF &
"Start number: " & integer'image(start_nb1) & LF &
"Time Interval: " & integer'image(stop1/resolution) & LF &
"Start01: " & integer'image(start01/resolution) & LF;
end if;
if falling_edge(tstop2) then
timestamp_for_fifo1(27 downto 26) <= "01";
timestamp_for_fifo1(25 downto 18) <= std_logic_vector(to_unsigned(start_nb2,8));
timestamp_for_fifo1(17) <= '1';
timestamp_for_fifo1(16 downto 0) <= std_logic_vector(to_unsigned(stop2/resolution,17));
start01_reg <= std_logic_vector(to_unsigned(start01/resolution,17));
report " Timestamp for interface FIFO 1:" & LF &
"===============================" & LF &
"Channel 2" & LF &
"Start number: " & integer'image(start_nb2) & LF &
"Time Interval: " & integer'image(stop2/resolution) & LF &
"Start01: " & integer'image(start01/resolution) & LF;
end if;
if falling_edge(tstop3) then
timestamp_for_fifo1(27 downto 26) <= "10";
timestamp_for_fifo1(25 downto 18) <= std_logic_vector(to_unsigned(start_nb3,8));
timestamp_for_fifo1(17) <= '1';
timestamp_for_fifo1(16 downto 0) <= std_logic_vector(to_unsigned(stop3/resolution,17));
start01_reg <= std_logic_vector(to_unsigned(start01/resolution,17));
report " Timestamp for interface FIFO 1:" & LF &
"===============================" & LF &
"Channel 3" & LF &
"Start number: " & integer'image(start_nb3) & LF &
"Time Interval: " & integer'image(stop3/resolution) & LF &
"Start01: " & integer'image(start01/resolution) & LF;
end if;
if falling_edge(tstop4) then
timestamp_for_fifo1(27 downto 26) <= "11";
timestamp_for_fifo1(25 downto 18) <= std_logic_vector(to_unsigned(start_nb4,8));
timestamp_for_fifo1(17) <= '1';
timestamp_for_fifo1(16 downto 0) <= std_logic_vector(to_unsigned(stop4/resolution,17));
start01_reg <= std_logic_vector(to_unsigned(start01/resolution,17));
report " Timestamp for interface FIFO 1:" & LF &
"===============================" & LF &
"Channel 4" & LF &
"Start number: " & integer'image(start_nb4) & LF &
"Time Interval: " & integer'image(stop4/resolution) & LF &
"Start01: " & integer'image(start01/resolution) & LF;
end if;
end process;
writing_fifo2: process (tstop5)
begin
if falling_edge(tstop5) then
timestamp_for_fifo2(27 downto 26) <= "00";
timestamp_for_fifo2(25 downto 18) <= std_logic_vector(to_unsigned(start_nb5,8));
timestamp_for_fifo2(17) <= '1';
timestamp_for_fifo2(16 downto 0) <= std_logic_vector(to_unsigned(stop5/resolution,17));
start01_reg <= std_logic_vector(to_unsigned(start01/resolution,17));
report " Timestamp for interface FIFO 2:" & LF &
"===============================" & LF &
"Channel 5" & LF &
"Start number: " & integer'image(start_nb5) & LF &
"Time Interval: " & integer'image(stop5/resolution) & LF &
"Start01: " & integer'image(start01/resolution) & LF;
end if;
end process;
start_retrigger_pulses: process
begin
start_retrig_p <= '0' after 333 ps;
wait for start_retrig_period/4;
start_retrig_p <= '1' after 333 ps;
wait for start_retrig_period/4;
start_retrig_p <= '0' after 333 ps;
wait for start_retrig_period/2;
end process;
start_nb_counter: process(tstart, start_retrig_p)
begin
if rising_edge(tstart) then
start_retrig_nb <= 0;
elsif rising_edge(start_retrig_p) then
start_retrig_nb <= start_retrig_nb + 1;
end if;
end process;
interrupt_flag: process(start_retrig_nb)
begin
if (start_retrig_nb mod 256) > 127 then
intflag <= '1';
else
intflag <= '0';
end if;
end process;
tstart <= tstart_i;
tstop1 <= tstop1_i;
tstop2 <= tstop2_i;
tstop3 <= tstop3_i;
tstop4 <= tstop4_i;
tstop5 <= tstop5_i;
startdis <= startdis_i;
stopdis <= stopdis_i;
int_flag_o <= intflag;
start01_o <= start01_reg;
end behavioral;
sim/spec/testbench/board_settings.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: MAy 2010
-- Description: Module emulating the settings on the board switches
-- Modified by: Penacoba
-- Modification Date: September 2010
-- Modification consisted on: All the config data come from a text file.
-- No compilation is needed to run a new test
-- with different board configuration, and several
-- successive configurations can be run on the same test.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity board_settings is
port(
s_id_i : in std_logic_vector(1 downto 0);
c_id_o : out std_logic_vector(3 downto 0);
m_id_o : out std_logic_vector(3 downto 0);
nostat_o : out std_logic;
p3_lgth_o : out std_logic_vector(2 downto 0);
rate_o : out std_logic_vector(1 downto 0);
slone_o : out std_logic;
subs_o : out std_logic_vector(7 downto 0)
);
end board_settings;
architecture archi of board_settings is
signal c_id_3 : string(1 to 3);
signal c_id_2 : string(1 to 3);
signal c_id_1 : string(1 to 3);
signal c_id_0 : string(1 to 3);
signal m_id_3 : string(1 to 3);
signal m_id_2 : string(1 to 3);
signal m_id_1 : string(1 to 3);
signal m_id_0 : string(1 to 3);
signal nostat : std_logic;
signal plength : std_logic_vector(2 downto 0);
signal rate : std_logic_vector(1 downto 0);
signal slone : std_logic;
signal station_adr : unsigned(7 downto 0);
signal constructor : unsigned(7 downto 0);
signal model : unsigned(7 downto 0);
signal length_strg : string(1 to 19);
signal mode_strg : string(1 to 19);
signal rate_strg : string(1 to 19);
signal nstat_strg : string(1 to 19);
signal read_config_trigger : std_logic:='0';
signal report_config_trigger : std_logic:='0';
begin
-- process reading config values from a file
---------------------------------------------
read_config: process
file config_file : text open read_mode is "../../sim/spec/data_vectors/board_settings_config.txt";
variable config_line : line;
variable validity_time : time;
variable c_id_3_config : string(1 to 3);
variable c_id_2_config : string(1 to 3);
variable c_id_1_config : string(1 to 3);
variable c_id_0_config : string(1 to 3);
variable m_id_3_config : string(1 to 3);
variable m_id_2_config : string(1 to 3);
variable m_id_1_config : string(1 to 3);
variable m_id_0_config : string(1 to 3);
variable nostat_config : std_logic;
variable plength_config : std_logic_vector(2 downto 0);
variable rate_config : std_logic_vector(1 downto 0);
variable slone_config : std_logic;
variable station_adr_config : std_logic_vector(7 downto 0);
begin
readline (config_file, config_line);
read (config_line, c_id_3_config);
readline (config_file, config_line);
read (config_line, c_id_2_config);
readline (config_file, config_line);
read (config_line, c_id_1_config);
readline (config_file, config_line);
read (config_line, c_id_0_config);
readline (config_file, config_line);
read (config_line, m_id_3_config);
readline (config_file, config_line);
read (config_line, m_id_2_config);
readline (config_file, config_line);
read (config_line, m_id_1_config);
readline (config_file, config_line);
read (config_line, m_id_0_config);
readline (config_file, config_line);
read (config_line, nostat_config);
readline (config_file, config_line);
read (config_line, plength_config);
readline (config_file, config_line);
read (config_line, rate_config);
readline (config_file, config_line);
read (config_line, slone_config);
readline (config_file, config_line);
hread (config_line, station_adr_config);
report " ++ config";
readline (config_file, config_line);
read (config_line, validity_time);
if endfile(config_file) then
file_close(config_file);
end if;
c_id_3 <= c_id_3_config;
c_id_2 <= c_id_2_config;
c_id_1 <= c_id_1_config;
c_id_0 <= c_id_0_config;
m_id_3 <= m_id_3_config;
m_id_2 <= m_id_2_config;
m_id_1 <= m_id_1_config;
m_id_0 <= m_id_0_config;
nostat <= nostat_config;
plength <= plength_config;
rate <= rate_config;
slone <= slone_config;
station_adr <= unsigned(station_adr_config);
read_config_trigger <= '1';
wait for validity_time - 1 ps;
read_config_trigger <= '0';
wait for 1 ps;
end process;
-- process transcribing the current board configuration into a temp file
-- for other blocks
-----------------------------------------------------------------------
board_temp_config: process(report_config_trigger)
file config_file : text;
variable config_line : line;
begin
if report_config_trigger = '1' then
file_open(config_file,"../../sim/spec/data_vectors/tmp_board_config.txt",write_mode);
write (config_line,slone);
writeline (config_file,config_line);
write (config_line,length_strg);
writeline (config_file,config_line);
write (config_line,nostat);
writeline (config_file,config_line);
hwrite (config_line,std_logic_vector(constructor));
writeline (config_file,config_line);
hwrite (config_line,std_logic_vector(model));
writeline (config_file,config_line);
hwrite (config_line,std_logic_vector(station_adr));
writeline (config_file,config_line);
file_close(config_file);
end if;
end process;
-- Signals actually sent to nanoFIP
-----------------------------------
with c_id_3 select
c_id_o(3) <= '0' when "gnd",
'1' when "vcc",
s_id_i(1) when "sd1",
s_id_i(0) when "sd0",
'0' when others;
with c_id_2 select
c_id_o(2) <= '0' when "gnd",
'1' when "vcc",
s_id_i(1) when "sd1",
s_id_i(0) when "sd0",
'0' when others;
with c_id_1 select
c_id_o(1) <= '0' when "gnd",
'1' when "vcc",
s_id_i(1) when "sd1",
s_id_i(0) when "sd0",
'0' when others;
with c_id_0 select
c_id_o(0) <= '0' when "gnd",
'1' when "vcc",
s_id_i(1) when "sd1",
s_id_i(0) when "sd0",
'0' when others;
with m_id_3 select
m_id_o(3) <= '0' when "gnd",
'1' when "vcc",
s_id_i(1) when "sd1",
s_id_i(0) when "sd0",
'0' when others;
with m_id_2 select
m_id_o(2) <= '0' when "gnd",
'1' when "vcc",
s_id_i(1) when "sd1",
s_id_i(0) when "sd0",
'0' when others;
with m_id_1 select
m_id_o(1) <= '0' when "gnd",
'1' when "vcc",
s_id_i(1) when "sd1",
s_id_i(0) when "sd0",
'0' when others;
with m_id_0 select
m_id_o(0) <= '0' when "gnd",
'1' when "vcc",
s_id_i(1) when "sd1",
s_id_i(0) when "sd0",
'0' when others;
nostat_o <= nostat;
p3_lgth_o <= plength;
rate_o <= rate;
slone_o <= slone;
subs_o <= std_logic_vector(station_adr);
-- Translation of values for the reporting
------------------------------------------
with c_id_3 select
constructor(7 downto 6) <= "00" when "gnd",
"11" when "vcc",
"10" when "sd1",
"01" when "sd0",
"00" when others;
with c_id_2 select
constructor(5 downto 4) <= "00" when "gnd",
"11" when "vcc",
"10" when "sd1",
"01" when "sd0",
"00" when others;
with c_id_1 select
constructor(3 downto 2) <= "00" when "gnd",
"11" when "vcc",
"10" when "sd1",
"01" when "sd0",
"00" when others;
with c_id_0 select
constructor(1 downto 0) <= "00" when "gnd",
"11" when "vcc",
"10" when "sd1",
"01" when "sd0",
"00" when others;
with m_id_3 select
model(7 downto 6) <= "00" when "gnd",
"11" when "vcc",
"10" when "sd1",
"01" when "sd0",
"00" when others;
with m_id_2 select
model(5 downto 4) <= "00" when "gnd",
"11" when "vcc",
"10" when "sd1",
"01" when "sd0",
"00" when others;
with m_id_1 select
model(3 downto 2) <= "00" when "gnd",
"11" when "vcc",
"10" when "sd1",
"01" when "sd0",
"00" when others;
with m_id_0 select
model(1 downto 0) <= "00" when "gnd",
"11" when "vcc",
"10" when "sd1",
"01" when "sd0",
"00" when others;
with nostat select
nstat_strg <= "Disabled " when '1',
"Enabled " when '0',
"Incorrectly defined" when others;
with plength select
length_strg <= "2 bytes " when "000",
"8 bytes " when "001",
"16 bytes " when "010",
"32 bytes " when "011",
"64 bytes " when "100",
"124 bytes " when "101",
"Incorrectly defined" when others;
with rate select
rate_strg <= "31.25 kbit/s " when "00",
"1 Mbit/s " when "01",
"2.5 Mbit/s " when "10",
"Incorrectly defined" when others;
with slone select
mode_strg <= "Memory mode " when '0',
"Stand-alone mode " when '1',
"Incorrectly defined" when others;
-- reporting processes
-----------------------
report_config_trigger <= read_config_trigger;-- after 1 ps;
reporting: process(report_config_trigger)
begin
if report_config_trigger'event and report_config_trigger ='1' then
report LF &
"Board configuration settings for nanoFIP under test" & LF &
"---------------------------------------------------" & LF &
"WorldFIP rate : " & rate_strg & LF &
"Agent address : " & integer'image(to_integer(station_adr)) & LF &
"Operation mode : " & mode_strg & Lf &
"Produced variable length : " & length_strg & LF &
"NanoFIP status byte tranmission: " & nstat_strg & LF &
"Constructor ID (dec) : " & integer'image(to_integer(constructor)) & LF &
"Model ID (dec) : " & integer'image(to_integer(model)) & LF;
end if;
end process;
end archi;
sim/spec/testbench/encounter.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: March 2010
-- Description: Counter with enable signal. Count value and 'done' signal
-- available. 'done' signal asserted at count value = 0.
-- Modified by: G. Penacoba
-- Modification Date: 30/04/2010
-- Modification consisted on: using unsigned types and numeric_std package
-- instead of std_logic_vectors and std_logic_unsigned
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity encounter is
generic(
width : integer:=16
);
port(
clk : in std_logic;
en : in std_logic;
reset : in std_logic;
start_value : in std_logic_vector(width-1 downto 0);
count : out std_logic_vector(width-1 downto 0);
count_done : out std_logic
);
end encounter;
architecture archi of encounter is
constant zeroes : unsigned(width-1 downto 0):=(others=>'0');
signal one : unsigned(width-1 downto 0);
signal value : unsigned(width-1 downto 0);
begin
decount: process (reset, clk, start_value)
begin
if reset = '1' then
value <= unsigned(start_value);
elsif clk'event and clk= '1' then
if en = '1' and value > zeroes then
value <= value - "1";
end if;
end if;
end process;
count <= std_logic_vector(value);
one <= zeroes + "1";
redundant: process (reset, clk)
begin
if reset = '1' then
count_done <= '0';
elsif clk'event and clk ='1' then
if en ='1' and value = one then
count_done <= '1';
elsif value = zeroes then
count_done <= '1';
else
count_done <= '0';
end if;
end if;
end process;
end archi;
sim/spec/testbench/nanoFIP/dualram_512x8.vhd
View file @ aae395c5
......@@ -52,9 +52,12 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use work.gencores_pkg.all;
use work.genram_pkg.all;
-- Component specific library
library PROASIC3; -- ProASIC3 library
use PROASIC3.all;
--library PROASIC3; -- ProASIC3 library
--use PROASIC3.all;
--=================================================================================================
......@@ -121,56 +124,95 @@ architecture RAM4K9 of dualram_512x8 is
-- A Low on this signal makes the output retain data from the previous Read. A High indicates a
-- pass-through behavior where the data being written will appear on the output immediately.
component RAM4K9
generic (MEMORYFILE : string := "");
port(
ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6,
ADDRA5, ADDRA4, ADDRA3, ADDRA2, ADDRA1, ADDRA0,
ADDRB11, ADDRB10, ADDRB9, ADDRB8, ADDRB7, ADDRB6,
ADDRB5, ADDRB4, ADDRB3, ADDRB2, ADDRB1, ADDRB0,
DINA8, DINA7, DINA6, DINA5, DINA4, DINA3, DINA2, DINA1, DINA0,
DINB8, DINB7, DINB6, DINB5, DINB4, DINB3, DINB2, DINB1, DINB0,
WIDTHA0, WIDTHA1,
WIDTHB0, WIDTHB1,
PIPEA, PIPEB,
WMODEA, WMODEB,
BLKA, BLKB,
WENA, WENB,
CLKA, CLKB,
RESET : in std_logic := 'U';
----------------------------------------------------
DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2, DOUTA1, DOUTA0,
DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic);
----------------------------------------------------
end component;
-- component RAM4K9
-- generic (MEMORYFILE : string := "");
-- port(
-- ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6,
-- ADDRA5, ADDRA4, ADDRA3, ADDRA2, ADDRA1, ADDRA0,
-- ADDRB11, ADDRB10, ADDRB9, ADDRB8, ADDRB7, ADDRB6,
-- ADDRB5, ADDRB4, ADDRB3, ADDRB2, ADDRB1, ADDRB0,
-- DINA8, DINA7, DINA6, DINA5, DINA4, DINA3, DINA2, DINA1, DINA0,
-- DINB8, DINB7, DINB6, DINB5, DINB4, DINB3, DINB2, DINB1, DINB0,
-- WIDTHA0, WIDTHA1,
-- WIDTHB0, WIDTHB1,
-- PIPEA, PIPEB,
-- WMODEA, WMODEB,
-- BLKA, BLKB,
-- WENA, WENB,
-- CLKA, CLKB,
-- RESET : in std_logic := 'U';
-- ----------------------------------------------------
-- DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2, DOUTA1, DOUTA0,
-- DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic);
-- ----------------------------------------------------
-- end component;
component generic_dpram_dualclock
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end component;
---------------------------------------------------------------------------------------------------
-- Instantiation of the component VCC
component VCCtmp
port (Y : out std_logic);
end component;
--component VCCtmp
-- port (Y : out std_logic);
--end component;
---------------------------------------------------------------------------------------------------
-- Instantiation of the component GND
component GNDtmp
port (Y : out std_logic);
end component;
--component GNDtmp
-- port (Y : out std_logic);
--end component;
---------------------------------------------------------------------------------------------------
signal POWER, GROUND : std_logic;
--signal POWER, GROUND : std_logic;
signal wea, web : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
power_supply_signal : VCCtmp port map(Y => POWER);
ground_signal : GNDtmp port map(Y => GROUND);
wea <= not RWA;
web <= not RWB;
--power_supply_signal : VCCtmp port map(Y => POWER);
--ground_signal : GNDtmp port map(Y => GROUND);
---------------------------------------------------------------------------------------------------
-- Instantiation of the component RAM4K9.
......@@ -182,105 +224,127 @@ begin
-- o PIPEA, PIPEB : GNDtmp (not pipelined read)
-- o WMODEA, WMODEB: GNDtmp (in write mode the output retains the data from the previous read)
A9D8DualClkRAM_R0C0 : RAM4K9
port map(
-- INPUTS
-- inputs concerning port A
-- data in A (1 byte, (7 downto 0))
DINA8 => GROUND,
DINA7 => DINA(7),
DINA6 => DINA(6),
DINA5 => DINA(5),
DINA4 => DINA(4),
DINA3 => DINA(3),
DINA2 => DINA(2),
DINA1 => DINA(1),
DINA0 => DINA(0),
-- address A (512 bytes depth, (8 downto 0))
ADDRA11 => GROUND,
ADDRA10 => GROUND,
ADDRA9 => GROUND,
ADDRA8 => ADDRA(8),
ADDRA7 => ADDRA(7),
ADDRA6 => ADDRA(6),
ADDRA5 => ADDRA(5),
ADDRA4 => ADDRA(4),
ADDRA3 => ADDRA(3),
ADDRA2 => ADDRA(2),
ADDRA1 => ADDRA(1),
ADDRA0 => ADDRA(0),
-- read/ write mode for A
WENA => RWA,
-- clock for A
CLKA => CLKA,
-- aspect ratio, block, pipeline, write mode configurations for port A
WIDTHA0 => POWER,
WIDTHA1 => POWER,
BLKA => GROUND,
PIPEA => GROUND,
WMODEA => GROUND,
-- inputs concerning port B
-- data in B (1 byte, (7 downto 0))
DINB8 => GROUND,
DINB7 => DINB(7),
DINB6 => DINB(6),
DINB5 => DINB(5),
DINB4 => DINB(4),
DINB3 => DINB(3),
DINB2 => DINB(2),
DINB1 => DINB(1),
DINB0 => DINB(0),
-- address B (512 bytes depth, (8 downto 0))
ADDRB11 => GROUND,
ADDRB10 => GROUND,
ADDRB9 => GROUND,
ADDRB8 => ADDRB(8),
ADDRB7 => ADDRB(7),
ADDRB6 => ADDRB(6),
ADDRB5 => ADDRB(5),
ADDRB4 => ADDRB(4),
ADDRB3 => ADDRB(3),
ADDRB2 => ADDRB(2),
ADDRB1 => ADDRB(1),
ADDRB0 => ADDRB(0),
-- read/ write mode for B
WENB => RWB,
-- clock for B
CLKB => CLKB,
-- aspect ratio, block, pipeline, write mode configurations for port B
WIDTHB0 => POWER,
WIDTHB1 => POWER,
BLKB => GROUND,
PIPEB => GROUND,
WMODEB => GROUND,
-- input reset
RESET => RESETn,
-------------------------------
-- OUTPUTS
-- output concerning port A
-- data out A (1 byte)
DOUTA8 => open,
DOUTA7 => DOUTA(7),
DOUTA6 => DOUTA(6),
DOUTA5 => DOUTA(5),
DOUTA4 => DOUTA(4),
DOUTA3 => DOUTA(3),
DOUTA2 => DOUTA(2),
DOUTA1 => DOUTA(1),
DOUTA0 => DOUTA(0),
-- output concerning port B
-- data out B (1 byte)
DOUTB8 => open,
DOUTB7 => DOUTB(7),
DOUTB6 => DOUTB(6),
DOUTB5 => DOUTB(5),
DOUTB4 => DOUTB(4),
DOUTB3 => DOUTB(3),
DOUTB2 => DOUTB(2),
DOUTB1 => DOUTB(1),
DOUTB0 => DOUTB(0));
DualClkRam : generic_dpram_dualclock
generic map (
g_data_width => 8,
g_size => 512)
port map (
rst_n_i =>'1',
-- Port A
clka_i => CLKA,
bwea_i => "1",
wea_i => wea,
aa_i => ADDRA,
da_i => DINA,
qa_o => DOUTA,
-- Port B
clkb_i => CLKB,
bweb_i => "1",
web_i => web,
ab_i => ADDRB,
db_i => DINB,
qb_o => DOUTB);
-- A9D8DualClkRAM_R0C0 : RAM4K9
-- port map(
-- -- INPUTS
-- -- inputs concerning port A
-- -- data in A (1 byte, (7 downto 0))
-- DINA8 => GROUND,
-- DINA7 => DINA(7),
-- DINA6 => DINA(6),
-- DINA5 => DINA(5),
-- DINA4 => DINA(4),
-- DINA3 => DINA(3),
-- DINA2 => DINA(2),
-- DINA1 => DINA(1),
-- DINA0 => DINA(0),
-- -- address A (512 bytes depth, (8 downto 0))
-- ADDRA11 => GROUND,
-- ADDRA10 => GROUND,
-- ADDRA9 => GROUND,
-- ADDRA8 => ADDRA(8),
-- ADDRA7 => ADDRA(7),
-- ADDRA6 => ADDRA(6),
-- ADDRA5 => ADDRA(5),
-- ADDRA4 => ADDRA(4),
-- ADDRA3 => ADDRA(3),
-- ADDRA2 => ADDRA(2),
-- ADDRA1 => ADDRA(1),
-- ADDRA0 => ADDRA(0),
-- -- read/ write mode for A
-- WENA => RWA,
-- -- clock for A
-- CLKA => CLKA,
-- -- aspect ratio, block, pipeline, write mode configurations for port A
-- WIDTHA0 => POWER,
-- WIDTHA1 => POWER,
-- BLKA => GROUND,
-- PIPEA => GROUND,
-- WMODEA => GROUND,
-- -- inputs concerning port B
-- -- data in B (1 byte, (7 downto 0))
-- DINB8 => GROUND,
-- DINB7 => DINB(7),
-- DINB6 => DINB(6),
-- DINB5 => DINB(5),
-- DINB4 => DINB(4),
-- DINB3 => DINB(3),
-- DINB2 => DINB(2),
-- DINB1 => DINB(1),
-- DINB0 => DINB(0),
-- -- address B (512 bytes depth, (8 downto 0))
-- ADDRB11 => GROUND,
-- ADDRB10 => GROUND,
-- ADDRB9 => GROUND,
-- ADDRB8 => ADDRB(8),
-- ADDRB7 => ADDRB(7),
-- ADDRB6 => ADDRB(6),
-- ADDRB5 => ADDRB(5),
-- ADDRB4 => ADDRB(4),
-- ADDRB3 => ADDRB(3),
-- ADDRB2 => ADDRB(2),
-- ADDRB1 => ADDRB(1),
-- ADDRB0 => ADDRB(0),
-- -- read/ write mode for B
-- WENB => RWB,
-- -- clock for B
-- CLKB => CLKB,
-- -- aspect ratio, block, pipeline, write mode configurations for port B
-- WIDTHB0 => POWER,
-- WIDTHB1 => POWER,
-- BLKB => GROUND,
-- PIPEB => GROUND,
-- WMODEB => GROUND,
-- -- input reset
-- RESET => RESETn,
-- -------------------------------
-- -- OUTPUTS
-- -- output concerning port A
-- -- data out A (1 byte)
-- DOUTA8 => open,
-- DOUTA7 => DOUTA(7),
-- DOUTA6 => DOUTA(6),
-- DOUTA5 => DOUTA(5),
-- DOUTA4 => DOUTA(4),
-- DOUTA3 => DOUTA(3),
-- DOUTA2 => DOUTA(2),
-- DOUTA1 => DOUTA(1),
-- DOUTA0 => DOUTA(0),
-- -- output concerning port B
-- -- data out B (1 byte)
-- DOUTB8 => open,
-- DOUTB7 => DOUTB(7),
-- DOUTB6 => DOUTB(6),
-- DOUTB5 => DOUTB(5),
-- DOUTB4 => DOUTB(4),
-- DOUTB3 => DOUTB(3),
-- DOUTB2 => DOUTB(2),
-- DOUTB1 => DOUTB(1),
-- DOUTB0 => DOUTB(0));
-------------------------------
end RAM4K9;
......
sim/spec/testbench/nanoFIP/wf_dualram_512x8_clka_rd_clkb_wr.vhd
View file @ aae395c5
......@@ -129,7 +129,7 @@ begin
-- end generate;
---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- for triplication: Combinatorial Majority_Voter
-- for triplication: Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
......
sim/spec/testbench/slone_interface.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: November 2010
-- Description: Generates the produced variable data
-- and the variable access signals to indicate activity in stand-alone
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity slone_interface is
port(
launch_slone_read : in std_logic;
launch_slone_write : in std_logic;
uclk : in std_logic;
ureset : in std_logic;
dat_o : out std_logic_vector(15 downto 0);
slone_access_read : out std_logic;
slone_access_write : out std_logic
);
end slone_interface;
architecture archi of slone_interface is
signal action : std_logic;
signal data_for_slone_hi : std_logic_vector(7 downto 0);
signal data_for_slone_lo : std_logic_vector(7 downto 0);
signal slone_rd : std_logic;
signal slone_wr : std_logic;
begin
-- process to dectect a rising edge on the inputs
-------------------------------------------------
input_registers: process
begin
slone_rd <= launch_slone_read;
slone_wr <= launch_slone_write;
if ureset ='1' then
action <= '0';
elsif (slone_rd ='0' and launch_slone_read ='1')
or (slone_wr ='0' and launch_slone_write ='1') then
action <= '1';
else
action <= '0';
end if;
wait until uclk ='1';
end process;
-- processes to fix the output data
-----------------------------------
output_register: process
begin
if ureset ='1' then
dat_o <= (others=>'0');
elsif action ='1' and slone_wr ='1' then
dat_o(15 downto 8) <= data_for_slone_hi;
dat_o(7 downto 0) <= data_for_slone_lo;
end if;
wait until uclk ='1';
end process;
access_register: process
begin
if ureset ='1' then
slone_access_read <= '0';
elsif launch_slone_read ='1' or (action ='1' and slone_rd ='1') then
slone_access_read <= '1';
else
slone_access_read <= '0';
end if;
if ureset ='1' then
slone_access_write <= '0';
elsif launch_slone_write ='1' or (action ='1' and slone_wr ='1') then
slone_access_write <= '1';
else
slone_access_write <= '0';
end if;
wait until uclk ='1';
end process;
-- process reading bytes from random data file
---------------------------------------------
read_store: process
file data_file: text open read_mode is "../../sim/spec/data_vectors/data_store.txt";
variable data_line: line;
variable data_byte_hi: std_logic_vector(7 downto 0);
variable data_byte_lo: std_logic_vector(7 downto 0);
begin
readline (data_file, data_line);
hread (data_line, data_byte_hi);
readline (data_file, data_line);
hread (data_line, data_byte_lo);
data_for_slone_hi <= data_byte_hi;
data_for_slone_lo <= data_byte_lo;
wait until uclk ='1';
end process;
end archi;
sim/spec/testbench/slone_monitor.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: November 2010
-- Description: Generates the produced variable data
-- and the variable access signals to indicate activity in stand-alone
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity slone_monitor is
port(
dat_i : in std_logic_vector(15 downto 0);
dat_o : in std_logic_vector(15 downto 0);
slone_access_read : in std_logic;
slone_access_write : in std_logic;
uclk : in std_logic;
ureset : in std_logic;
var_id : in std_logic_vector(1 downto 0)
);
end slone_monitor;
architecture archi of slone_monitor is
signal in_consumed : std_logic_vector(15 downto 0);
signal in_broadcast : std_logic_vector(15 downto 0);
signal out_produced : vector_type;
begin
-- process reading from a text file the data sent by FIP for consumption
------------------------------------------------------------------------
read_incoming: process(slone_access_read, var_id)
file data_file : text;
variable data_line : line;
variable data_byte_hi : std_logic_vector(7 downto 0);
variable data_byte_lo : std_logic_vector(7 downto 0);
begin
if slone_access_read ='1' then
if var_id = "01" then
file_open(data_file,"../../sim/spec/data_vectors/tmp_var1_mem.txt",read_mode);
readline (data_file, data_line);
readline (data_file, data_line);
readline (data_file, data_line);
hread (data_line, data_byte_lo);
readline (data_file, data_line);
hread (data_line, data_byte_hi);
file_close(data_file);
in_consumed <= data_byte_hi & data_byte_lo;
elsif var_id = "10" then
file_open(data_file,"../../sim/spec/data_vectors/tmp_var2_mem.txt",read_mode);
readline (data_file, data_line);
readline (data_file, data_line);
readline (data_file, data_line);
read (data_line, data_byte_lo);
readline (data_file, data_line);
read (data_line, data_byte_hi);
file_close(data_file);
in_broadcast <= data_byte_hi & data_byte_lo;
end if;
end if;
end process;
-- process checking the validity of the incoming consumed data as they are read from nanoFIP slone bus
------------------------------------------------------------------------------------------------------
check_consumed_and_broadcast: process(slone_access_read)
begin
if slone_access_read ='0' then
if var_id = "01" then
if in_consumed = dat_i then
report " __ check OK __ The value read from the 16-bit stand-alone bus" &
" matches the one sent from FIP for the consumed variable" & LF;
else
report " #### check NOT OK #### The value read from the 16-bit stand-alone bus" &
" does not match the one sent from FIP for the consumed variable" & LF
severity warning;
end if;
elsif var_id = "10" then
if in_broadcast = dat_i then
report " __ check OK __ The value read from the 16-bit stand-alone bus" &
" matches the one sent from FIP for the broadcast variable" & LF;
else
report " #### check NOT OK #### The value read from the 16-bit stand-alone bus" &
" does not match the one sent from FIP for the broadcast variable" & LF
severity warning;
end if;
end if;
end if;
end process;
-- process building an image of the nanoFIP memory for the produced variable
----------------------------------------------------------------------------
building_produced: process
begin
if slone_access_write ='1' then
out_produced(2) <= dat_o(7 downto 0);
out_produced(3) <= dat_o(15 downto 8);
end if;
wait until uclk ='1';
end process;
-- process transcribing to a text file the image of the nanoFIP memory for the produced variable
------------------------------------------------------------------------------------------------
write_outgoing: process(slone_access_write)
file data_file : text;
variable data_line : line;
begin
if slone_access_write ='0' then
file_open(data_file,"../../sim/spec/data_vectors/tmp_var3_mem.txt",write_mode);
for i in 0 to max_frame_length-1 loop
hwrite (data_line, out_produced(i));
writeline (data_file, data_line);
end loop;
file_close(data_file);
end if;
end process;
end archi;
sim/spec/testbench/start_stop_gen.vhd deleted 100644 → 0
View file @ 71c1e137
-- Created by : G. Penacoba
-- Creation Date: May 2011
-- Description: generates start and stop pulses for test-bench
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
entity start_stop_gen is
port(
tstart_o : out std_logic;
tstop1_o : out std_logic;
tstop2_o : out std_logic;
tstop3_o : out std_logic;
tstop4_o : out std_logic;
tstop5_o : out std_logic
);
end start_stop_gen;
architecture behavioral of start_stop_gen is
signal tstart : std_logic:='0';
signal tstop1 : std_logic:='0';
signal tstop2 : std_logic:='0';
signal tstop3 : std_logic:='0';
signal tstop4 : std_logic:='0';
signal tstop5 : std_logic:='0';
signal pulse_channel : integer;
signal pulse_length : time;
begin
-- process reading the schedule of frame exchange from a text file
------------------------------------------------------------------
sequence: process
file sequence_file : text open read_mode is "data_vectors/pulses.txt";
variable sequence_line : line;
variable interval_time : time;
variable coma : string(1 to 1);
variable pulse_ch : integer;
variable pulse_lgth : time;
begin
readline (sequence_file, sequence_line);
read (sequence_line, interval_time);
read (sequence_line, coma);
read (sequence_line, pulse_ch);
read (sequence_line, coma);
read (sequence_line, pulse_lgth);
wait for interval_time;
pulse_channel <= pulse_ch;
pulse_length <= pulse_lgth;
if endfile(sequence_file) then
file_close(sequence_file);
wait;
end if;
end process;
start_extender: process
begin
wait until pulse_channel = 0;
tstart <= '1';
wait for pulse_length;
tstart <= '0';
end process;
stop1_extender: process
begin
wait until pulse_channel = 1;
tstop1 <= '1';
wait for pulse_length;
tstop1 <= '0';
end process;
stop2_extender: process
begin
wait until pulse_channel = 2;
tstop2 <= '1';
wait for pulse_length;
tstop2 <= '0';
end process;
stop3_extender: process
begin
wait until pulse_channel = 3;
tstop3 <= '1';
wait for pulse_length;
tstop3 <= '0';
end process;
stop4_extender: process
begin
wait until pulse_channel = 4;
tstop4 <= '1';
wait for pulse_length;
tstop4 <= '0';
end process;
stop5_extender: process
begin
wait until pulse_channel = 5;
tstop5 <= '1';
wait for pulse_length;
tstop5 <= '0';
end process;
tstart_o <= tstart;
tstop1_o <= tstop1;
tstop2_o <= tstop2;
tstop3_o <= tstop3;
tstop4_o <= tstop4;
tstop5_o <= tstop5;
end behavioral;
sim/spec/testbench/tb_masterFIP.vhd
View file @ aae395c5
......@@ -218,7 +218,47 @@ port
jc_tck_o : out std_logic);
end component;
component user_interface
port(
urstn_from_nf : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
rstpon_o : out std_logic;
uclk_o : out std_logic;
urstn_to_nf : out std_logic;
var1_acc_o : out std_logic;
var2_acc_o : out std_logic;
var3_acc_o : out std_logic;
ack_i : in std_logic;
dat_i : in std_logic_vector(15 downto 0);
adr_o : out std_logic_vector(9 downto 0);
cyc_o : out std_logic;
dat_o : out std_logic_vector(15 downto 0);
rst_o : out std_logic;
stb_o : out std_logic;
wclk_o : out std_logic;
we_o : out std_logic
);
end component;
component board_settings
port(
s_id_i : in std_logic_vector(1 downto 0);
c_id_o : out std_logic_vector(3 downto 0);
m_id_o : out std_logic_vector(3 downto 0);
nostat_o : out std_logic;
p3_lgth_o : out std_logic_vector(2 downto 0);
rate_o : out std_logic_vector(1 downto 0);
slone_o : out std_logic;
subs_o : out std_logic_vector(7 downto 0)
);
end component;
-----------------------------------------------------------------------------
-- CMD_ROUTER component
-----------------------------------------------------------------------------
......@@ -240,8 +280,7 @@ constant pll_clk_period : time:= 8 ns;
constant g_width : integer:= 32;
constant g_span : integer:= 32;
constant spec_clk_period : time:= 50 ns;
signal nanoFIP_clk_period : time:= 25 ns;
constant start_retrig_period : time:= 512 ns;
--signal nanoFIP_clk_period : time:= 25 ns;
-- Number of Models receiving commands
constant N_BFM : integer := 1; -- 0 : GN412X_BFM in Model Mode
......@@ -317,7 +356,7 @@ signal spec_led_red : std_logic;
signal fd_rxcdn, fd_rxd, fd_txer, fd_wdgn, fd_rstn, fd_txck, fd_txena, fd_txd : std_logic;
signal consu_data : std_logic_vector (15 downto 0);
signal nanoFIP_rxcdn, nanoFIP_txena, nanoFIP_txck, nanoFIP_rstno ,nanoFIP_wdgn : std_logic;
signal nanoFIP_clk : std_logic:='0';
signal nanoFIP_clk : std_logic;
signal ext_sync : std_logic := '0';
......@@ -353,6 +392,44 @@ signal spare : std_logic;
signal TX_ERROR : std_logic;
signal GPIO : std_logic_vector(15 downto 0);
signal rstpon : std_logic; --! Power On Reset, active low
signal uclk : std_logic; --! 40 MHz clock
signal urst_to_nf : std_logic; --! Initialisation control, active low
signal urst_from_nf : std_logic; --! Reset output, active low
signal var1_rdy : std_logic; --! Variable 1 ready
signal var1_acc : std_logic; --! Variable 1 access
signal var2_rdy : std_logic; --! Variable 2 ready
signal var2_acc : std_logic; --! Variable 2 access
signal var3_rdy : std_logic; --! Variable 3 ready
signal var3_acc : std_logic; --! Variable 3 access
signal u_cacer : std_logic; --! nanoFIP status byte, bit 2
signal u_pacer : std_logic; --! nanoFIP status byte, bit 3
signal r_tler : std_logic; --! nanoFIP status byte, bit 4
signal r_fcser : std_logic; --! nanoFIP status byte, bit 5
signal clk : std_logic:='1';
signal reset : std_logic;
signal ack : std_logic:='0';
signal dat_from_fip : std_logic_vector(15 downto 0);
signal adr : std_logic_vector(9 downto 0);
signal cyc : std_logic;
signal dat_to_fip : std_logic_vector(15 downto 0);
signal rst : std_logic := '0';
signal stb : std_logic;
signal wclk : std_logic;
signal we : std_logic;
signal rate : std_logic_vector (1 downto 0); --! Bit rate
signal subs : std_logic_vector (7 downto 0); --! Subscriber number coding.
signal s_id : std_logic_vector (1 downto 0); --! Identification selection
signal m_id : std_logic_vector (3 downto 0); --! Model identification settings
signal c_id : std_logic_vector (3 downto 0); --! Constructor identification settings
signal p3_lgth : std_logic_vector (2 downto 0); --! Produced variable data length
signal slone : std_logic; --! Stand-alone mode
signal nostat : std_logic; --! No NanoFIP status transmission
-----------------------------------------------------------------------------
-- Command Router Signals
......@@ -419,11 +496,13 @@ begin
agent: nanofip
port map(
c_id_i => (others => '0'),
m_id_i => (others => '0'),
p3_lgth_i => (others => '0'),
rate_i => "01",
subs_i => "00000011",
uclk_i => nanoFIP_clk,
c_id_i => c_id,
m_id_i => m_id,
p3_lgth_i => p3_lgth,
rate_i => rate,
subs_i => subs,
fd_rxcdn_i => nanoFIP_rxcdn,
fd_rxd_i => fd_txd,
......@@ -435,38 +514,80 @@ begin
fd_txd_o => fd_rxd,
fd_txena_o => nanoFIP_txena,
nostat_i => '1',
nostat_i => nostat,
rstin_i => (rst_n),--was not
rstpon_i => '1',
slone_i => '1',
uclk_i => nanoFIP_clk,
var1_acc_i => '0',
var2_acc_i => '0',
var3_acc_i => '0',
wclk_i => nanoFIP_clk,
adr_i => (others => '0'),
cyc_i => '0',
dat_i => consu_data,
rst_i => '0',
stb_i => '0',
we_i => '0',
jc_tdo_i => '0',
rston_o => open,
slone_i => '0',
rston_o => urst_from_nf,
var1_acc_i => var1_acc,
var2_acc_i => var2_acc,
var3_acc_i => var3_acc,
wclk_i => wclk,
rst_i => rst,
ack_o => ack,
adr_i => adr,
cyc_i => cyc,
dat_i => dat_to_fip,
dat_o => dat_from_fip,
stb_i => stb,
we_i => we,
var1_rdy_o => var1_rdy,
var2_rdy_o => var2_rdy,
var3_rdy_o => var3_rdy,
s_id_o => open,
r_fcser_o => open,
r_tler_o => open,
u_cacer_o => open,
u_pacer_o => open,
var1_rdy_o => open,
var2_rdy_o => open,
var3_rdy_o => open,
ack_o => open,
jc_tdo_i => '0',
jc_tms_o => open,
jc_tdi_o => open,
jc_tck_o => open,
dat_o => consu_data);
jc_tck_o => open);
user_logic: user_interface
port map(
uclk_o => nanoFIP_clk,
urstn_from_nf => urst_from_nf,
rstpon_o => open,
urstn_to_nf => open,
var1_rdy_i => var1_rdy,
var2_rdy_i => var2_rdy,
var3_rdy_i => var3_rdy,
var1_acc_o => var1_acc,
var2_acc_o => var2_acc,
var3_acc_o => var3_acc,
ack_i => ack,
dat_i => dat_from_fip,
adr_o => adr,
cyc_o => cyc,
dat_o => dat_to_fip,
rst_o => rst,
stb_o => stb,
wclk_o => wclk,
we_o => we
);
board: board_settings
port map(
s_id_i => s_id,
c_id_o => c_id,
m_id_o => m_id,
nostat_o => nostat,
p3_lgth_o => p3_lgth,
rate_o => rate,
slone_o => slone,
subs_o => subs
);
CMD_ERR <= (others => '0');
......@@ -601,11 +722,11 @@ begin
wait for spec_clk_period/2;
end process;
nanoFIP_clock: process
begin
nanoFIP_clk <= not (nanoFIP_clk) after 1 ns;
wait for nanoFIP_clk_period/2;
end process;
-- nanoFIP_clock: process
-- begin
-- nanoFIP_clk <= not (nanoFIP_clk) after 1 ns;
-- wait for nanoFIP_clk_period/2;
-- end process;
--ext_sync <= '1' after 8500 ns, '0' after 8580 ns,
-- '1' after 194000 ns, '0' after 194080 ns,
......
sim/spec/testbench/tb_package.vhd 0 → 100644
View file @ aae395c5
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package tb_package is
constant max_frame_length : integer := 131;
subtype byte_count_type is integer range 0 to max_frame_length-1;
type vector_type is array (max_frame_length-1 downto 0) of std_logic_vector(7 downto 0);
constant reset_max_latency : time := 2 ms;
subtype byte_slice is integer range 0 to 7;
subtype byte_width is integer range 8 downto 1;
subtype jitter_time is time range 0 fs to 1 ms;
component hex_byte_transcriber
port(
input : in std_logic_vector(7 downto 0);
output : out string (1 to 2)
);
end component;
component bin_byte_transcriber
port(
input : in std_logic_vector(7 downto 0);
output : out string (1 to 8)
);
end component;
end tb_package;
package body tb_package is
end tb_package;
sim/spec/testbench/user_access_monitor.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: November 2010
-- Description: Tracks the user access errors of the user interface for
-- checking when nanoFIP reports.
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity user_access_monitor is
port(
cyc : in std_logic;
uclk_period : in time;
urstn_from_nf : in std_logic;
slone_access_read : in std_logic;
slone_access_write : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
var_id : in std_logic_vector(1 downto 0);
var1_acc_o : out std_logic;
var2_acc_o : out std_logic;
var3_acc_o : out std_logic
);
end user_access_monitor;
architecture archi of user_access_monitor is
signal station_adr : std_logic_vector(7 downto 0);
signal ucacerr : boolean;
signal upacerr : boolean;
signal rst_latency_reached : boolean;
signal urst_from_nf_asserted : boolean;
signal urst_from_nf_assertion : time:=0 fs;
signal var1_acc : std_logic;
signal var2_acc : std_logic;
signal var3_acc : std_logic;
signal var3_fresh : boolean;
signal vreset_second_byte : std_logic_vector(7 downto 0);
signal vreset_hist_opened_ok : boolean;
signal vreset_time : time;
signal previous_vreset_time : time;
begin
var1_acc_o <= var1_acc;
var2_acc_o <= var2_acc;
var3_acc_o <= var3_acc;
-- process generating the different variable access signals
-----------------------------------------------------------
user_access: process(var_id, cyc, slone_access_read, slone_access_write)
begin
case var_id is
when "01" =>
var1_acc <= cyc or slone_access_read;
var2_acc <= '0';
var3_acc <= slone_access_write;
when "10" =>
var1_acc <= '0';
var2_acc <= cyc or slone_access_read;
var3_acc <= slone_access_write;
when "11" =>
var1_acc <= slone_access_read;
var2_acc <= slone_access_read;
var3_acc <= cyc or slone_access_write;
when others =>
var1_acc <= slone_access_read;
var2_acc <= slone_access_read;
var3_acc <= slone_access_write;
end case;
end process;
-- 2 proccesses generating the current status of the user access errors
-----------------------------------------------------------------------
user_c_access_error: process(var1_rdy_i, var2_rdy_i, var3_rdy_i,
var1_acc, var2_acc)
begin
if (var1_acc ='1' and var1_rdy_i ='0')
or (var2_acc ='1' and var2_rdy_i ='0') then
ucacerr <= TRUE;
elsif var3_rdy_i'event and var3_rdy_i ='1' then
ucacerr <= FALSE after 1 ps;
end if;
end process;
user_p_access_error: process(var3_rdy_i, var3_acc)
begin
if (var3_acc ='1' and var3_rdy_i ='0') then
upacerr <= TRUE;
elsif var3_rdy_i'event and var3_rdy_i ='1' then
upacerr <= FALSE after 1 ps;
end if;
end process;
-- process tracking the current freshness of the data in the memory for the produced variable
---------------------------------------------------------------------------------------------
var3_freshness:process(var3_rdy_i, var3_acc)
begin
if var3_acc ='1' then
var3_fresh <= TRUE;
elsif var3_rdy_i'event and var3_rdy_i ='1' then
var3_fresh <= FALSE after 1 ps;
end if;
end process;
-- process transcribing the current status of the user access errors
-- and the produced variable freshness to a text file
-------------------------------------------------------------------
write_produced_status:process(var3_rdy_i)
file data_file : text;
variable data_line : line;
begin
if var3_rdy_i'event and var3_rdy_i ='1' then
file_open(data_file,"../../sim/spec/data_vectors/tmp_err_and_fresh.txt",write_mode);
write (data_line, ucacerr);
writeline (data_file, data_line);
write (data_line, upacerr);
writeline (data_file, data_line);
write (data_line, var3_fresh);
writeline (data_file, data_line);
file_close(data_file);
end if;
end process;
-- process for the user_acc register to be expected on the Produced Frames
------------------------------------------------------------------------------------
-- reporting: process(ucacerr, upacerr)
-- begin
-- assert not(ucacerr or upacerr)
-- report " The user logic access violates the VAR_RDY condition "
-- & "and should generate a nanoFIP status error" & LF
-- severity warning;
-- end process;
reporting: process(var1_rdy_i, var1_acc, var2_rdy_i, var2_acc, var3_rdy_i, var3_acc)
begin
assert not(var1_acc ='1' and var1_rdy_i ='0')
report " ++ The user logic memory access violates the VAR1_RDY condition of the Consumed variable." & LF &
" ++ Reading the memory when the signal is not active may lead to retrieval of incorrect data." & LF &
" ++ This should activate the corresponding access error flag on the nanoFIP status byte of the Produced variable." & LF
severity warning;
assert not(var2_acc ='1' and var2_rdy_i ='0')
report " ++ The user logic memory access violates the VAR2_RDY condition of the Broadcast variable." & LF &
" ++ Reading the memory when the signal is not active may lead to retrieval of incorrect data." & LF &
" ++ This should activate the corresponding access error flag on the nanoFIP status byte of the Produced variable." & LF
severity warning;
assert not(var3_acc ='1' and var3_rdy_i ='0')
report " ++ The user logic memory access violates the VAR3_RDY condition of the Produced variable." & LF &
" ++ Writing the memory when the signal is not active may lead to corruption of the data." & LF &
" ++ This should activate the corresponding access error flag on the nanoFIP status byte of the Produced variable." & LF
severity warning;
end process;
-- process extracting the history information for the reset
-- from temporary text files
-----------------------------------------------------------
check_for_reset_history: process--(urstn_from_nf)
file vhist_file : text;
variable vhist_line : line;
variable vfile_status : FILE_OPEN_STATUS;
file config_file : text;
variable config_line : line;
variable vrst_time : time;
variable second_byte : std_logic_vector(7 downto 0);
variable station_adr_tmp : std_logic_vector(7 downto 0);
begin
-- if urstn_from_nf ='0' then
wait for 0 fs;
wait for 0 fs;
wait for 0 fs;
file_open(vfile_status, vhist_file,"../../sim/spec/data_vectors/tmp_vreset_hist.txt",read_mode);
if vfile_status = open_ok then
readline (vhist_file, vhist_line);
read (vhist_line, vrst_time);
readline (vhist_file, vhist_line);
readline (vhist_file, vhist_line);
hread (vhist_line, second_byte);
report " ++ tmp_vreset_hist";
file_close(vhist_file);
vreset_hist_opened_ok <= TRUE;
vreset_time <= vrst_time;
vreset_second_byte <= second_byte;
else
vreset_hist_opened_ok <= FALSE;
end if;
file_open(config_file,"../../sim/spec/data_vectors/tmp_board_config.txt",read_mode);
readline (config_file, config_line);
readline (config_file, config_line);
readline (config_file, config_line);
readline (config_file, config_line);
readline (config_file, config_line);
readline (config_file, config_line);
hread (config_line, station_adr_tmp);
file_close(config_file);
station_adr <= station_adr_tmp;
-- end if;
wait for uclk_period;
end process;
process(urstn_from_nf)
begin
if urstn_from_nf'event and urstn_from_nf ='0' then
urst_from_nf_assertion <= now;
end if;
end process;
reset_surveillance: process
begin
wait for 0 ps;
wait for 0 ps;
wait for 0 ps;
previous_vreset_time <= vreset_time;
if previous_vreset_time /= vreset_time then
urst_from_nf_asserted <= FALSE;
rst_latency_reached <= FALSE;
elsif urstn_from_nf = '0' then
urst_from_nf_asserted <= TRUE;
elsif vreset_hist_opened_ok and ((now - vreset_time) > reset_max_latency) and (vreset_second_byte = station_adr) then
rst_latency_reached <= TRUE;
end if;
wait for uclk_period;
end process;
reset_reporting: process(urst_from_nf_asserted, rst_latency_reached)--, urst_from_nf_assertion)
begin
if rst_latency_reached and not urst_from_nf_asserted then
report " #### Check NOT OK #### " & time'image(reset_max_latency) & " have passed and"
& LF & " nanoFIP has still not asserted the User reset (RSTON)" & LF
severity warning;
elsif urst_from_nf_asserted and not rst_latency_reached then
if not (vreset_hist_opened_ok and (vreset_second_byte = station_adr)) then
report " #### Check NOT OK #### NanoFIP has asserted the User reset (RSTON)"
& LF & " although no action or event prompted it" & LF
severity warning;
else
if vreset_time < urst_from_nf_assertion and urst_from_nf_assertion < vreset_time + reset_max_latency then
if vreset_second_byte = station_adr then
report " __ Check OK __ After " & time'image(urst_from_nf_assertion - vreset_time) & " NanoFIP asserts"
& LF & " the User reset (RSTON) in response to the presence of nanoFIP station address"
& LF & " in the second byte of the reset variable sent by the Bus Arbitrer" & LF;
else
report " #### Check NOT OK #### NanoFIP has asserted the User reset (RSTON) in response to the Reset variable "
& LF & " although the station address was not present in the second byte" & LF
severity warning;
end if;
elsif (urst_from_nf_assertion > (vreset_time + reset_max_latency)) and (vreset_second_byte = station_adr) then
report " #### Check NOT OK #### NanoFIP has asserted now the User reset (RSTON). This is too late"
& LF & " with respect to the generating event to consider it a proper reaction" & LF
severity warning;
end if;
end if;
end if;
end process;
reset_reporting2: process(urstn_from_nf)
variable urstfromnf_deassertion : time;
begin
if urstn_from_nf'event and urstn_from_nf ='0' and urst_from_nf_asserted then
report " #### Check NOT OK #### NanoFIP has asserted the User reset (RSTON) again"
& LF & " although no action or event prompted it" & LF
severity warning;
end if;
if urstn_from_nf'event and urstn_from_nf ='1' and now /= 0 fs then
urstfromnf_deassertion := now;
report " NanoFIP has kept the User Reset asserted for "
& time'image(urstfromnf_deassertion - urst_from_nf_assertion) & LF;
end if;
end process;
-- reset_reporting: process
-- variable urstfromnf_assertion : time;
-- variable rst_allowed_source_time : time;
-- begin
-- if urstn_from_nf'event and urstn_from_nf ='0' then
-- wait for 0 ps;
-- urstfromnf_assertion := now;
-- rst_allowed_source_time := urstfromnf_assertion - reset_max_latency;
-- urst_from_nf_assertion <= urstfromnf_assertion;
--
-- if vreset_hist_opened_ok
-- and rst_allowed_source_time <= vreset_time and vreset_time <= urstfromnf_assertion
-- and vreset_second_byte = station_adr then
-- report " __ Check OK __ After " & time'image(urstfromnf_assertion - vreset_time)
-- & LF & " NanoFIP asserts the User Reset (RSTON)"
-- & LF & " in response to the presence of nanoFIP station address"
-- & LF & " in the second byte of the reset variable sent by the Bus Arbitrer" & LF;
--
-- else
-- report " #### Check NOT OK #### NanoFIP has asserted the User Reset (RSTON)"
-- & LF & " although no action or event prompted it" & LF
-- severity warning;
-- end if;
-- end if;
-- wait on urstn_from_nf;
-- end process;
end archi;
sim/spec/testbench/user_config.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: September 2010
-- Description: Module for the readout of the configuration settings from a
-- text file.
-- Modified by: G. Penacoba
-- Modification Date: January 2011.
-- Modification consisted on: Times of resets are registered in tmp files for use by other units.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity user_config is
port(
config_validity : out time;
uclk_period : out time;
ureset_length : out time;
wclk_period : out time;
wreset_length : out time;
preset_length : out time
);
end user_config;
architecture archi of user_config is
signal read_config_trigger : std_logic;
signal report_config_trigger: std_logic;
signal s_uclk_period : time;
signal s_ureset_length : time;
signal s_wclk_period : time;
signal s_wreset_length : time;
signal s_preset_length : time;
begin
-- process reading config values from a file
---------------------------------------------
read_config: process
file config_file : text open read_mode is "../../sim/spec/data_vectors/user_logic_config.txt";
variable config_line : line;
variable validity_time : time;
variable uclk_period_config : time;
variable ureset_lgth_config : time;
variable wclk_period_config : time;
variable wreset_lgth_config : time;
variable preset_lgth_config : time;
begin
readline (config_file, config_line);
read (config_line, uclk_period_config);
readline (config_file, config_line);
read (config_line, wclk_period_config);
readline (config_file, config_line);
read (config_line, preset_lgth_config);
readline (config_file, config_line);
read (config_line, ureset_lgth_config);
readline (config_file, config_line);
read (config_line, wreset_lgth_config);
readline (config_file, config_line);
read (config_line, validity_time);
if endfile(config_file) then
file_close(config_file);
end if;
config_validity <= validity_time;
s_uclk_period <= uclk_period_config;
uclk_period <= uclk_period_config;
s_wclk_period <= wclk_period_config;
wclk_period <= wclk_period_config;
s_preset_length <= preset_lgth_config;
preset_length <= preset_lgth_config;
s_ureset_length <= ureset_lgth_config;
ureset_length <= ureset_lgth_config;
s_wreset_length <= wreset_lgth_config;
wreset_length <= wreset_lgth_config;
read_config_trigger <= '1';
wait for validity_time - 1 ps;
read_config_trigger <= '0';
wait for 1 ps;
end process;
-- reporting processes
-----------------------
report_config_trigger <= read_config_trigger;
history: process(report_config_trigger)
file phist_file : text;
file uhist_file : text;
variable phist_line : line;
variable uhist_line : line;
variable prst_time : time;
variable urst_time : time;
begin
if report_config_trigger'event and report_config_trigger ='1' then
if s_preset_length > 0 fs then
prst_time := now;
file_open(phist_file, "../../sim/spec/data_vectors/tmp_preset_hist.txt", write_mode);
write (phist_line, prst_time);
writeline (phist_file, phist_line);
file_close(phist_file);
end if;
if s_ureset_length > 0 fs then
urst_time := now;
file_open(uhist_file, "../../sim/spec/data_vectors/tmp_ureset_hist.txt", write_mode);
write (uhist_line, urst_time);
writeline (uhist_file, uhist_line);
file_close(uhist_file);
end if;
end if;
end process;
reporting: process(report_config_trigger)
begin
if report_config_trigger'event and report_config_trigger ='1' then
if now = 0 ps then
report LF & "User logic configuration settings" & LF &
"---------------------------------" & LF &
"User Clock period : " & time'image(s_uclk_period) & LF &
"Wishbone interface Clock period: " & time'image(s_wclk_period) & LF & LF;
end if;
if s_preset_length > 0 fs then
report " ++ The power-on reset (RSTPON) is asserted for " & time'image(s_preset_length)
& LF & " ++ As a consequence, nanoFIP should reset its internal registers and error flags,"
& LF & " ++ assert the Fieldrive reset (FD_RSTN)"
& LF & " ++ and reset the VAR_RDY user interface signals" & LF
severity warning;
end if;
if s_ureset_length > 0 fs then
report " ++ The user reset (RSTIN) is asserted for " & time'image(s_ureset_length)
& LF & " ++ As a consequence, nanoFIP should reset its internal registers and error flags,"
& LF & " ++ assert the Fieldrive reset (FD_RSTN)"
& LF & " ++ and reset the VAR_RDY user interface signals" & LF
severity warning;
end if;
if s_wreset_length > 0 fs then
report " ++ The wishbone reset (RST_I) is asserted for " & time'image(s_wreset_length) & LF
severity warning;
end if;
end if;
end process;
end archi;
sim/spec/testbench/user_interface.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: MAy 2010
-- Description: Module emulating all the user logic activity
-- Modified by: G. Penacoba
-- Modification Date: September 2010
-- Modification consisted on: Configuration settings retrieved from a text file through an independent module.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.tb_package.all;
entity user_interface is
port(
urstn_from_nf : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
rstpon_o : out std_logic;
uclk_o : out std_logic;
urstn_to_nf : out std_logic;
var1_acc_o : out std_logic;
var2_acc_o : out std_logic;
var3_acc_o : out std_logic;
ack_i : in std_logic;
dat_i : in std_logic_vector(15 downto 0);
adr_o : out std_logic_vector(9 downto 0);
cyc_o : out std_logic;
dat_o : out std_logic_vector(15 downto 0);
rst_o : out std_logic;
stb_o : out std_logic;
wclk_o : out std_logic;
we_o : out std_logic
);
end user_interface;
architecture archi of user_interface is
component slone_interface
port(
launch_slone_read : in std_logic;
launch_slone_write : in std_logic;
uclk : in std_logic;
ureset : in std_logic;
dat_o : out std_logic_vector(15 downto 0);
slone_access_read : out std_logic;
slone_access_write : out std_logic
);
end component;
component slone_monitor
port(
dat_i : in std_logic_vector(15 downto 0);
dat_o : in std_logic_vector(15 downto 0);
slone_access_read : in std_logic;
slone_access_write : in std_logic;
uclk : in std_logic;
ureset : in std_logic;
var_id : in std_logic_vector(1 downto 0)
);
end component;
component user_sequencer
port(
uclk_period : in time;
wclk_period : in time;
block_size : out std_logic_vector(6 downto 0);
launch_slone_read : out std_logic;
launch_slone_write : out std_logic;
launch_wb_read : out std_logic;
launch_wb_write : out std_logic;
transfer_length : out std_logic_vector(6 downto 0);
transfer_offset : out std_logic_vector(6 downto 0);
var_id : out std_logic_vector(1 downto 0)
);
end component;
component user_access_monitor is
port(
cyc : in std_logic;
uclk_period : in time;
urstn_from_nf : in std_logic;
slone_access_read : in std_logic;
slone_access_write : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
var_id : in std_logic_vector(1 downto 0);
var1_acc_o : out std_logic;
var2_acc_o : out std_logic;
var3_acc_o : out std_logic
);
end component;
component wishbone_interface
port(
block_size : in std_logic_vector(6 downto 0);
launch_wb_read : in std_logic;
launch_wb_write : in std_logic;
transfer_length : in std_logic_vector(6 downto 0);
transfer_offset : in std_logic_vector(6 downto 0);
var_id : in std_logic_vector(1 downto 0);
ack_i : in std_logic;
clk_i : in std_logic;
dat_i : in std_logic_vector(7 downto 0);
rst_i : in std_logic;
adr_o : out std_logic_vector(9 downto 0);
cyc_o : out std_logic;
dat_o : out std_logic_vector(7 downto 0);
stb_o : out std_logic;
we_o : out std_logic
);
end component;
component wishbone_monitor
port(
ack_i : in std_logic;
clk_o : in std_logic;
dat_i : in std_logic_vector(7 downto 0);
rst_o : in std_logic;
adr_o : in std_logic_vector(9 downto 0);
cyc_o : in std_logic;
dat_o : in std_logic_vector(7 downto 0);
stb_o : in std_logic;
we_o : in std_logic
);
end component;
component user_config is
port(
config_validity : out time;
uclk_period : out time;
ureset_length : out time;
wclk_period : out time;
wreset_length : out time;
preset_length : out time
);
end component;
signal adr : std_logic_vector(9 downto 0);
signal data_from_wb : std_logic_vector(7 downto 0);
signal stb : std_logic;
signal we : std_logic;
signal block_size : std_logic_vector(6 downto 0):="000" & x"0";
signal config_validity_time : time;
signal cyc : std_logic;
signal data_from_slone : std_logic_vector(15 downto 0);
signal memory_output : boolean;
signal slone_access_read : std_logic;
signal slone_access_write : std_logic;
signal slone_output : boolean;
signal launch_slone_read : std_logic:='0';
signal launch_slone_write : std_logic:='0';
signal launch_wb_read : std_logic:='0';
signal launch_wb_write : std_logic:='0';
signal transfer_length : std_logic_vector(6 downto 0):="000" & x"0";
signal transfer_offset : std_logic_vector(6 downto 0):="000" & x"0";
signal uclk : std_logic:='0';
signal uclk_period : time;
signal ureset : std_logic;
signal ureset_length : time;
signal var_id : std_logic_vector(1 downto 0):="00";
signal wclk : std_logic:='0';
signal wclk_period : time;
signal wreset : std_logic;
signal wreset_length : time;
signal preset : std_logic;
signal preset_length : time;
begin
user_clock: process
begin
wait for 0 us; -- wait needed for the config text file to be read
uclk <= not(uclk);
wait for uclk_period/2;
end process;
user_reset: process
begin
wait for 0 us; -- wait needed for the config text file to be read
if ureset_length > 0 ps then
ureset <= '1';
wait for ureset_length;
else
ureset <= '0';
wait for ureset_length;
end if;
ureset <= '0';
wait for config_validity_time - ureset_length;
end process;
wb_clock: process
begin
wait for 0 us; -- wait needed for the config text file to be read
wclk <= not(wclk);
wait for wclk_period/2;
end process;
wb_reset: process
begin
wait for 0 us; -- wait needed for the config text file to be read
if wreset_length > 0 ps then
wreset <= '1';
wait for wreset_length;
else
wreset <= '0';
wait for wreset_length;
end if;
wreset <= '0';
wait for config_validity_time - wreset_length;
end process;
por_reset: process
begin
wait for 0 us; -- wait needed for the config text file to be read
if preset_length > 0 ps then
preset <= '1';
wait for preset_length;
else
preset <= '0';
wait for preset_length;
end if;
preset <= '0';
wait for config_validity_time - preset_length;
end process;
slone_output_detector: process
begin
if launch_slone_write ='1' then
slone_output <= TRUE;
elsif memory_output then
slone_output <= FALSE;
end if;
wait until uclk ='1';
end process;
memory_output_detector: process
begin
if launch_wb_write ='1' then
memory_output <= TRUE;
elsif slone_output then
memory_output <= FALSE;
end if;
wait until wclk ='1';
end process;
sa_interface: slone_interface
port map(
launch_slone_read => launch_slone_read,
launch_slone_write => launch_slone_write,
uclk => uclk,
ureset => ureset,
dat_o => data_from_slone,
slone_access_read => slone_access_read,
slone_access_write => slone_access_write
);
sa_monitor: slone_monitor
port map(
dat_i => dat_i,
dat_o => data_from_slone,
slone_access_read => slone_access_read,
slone_access_write => slone_access_write,
uclk => uclk,
ureset => ureset,
var_id => var_id
);
user_sequence: user_sequencer
port map(
uclk_period => uclk_period,
wclk_period => wclk_period,
block_size => block_size,
launch_slone_read => launch_slone_read,
launch_slone_write => launch_slone_write,
launch_wb_read => launch_wb_read,
launch_wb_write => launch_wb_write,
transfer_length => transfer_length,
transfer_offset => transfer_offset,
var_id => var_id
);
user_acc_monitor: user_access_monitor
port map(
cyc => cyc,
uclk_period => uclk_period,
urstn_from_nf => urstn_from_nf,
slone_access_read => slone_access_read,
slone_access_write => slone_access_write,
var1_rdy_i => var1_rdy_i,
var2_rdy_i => var2_rdy_i,
var3_rdy_i => var3_rdy_i,
var_id => var_id,
var1_acc_o => var1_acc_o,
var2_acc_o => var2_acc_o,
var3_acc_o => var3_acc_o
);
wb_interface: wishbone_interface
port map(
block_size => block_size,
launch_wb_read => launch_wb_read,
launch_wb_write => launch_wb_write,
transfer_length => transfer_length,
transfer_offset => transfer_offset,
var_id => var_id,
ack_i => ack_i,
clk_i => wclk,
dat_i => dat_i(7 downto 0),
rst_i => wreset,
adr_o => adr,
cyc_o => cyc,
dat_o => data_from_wb,
stb_o => stb,
we_o => we
);
wb_monitor: wishbone_monitor
port map(
ack_i => ack_i,
clk_o => wclk,
dat_i => dat_i(7 downto 0),
rst_o => wreset,
adr_o => adr,
cyc_o => cyc,
dat_o => data_from_wb,
stb_o => stb,
we_o => we
);
user_configuration: user_config
port map(
config_validity => config_validity_time,
uclk_period => uclk_period,
ureset_length => ureset_length,
wclk_period => wclk_period,
wreset_length => wreset_length,
preset_length => preset_length
);
uclk_o <= uclk;
urstn_to_nf <= not(ureset);
rstpon_o <= not(preset);
adr_o <= adr;
cyc_o <= cyc;
rst_o <= wreset;
wclk_o <= wclk;
stb_o <= stb;
we_o <= we;
dat_o <= data_from_slone when slone_output
else x"00" & data_from_wb when memory_output
else (others=>'0');
end archi;
sim/spec/testbench/user_sequencer.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: March 2010
-- Description: Orders the sequence of actions of the user
-- Modified by: G. Penacoba
-- Modification Date: 23/08/2010
-- Modification consisted on: Name change
-- + addition of the other user interface signals
-- Modification Date: October 2010
-- Modification consisted on: Addition of access to schedule from a text file + reporting
-- + addition of user access error and freshness status signals
-- Modification Date: 1 November 2010
-- Modification consisted on: Management of user_access signals and errors and freshness status
-- moved to a different file.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity user_sequencer is
port(
uclk_period : in time;
wclk_period : in time;
block_size : out std_logic_vector(6 downto 0);
launch_slone_read : out std_logic;
launch_slone_write : out std_logic;
launch_wb_read : out std_logic;
launch_wb_write : out std_logic;
transfer_length : out std_logic_vector(6 downto 0);
transfer_offset : out std_logic_vector(6 downto 0);
var_id : out std_logic_vector(1 downto 0)
);
end user_sequencer;
architecture archi of user_sequencer is
signal blck_sze : integer:=0;
signal launch_slone_rd : std_logic:='0';
signal launch_slone_wr : std_logic:='0';
signal launch_wb_rd : std_logic:='0';
signal launch_wb_wr : std_logic:='0';
signal transfer_lgth : integer:=0;
signal transfer_offst : integer:=0;
signal var : integer:=0;
begin
-- process retrieving the sequence of actions performed by the user logic from a text file
------------------------------------------------------------------------------------------
sequence: process
file sequence_file : text open read_mode is "../../sim/spec/data_vectors/user_sequence.txt";
variable sequence_line : line;
file config_file : text;
variable config_line : line;
variable stand_by_time : time;
variable coma : string(1 to 1);
variable block_size_tmp : integer;
variable rd_wr : std_logic;
variable slone_cfig_tmp : std_logic_vector(0 downto 0);
variable trfer_lgth_tmp : integer;
variable trfer_ofst_tmp : integer;
variable var_id_tmp : integer;
begin
wait for 0 us;
readline (sequence_file, sequence_line);
readline (sequence_file, sequence_line);
readline (sequence_file, sequence_line);
wait for wclk_period;
loop
launch_slone_rd <= '0';
launch_slone_wr <= '0';
launch_wb_rd <= '0';
launch_wb_wr <= '0';
file_open(config_file,"../../sim/spec/data_vectors/tmp_board_config.txt",read_mode);
readline (config_file, config_line);
read (config_line, slone_cfig_tmp);
file_close(config_file);
-- report " FIRST slone config " & integer'image(to_integer(unsigned(slone_cfig_tmp)));
readline (sequence_file, sequence_line);
read (sequence_line, stand_by_time);
if not(endfile(sequence_file)) then
readline (sequence_file, sequence_line);
read (sequence_line, rd_wr);
read (sequence_line, coma);
read (sequence_line, var_id_tmp);
read (sequence_line, coma);
read (sequence_line, trfer_lgth_tmp);
read (sequence_line, coma);
read (sequence_line, trfer_ofst_tmp);
read (sequence_line, coma);
read (sequence_line, block_size_tmp);
else
file_close(sequence_file);
end if;
if slone_cfig_tmp ="1" then
wait for stand_by_time - uclk_period;
else
wait for stand_by_time - wclk_period;
end if;
var_id <= std_logic_vector(to_unsigned(var_id_tmp,2));
var <= var_id_tmp;
transfer_length <= std_logic_vector(to_unsigned(trfer_lgth_tmp,7));
transfer_lgth <= trfer_lgth_tmp;
transfer_offset <= std_logic_vector(to_unsigned(trfer_ofst_tmp,7));
transfer_offst <= trfer_ofst_tmp;
block_size <= std_logic_vector(to_unsigned(block_size_tmp,7));
blck_sze <= block_size_tmp;
file_open(config_file,"../../sim/spec/data_vectors/tmp_board_config.txt",read_mode);
readline (config_file, config_line);
read (config_line, slone_cfig_tmp);
file_close(config_file);
-- report " SECOND slone config " & integer'image(to_integer(unsigned(slone_cfig_tmp)));
if slone_cfig_tmp ="1" then
if rd_wr ='1' then
launch_slone_rd <= '0';
launch_slone_wr <= '1';
launch_wb_rd <= '0';
launch_wb_wr <= '0';
else
launch_slone_rd <= '1';
launch_slone_wr <= '0';
launch_wb_rd <= '0';
launch_wb_wr <= '0';
end if;
else
if rd_wr ='1' then
launch_slone_rd <= '0';
launch_slone_wr <= '0';
launch_wb_rd <= '0';
launch_wb_wr <= '1';
else
launch_slone_rd <= '0';
launch_slone_wr <= '0';
launch_wb_rd <= '1';
launch_wb_wr <= '0';
end if;
end if;
if slone_cfig_tmp ="1" then
wait for uclk_period;
else
wait for wclk_period;
end if;
end loop;
end process;
launch_slone_read <= launch_slone_rd;
launch_slone_write <= launch_slone_wr;
launch_wb_read <= launch_wb_rd;
launch_wb_write <= launch_wb_wr;
reporting: process(launch_slone_rd, launch_slone_wr, launch_wb_rd, launch_wb_wr)
begin
if launch_slone_rd ='1' then
report LF & " User logic reads 2 bytes from the 16-bit stand-alone bus"& LF;
elsif launch_slone_wr ='1' then
report LF & " User logic writes 2 bytes on the 16-bit stand-alone bus"& LF;
elsif launch_wb_rd ='1' then
if transfer_offst = 0 then
report LF & " User logic reads " & integer'image(transfer_lgth) &
" bytes of user data plus the length byte and the PDU type byte" &
" between address " & integer'image(transfer_offst+transfer_lgth+1) & " and address 0" &
" from variable " & integer'image(var) & " in nanoFIP memory" & LF;
else
report LF & " User logic reads " & integer'image(transfer_lgth) &
" bytes of user data" &
" between address " & integer'image(transfer_offst+transfer_lgth+1) &
" and address " & integer'image(transfer_offst+2) &
" from variable " & integer'image(var) & " in nanoFIP memory" & LF;
end if;
elsif launch_wb_wr ='1' then
report LF & " User logic writes " & integer'image(transfer_lgth) &
" bytes on variable " & integer'image(var) &
" in nanoFIP memory between address " & integer'image(transfer_offst+transfer_lgth+1) &
" and address " & integer'image(transfer_offst+2) & LF;
end if;
end process;
end archi;
sim/spec/testbench/wishbone_interface.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: February 2010
-- Description: Module to perform wishbone cycles (read/write in single or block transfer)
-- Modified by: G. Penacoba
-- Modification Date: October 2010
-- Modification consisted on: Memory counters on read adapted to include Length and PDU type bytes.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity wishbone_interface is
port(
block_size : in std_logic_vector(6 downto 0);
launch_wb_read : in std_logic;
launch_wb_write : in std_logic;
transfer_length : in std_logic_vector(6 downto 0);
transfer_offset : in std_logic_vector(6 downto 0);
var_id : in std_logic_vector(1 downto 0);
ack_i : in std_logic;
clk_i : in std_logic;
dat_i : in std_logic_vector(7 downto 0);
rst_i : in std_logic;
adr_o : out std_logic_vector(9 downto 0);
cyc_o : out std_logic;
dat_o : out std_logic_vector(7 downto 0);
stb_o : out std_logic;
we_o : out std_logic
);
end wishbone_interface;
architecture archi of wishbone_interface is
component encounter
generic(
width : integer:=16
);
port(
clk : in std_logic;
en : in std_logic;
reset : in std_logic;
start_value : in std_logic_vector(width-1 downto 0);
count : out std_logic_vector(width-1 downto 0);
count_done : out std_logic
);
end component;
constant zero : std_logic_vector(6 downto 0):=(others =>'0');
type wb_st_type is (idle, single, burst, rest);
signal wb_state, nxt_wb_state : wb_st_type:=idle;
signal add_count : std_logic_vector(9 downto 0);
signal burst_done : std_logic;
signal burst_size : std_logic_vector(6 downto 0):=(others=>'0');
signal cyc : std_logic;
signal data_for_mem : std_logic_vector(7 downto 0);
signal mem_count : std_logic_vector(6 downto 0);
signal mem_done : std_logic;
signal mem_length : std_logic_vector(6 downto 0):=(others=>'0');
signal mem_offset : std_logic_vector(6 downto 0):=(others=>'0');
signal reset_burst : std_logic;
signal reset_mem : std_logic;
signal stb : std_logic;
signal valid_bus_cycle : std_logic;
signal var_adr : std_logic_vector(1 downto 0):=(others=>'0');
signal we : std_logic:='0';
begin
-- wishbone interface state machine (sequential section)
-----------------------------------------------------------------------------
wb_fsm_seq: process
begin
if rst_i = '1' then
wb_state <= idle;
else
wb_state <= nxt_wb_state;
end if;
wait until clk_i ='1';
end process;
-- wishbone interface state machine (combinatorial section)
-----------------------------------------------------------------------------------
wb_fsm_comb: process (wb_state, launch_wb_read, launch_wb_write,
burst_size, ack_i, burst_done, mem_done)
begin
case wb_state is
when idle =>
cyc <= '0';
reset_burst <= '1';
reset_mem <= '1';
stb <= '0';
if (launch_wb_read /='0' or launch_wb_write /='0') then
if burst_size > zero then
nxt_wb_state <= burst;
else
nxt_wb_state <= single;
end if;
else
nxt_wb_state <= idle;
end if;
when single =>
cyc <= '1';
reset_burst <= '1';
reset_mem <= '0';
stb <= '1';
if ack_i ='0' then
nxt_wb_state <= single;
elsif mem_done ='1' then
nxt_wb_state <= idle;
else
nxt_wb_state <= rest;
end if;
when burst =>
cyc <= '1';
reset_burst <= '0';
reset_mem <= '0';
stb <= '1';
if ack_i ='0' then
nxt_wb_state <= burst;
elsif mem_done ='1' then
nxt_wb_state <= idle;
elsif burst_done ='1' then
nxt_wb_state <= rest;
else
nxt_wb_state <= burst;
end if;
when rest =>
cyc <= '1';
reset_burst <= '1';
reset_mem <= '0';
stb <= '0';
if burst_size > zero then
nxt_wb_state <= burst;
else
nxt_wb_state <= single;
end if;
when others =>
cyc <= '0';
reset_burst <= '1';
reset_mem <= '1';
stb <= '0';
nxt_wb_state <= idle;
end case;
end process;
-- latches for identifying the type of the memory access cycle
--------------------------------------------------------------
latch_inference: process (launch_wb_read, launch_wb_write)
begin
if launch_wb_read ='1' then
if block_size = zero then
burst_size <= zero;
else
burst_size <= block_size - ("000" & x"1");
end if;
if transfer_offset = zero then
mem_length <= transfer_length + ("000" & x"1");
mem_offset <= (others=>'0');
else
mem_length <= transfer_length - ("000" & x"1");
mem_offset <= transfer_offset + ("000" & x"2");
end if;
var_adr <= var_id -"01";
we <= '0';
elsif launch_wb_write ='1' then
if block_size = zero then
burst_size <= zero;
else
burst_size <= block_size - ("000" & x"1");
end if;
mem_length <= transfer_length - ("000" & x"1");
mem_offset <= transfer_offset + ("000" & x"2");
var_adr <= var_id -"01";
we <= '1';
end if;
end process;
add_count <= "0" & var_adr & (mem_count + mem_offset);
valid_bus_cycle <= stb and cyc and ack_i;
-- output signals
-----------------------
adr_o <= add_count;
cyc_o <= cyc;
dat_o <= data_for_mem;
stb_o <= stb;
we_o <= we;
-- process reading bytes from random data file
---------------------------------------------
read_store: process
file data_file: text open read_mode is "../../sim/spec/data_vectors/data_store.txt";
variable data_line: line;
variable data_byte: std_logic_vector(7 downto 0);
begin
readline (data_file, data_line);
hread (data_line, data_byte);
data_for_mem <= data_byte;
wait until clk_i ='1';
end process;
burst_counter: encounter
generic map(
width => 7
)
port map(
clk => clk_i,
en => valid_bus_cycle,
reset => reset_burst,
start_value => burst_size,
count => open,
count_done => burst_done
);
mem_counter: encounter
generic map(
width => 7
)
port map(
clk => clk_i,
en => valid_bus_cycle,
reset => reset_mem,
start_value => mem_length,
count => mem_count,
count_done => mem_done
);
end archi;
sim/spec/testbench/wishbone_monitor.vhd 0 → 100644
View file @ aae395c5
-- Created by : G. Penacoba
-- Creation Date: October 2010
-- Description: Block performing the validity check of the exchanged data from the user side.
-- Monitors only the contents of the memory through the wishbone interface signals.
-- Modified by:
-- Modification Date:
-- Modification consisted on:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
use std.textio.all;
use work.tb_package.all;
entity wishbone_monitor is
port(
ack_i : in std_logic;
clk_o : in std_logic;
dat_i : in std_logic_vector(7 downto 0);
rst_o : in std_logic;
adr_o : in std_logic_vector(9 downto 0);
cyc_o : in std_logic;
dat_o : in std_logic_vector(7 downto 0);
stb_o : in std_logic;
we_o : in std_logic
);
end wishbone_monitor;
architecture archi of wishbone_monitor is
signal adr : byte_count_type;
signal errct : byte_count_type;
signal errct_trig : std_logic:='0';
signal in_broadcast : vector_type;
signal in_consumed : vector_type;
signal out_produced : vector_type;
signal valid_bus_cycle : boolean;
signal var_id : integer:=0;
signal writing_produced : boolean;
begin
-- process reading from a text file the data sent by FIP for consumption
------------------------------------------------------------------------
read_incoming: process(cyc_o, var_id)
file data_file : text;
variable data_line : line;
variable data_byte : std_logic_vector(7 downto 0);
variable data_vector : vector_type;
variable i : integer:=0;
begin
if cyc_o ='1' then
if var_id = 1 then
data_vector := (others => x"00");
file_open(data_file,"../../sim/spec/data_vectors/tmp_var1_mem.txt",read_mode);
while not(endfile(data_file)) loop
readline (data_file, data_line);
hread (data_line, data_byte);
data_vector(i) := data_byte;
i := i+1;
end loop;
file_close(data_file);
i := 0;
in_consumed <= data_vector;
elsif var_id = 2 then
data_vector := (others => x"00");
file_open(data_file,"../../sim/spec/data_vectors/tmp_var2_mem.txt",read_mode);
while not(endfile(data_file)) loop
readline (data_file, data_line);
hread (data_line, data_byte);
data_vector(i) := data_byte;
i := i+1;
end loop;
file_close(data_file);
i := 0;
in_broadcast <= data_vector;
end if;
end if;
end process;
-- process checking the validity of the incoming consumed data as they are retrieved from nanoFIP memory
--------------------------------------------------------------------------------------------------------
check_consumed_and_broadcast: process
begin
if valid_bus_cycle then
if var_id = 1 then
if in_consumed(adr) /= dat_i then
report LF & " #### check NOT OK #### Value retrieved from memory DAT_I::::" & integer'image(to_integer(unsigned(dat_i))) &
"in address " & integer'image(adr) &
" of the Consumed variable does not match the corresponding one sent from FIP by the BA" & LF
severity warning;
errct_trig <= '1';
end if;
elsif var_id = 2 then
if in_broadcast(adr) /= dat_i then
report " #### check NOT OK #### Value retrieved from memory in address " &
integer'image(adr) & " of the Broadcast variable does not match the corresponding one sent from FIP by the BA" & LF
severity warning;
errct_trig <= '1';
end if;
end if;
else
errct_trig <= '0';
end if;
wait until clk_o ='1';
end process;
count_errors: process
begin
if cyc_o ='1' then
if errct_trig ='1' then
errct <= errct + 1;
end if;
else
errct <= 0;
end if;
wait until clk_o ='1';
end process;
report_errors: process (cyc_o)
begin
if cyc_o'event and cyc_o= '0' then
if errct = 0 and we_o = '0' and now /= 0 fs then
report " __ check OK __ All values found in memory match the ones sent from FIP" & LF & LF
severity note;
end if;
end if;
end process;
-- process building an image of the nanoFIP memory for the produced variable
----------------------------------------------------------------------------
produced_memory:process
begin
if writing_produced and valid_bus_cycle then
out_produced(adr) <= dat_o;
end if;
wait until clk_o ='1';
end process;
-- process transcribing to a text file the image of the nanoFIP memory for the produced variable
------------------------------------------------------------------------------------------------
write_outgoing: process(writing_produced)
file data_file : text;
variable data_line : line;
begin
if writing_produced'event and writing_produced = FALSE then
file_open(data_file,"../../sim/spec/data_vectors/tmp_var3_mem.txt",write_mode);
for i in 0 to max_frame_length-1 loop
hwrite (data_line, out_produced(i));
writeline (data_file, data_line);
end loop;
file_close(data_file);
end if;
end process;
var_id <= to_integer(unsigned(adr_o(8 downto 7)))+1;
adr <= to_integer(unsigned(adr_o(6 downto 0)));
valid_bus_cycle <= cyc_o ='1' and stb_o ='1' and ack_i ='1';
writing_produced <= cyc_o ='1' and var_id = 3 and we_o ='1';
end archi;
syn/spec/spec_masterFIP.xise
View file @ aae395c5
......@@ -16,12 +16,12 @@
<files>
<file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
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......@@ -40,7 +40,7 @@
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......@@ -60,8 +60,8 @@
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......@@ -92,7 +92,7 @@
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......@@ -100,7 +100,7 @@
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......@@ -112,52 +112,52 @@
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......@@ -180,20 +180,20 @@
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......@@ -232,8 +232,8 @@
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......@@ -300,16 +300,16 @@
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......@@ -328,8 +328,8 @@
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......@@ -344,8 +344,8 @@
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......@@ -480,8 +480,8 @@
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......@@ -628,40 +628,40 @@
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......@@ -670,24 +670,24 @@
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<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="blk_mem_gen_v7_3.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
......@@ -921,6 +997,7 @@
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
......@@ -938,7 +1015,9 @@
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
......@@ -991,10 +1070,12 @@
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -1002,8 +1083,10 @@
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spec_masterFIP|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../top/spec/spec_masterFIP.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/tb_masterFIP/dut" xil_pn:valueState="non-default"/>
......@@ -1021,13 +1104,18 @@
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="All" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
......@@ -1035,6 +1123,8 @@
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
......@@ -1066,6 +1156,9 @@
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -1091,6 +1184,7 @@
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
......@@ -1143,22 +1237,28 @@
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_masterFIP" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -1167,7 +1267,13 @@
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -1181,6 +1287,7 @@
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -1191,11 +1298,14 @@
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
......@@ -1216,7 +1326,9 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<bindings>
<binding xil_pn:location="/spec_masterFIP" xil_pn:name="../../top/spec/spec_masterFIP.ucf"/>
</bindings>
<libraries/>
......
top/spec/spec_masterFIP.vhd
View file @ aae395c5
......@@ -230,7 +230,7 @@ architecture rtl of spec_masterFIP is
signal clk_40m_sys, rst_sys : std_logic;
signal rst_sys_n : std_logic;
signal pllout_clk_sys, pllout_clk_sys_fb : std_logic;
signal sys_locked, pll_status : std_logic;
signal sys_locked : std_logic;
-- WISHBONE from crossbar master port
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
......@@ -243,7 +243,7 @@ architecture rtl of spec_masterFIP is
-- Carrier 1-wire
signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
-- VIC
signal fmc_eic_irq, irq_to_gn4124 : std_logic;
signal fmc_eic_irq : std_logic;
signal fmc_eic_irq_synch : std_logic_vector (1 downto 0);
-- EEPROM on mezzanine
signal tdc_scl_out, tdc_scl_in, tdc_sda_out, tdc_sda_in: std_logic;
......@@ -312,7 +312,7 @@ begin
---------------------------------------------------------------------------------------------------
-- Reset for 62.5 MHz clk domain --
-- Reset for 40 MHz clk domain --
---------------------------------------------------------------------------------------------------
cmp_spec_rst_gen : spec_reset_gen
......@@ -385,8 +385,8 @@ begin
vc_rdy_i => vc_rdy_i,
-- Interrupt interface
dma_irq_o => open,
irq_p_i => irq_to_gn4124,
irq_p_o => irq_p_o,
irq_p_i => '0',
irq_p_o => open,
-- CSR WISHBONE interface (master pipelined)
csr_clk_i => clk_40m_sys,
csr_adr_o => gn_wb_adr,
......@@ -562,7 +562,7 @@ begin
carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_info_stat_p2l_pll_lck_i => gn4124_status(0),
carrier_info_stat_sys_pll_lck_i => pll_status,
carrier_info_stat_sys_pll_lck_i => '0',
carrier_info_stat_ddr3_cal_done_i => '0',
carrier_info_stat_reserved_i => (others => '0'),
carrier_info_ctrl_led_green_o => open,
......
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