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MasterFIP - Gateware
Commit bc4cc976 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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added counter of ext_sync_p

parent aae395c5
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rtl/fmc_masterFIP_core.vhd
View file @ bc4cc976
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rtl/fmc_masterfip_csr.vhd
View file @ bc4cc976
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd -- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb -- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 10/21/15 17:14:44 -- Created : 10/27/15 14:50:00
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
...@@ -48,6 +48,10 @@ entity fmc_masterfip_csr is ...@@ -48,6 +48,10 @@ entity fmc_masterfip_csr is
mf_ext_sync_oe_o : out std_logic; mf_ext_sync_oe_o : out std_logic;
-- Port for BIT field: 'test pulse' in reg: 'ext sync' -- Port for BIT field: 'test pulse' in reg: 'ext sync'
mf_ext_sync_tst_n_o : out std_logic; mf_ext_sync_tst_n_o : out std_logic;
-- Port for BIT field: 'pulses counter reset' in reg: 'ext sync'
mf_ext_sync_p_cnt_rst_o : out std_logic;
-- Port for std_logic_vector field: 'ext_sync_p_cnt' in reg: 'ext sync pulses cnt'
mf_ext_sync_p_cnt_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: '150ohms terination of the bus' in reg: '150ohms bus termination' -- Port for BIT field: '150ohms terination of the bus' in reg: '150ohms bus termination'
mf_bus_term_en_n_o : out std_logic; mf_bus_term_en_n_o : out std_logic;
-- Port for std_logic_vector field: 'speed' in reg: 'speed' -- Port for std_logic_vector field: 'speed' in reg: 'speed'
...@@ -70,8 +74,6 @@ entity fmc_masterfip_csr is ...@@ -70,8 +74,6 @@ entity fmc_masterfip_csr is
mf_turnar_time_cnt_i : in std_logic_vector(30 downto 0); mf_turnar_time_cnt_i : in std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'silence time counter' in reg: 'silence time cnt' -- Port for std_logic_vector field: 'silence time counter' in reg: 'silence time cnt'
mf_silen_time_cnt_i : in std_logic_vector(30 downto 0); mf_silen_time_cnt_i : in std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'ext_sync_tstamp' in reg: 'ext sync tstamp'
mf_ext_sync_tstamp_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'tx rst' in reg: 'tx ctrl' -- Port for BIT field: 'tx rst' in reg: 'tx ctrl'
mf_tx_ctrl_rst_o : out std_logic; mf_tx_ctrl_rst_o : out std_logic;
-- Port for BIT field: 'tx strt' in reg: 'tx ctrl' -- Port for BIT field: 'tx strt' in reg: 'tx ctrl'
...@@ -382,6 +384,7 @@ signal mf_ext_sync_term_en_int : std_logic ; ...@@ -382,6 +384,7 @@ signal mf_ext_sync_term_en_int : std_logic ;
signal mf_ext_sync_dir_int : std_logic ; signal mf_ext_sync_dir_int : std_logic ;
signal mf_ext_sync_oe_int : std_logic ; signal mf_ext_sync_oe_int : std_logic ;
signal mf_ext_sync_tst_n_int : std_logic ; signal mf_ext_sync_tst_n_int : std_logic ;
signal mf_ext_sync_p_cnt_rst_int : std_logic ;
signal mf_bus_term_en_n_int : std_logic ; signal mf_bus_term_en_n_int : std_logic ;
signal mf_macrocyc_lgth_int : std_logic_vector(30 downto 0); signal mf_macrocyc_lgth_int : std_logic_vector(30 downto 0);
signal mf_macrocyc_start_int : std_logic ; signal mf_macrocyc_start_int : std_logic ;
...@@ -497,6 +500,7 @@ begin ...@@ -497,6 +500,7 @@ begin
mf_ext_sync_dir_int <= '0'; mf_ext_sync_dir_int <= '0';
mf_ext_sync_oe_int <= '0'; mf_ext_sync_oe_int <= '0';
mf_ext_sync_tst_n_int <= '0'; mf_ext_sync_tst_n_int <= '0';
mf_ext_sync_p_cnt_rst_int <= '0';
mf_bus_term_en_n_int <= '0'; mf_bus_term_en_n_int <= '0';
mf_macrocyc_lgth_int <= "0000000000000000000000000000000"; mf_macrocyc_lgth_int <= "0000000000000000000000000000000";
mf_macrocyc_start_int <= '0'; mf_macrocyc_start_int <= '0';
...@@ -681,16 +685,17 @@ begin ...@@ -681,16 +685,17 @@ begin
mf_ext_sync_dir_int <= wrdata_reg(1); mf_ext_sync_dir_int <= wrdata_reg(1);
mf_ext_sync_oe_int <= wrdata_reg(2); mf_ext_sync_oe_int <= wrdata_reg(2);
mf_ext_sync_tst_n_int <= wrdata_reg(3); mf_ext_sync_tst_n_int <= wrdata_reg(3);
mf_ext_sync_p_cnt_rst_int <= wrdata_reg(8);
end if; end if;
rddata_reg(0) <= mf_ext_sync_term_en_int; rddata_reg(0) <= mf_ext_sync_term_en_int;
rddata_reg(1) <= mf_ext_sync_dir_int; rddata_reg(1) <= mf_ext_sync_dir_int;
rddata_reg(2) <= mf_ext_sync_oe_int; rddata_reg(2) <= mf_ext_sync_oe_int;
rddata_reg(3) <= mf_ext_sync_tst_n_int; rddata_reg(3) <= mf_ext_sync_tst_n_int;
rddata_reg(8) <= mf_ext_sync_p_cnt_rst_int;
rddata_reg(4) <= 'X'; rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X'; rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X'; rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X'; rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X'; rddata_reg(11) <= 'X';
...@@ -717,6 +722,12 @@ begin ...@@ -717,6 +722,12 @@ begin
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00000100" => when "00000100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_ext_sync_p_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
mf_bus_term_en_n_int <= wrdata_reg(0); mf_bus_term_en_n_int <= wrdata_reg(0);
end if; end if;
...@@ -754,7 +765,7 @@ begin ...@@ -754,7 +765,7 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00000101" => when "00000110" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(1 downto 0) <= mf_speed_i; rddata_reg(1 downto 0) <= mf_speed_i;
...@@ -790,7 +801,7 @@ begin ...@@ -790,7 +801,7 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00000110" => when "00000111" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
mf_macrocyc_lgth_int <= wrdata_reg(30 downto 0); mf_macrocyc_lgth_int <= wrdata_reg(30 downto 0);
mf_macrocyc_start_int <= wrdata_reg(31); mf_macrocyc_start_int <= wrdata_reg(31);
...@@ -799,7 +810,7 @@ begin ...@@ -799,7 +810,7 @@ begin
rddata_reg(31) <= mf_macrocyc_start_int; rddata_reg(31) <= mf_macrocyc_start_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00000111" => when "00001000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
mf_turnar_lgth_int <= wrdata_reg(30 downto 0); mf_turnar_lgth_int <= wrdata_reg(30 downto 0);
mf_turnar_start_int <= wrdata_reg(31); mf_turnar_start_int <= wrdata_reg(31);
...@@ -808,7 +819,7 @@ begin ...@@ -808,7 +819,7 @@ begin
rddata_reg(31) <= mf_turnar_start_int; rddata_reg(31) <= mf_turnar_start_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001000" => when "00001001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
mf_silen_lgth_int <= wrdata_reg(30 downto 0); mf_silen_lgth_int <= wrdata_reg(30 downto 0);
mf_silen_start_int <= wrdata_reg(31); mf_silen_start_int <= wrdata_reg(31);
...@@ -817,33 +828,27 @@ begin ...@@ -817,33 +828,27 @@ begin
rddata_reg(31) <= mf_silen_start_int; rddata_reg(31) <= mf_silen_start_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001001" => when "00001010" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(30 downto 0) <= mf_macrocyc_time_cnt_i; rddata_reg(30 downto 0) <= mf_macrocyc_time_cnt_i;
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001010" => when "00001011" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(30 downto 0) <= mf_turnar_time_cnt_i; rddata_reg(30 downto 0) <= mf_turnar_time_cnt_i;
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001011" => when "00001100" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(30 downto 0) <= mf_silen_time_cnt_i; rddata_reg(30 downto 0) <= mf_silen_time_cnt_i;
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_ext_sync_tstamp_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001101" => when "00001101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
mf_tx_ctrl_rst_int <= wrdata_reg(0); mf_tx_ctrl_rst_int <= wrdata_reg(0);
...@@ -1960,6 +1965,9 @@ begin ...@@ -1960,6 +1965,9 @@ begin
mf_ext_sync_oe_o <= mf_ext_sync_oe_int; mf_ext_sync_oe_o <= mf_ext_sync_oe_int;
-- test pulse -- test pulse
mf_ext_sync_tst_n_o <= mf_ext_sync_tst_n_int; mf_ext_sync_tst_n_o <= mf_ext_sync_tst_n_int;
-- pulses counter reset
mf_ext_sync_p_cnt_rst_o <= mf_ext_sync_p_cnt_rst_int;
-- ext_sync_p_cnt
-- 150ohms terination of the bus -- 150ohms terination of the bus
mf_bus_term_en_n_o <= mf_bus_term_en_n_int; mf_bus_term_en_n_o <= mf_bus_term_en_n_int;
-- speed -- speed
...@@ -1978,7 +1986,6 @@ begin ...@@ -1978,7 +1986,6 @@ begin
-- macrocycle time counter -- macrocycle time counter
-- turnaround time counter -- turnaround time counter
-- silence time counter -- silence time counter
-- ext_sync_tstamp
-- tx rst -- tx rst
mf_tx_ctrl_rst_o <= mf_tx_ctrl_rst_int; mf_tx_ctrl_rst_o <= mf_tx_ctrl_rst_int;
-- tx strt -- tx strt
......
rtl/masterFIP_pkg.vhd
View file @ bc4cc976
...@@ -202,7 +202,8 @@ package masterFIP_pkg is ...@@ -202,7 +202,8 @@ package masterFIP_pkg is
mf_ext_sync_dir_o : out std_logic; mf_ext_sync_dir_o : out std_logic;
mf_ext_sync_oe_o : out std_logic; mf_ext_sync_oe_o : out std_logic;
mf_ext_sync_tst_n_o : out std_logic; mf_ext_sync_tst_n_o : out std_logic;
mf_ext_sync_tstamp_i : in std_logic_vector(31 downto 0); mf_ext_sync_p_cnt_rst_o : out std_logic;
mf_ext_sync_p_cnt_i : in std_logic_vector(31 downto 0);
mf_bus_term_en_n_o : out std_logic; mf_bus_term_en_n_o : out std_logic;
mf_speed_i : in std_logic_vector(1 downto 0); mf_speed_i : in std_logic_vector(1 downto 0);
...@@ -498,19 +499,34 @@ package masterFIP_pkg is ...@@ -498,19 +499,34 @@ package masterFIP_pkg is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
component decr_counter component decr_counter
generic generic
(width : integer := 32); (width : integer := 32);
port port
(clk_i : in std_logic; (clk_i : in std_logic;
rst_i : in std_logic; rst_i : in std_logic;
counter_load_i : in std_logic; counter_load_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0); counter_top_i : in std_logic_vector(width-1 downto 0);
------------------------------------------------------------- -------------------------------------------------------------
counter_is_zero_o : out std_logic; counter_is_zero_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0)); counter_o : out std_logic_vector(width-1 downto 0));
------------------------------------------------------------- -------------------------------------------------------------
end component; end component;
---------------------------------------------------------------------------------------------------
component incr_counter is
generic
(g_counter_lgth : natural := 4);
port
(clk_i : in std_logic;
counter_incr_i : in std_logic;
counter_reinit_i : in std_logic;
-------------------------------------------------------------
counter_o : out std_logic_vector (g_counter_lgth-1 downto 0);
counter_is_full_o : out std_logic);
end component incr_counter;
-------------------------------------------------------------
end masterFIP_pkg; end masterFIP_pkg;
--================================================================================================= --=================================================================================================
......
rtl/masterfip_rx.vhd
View file @ bc4cc976
...@@ -153,7 +153,7 @@ architecture struc of masterfip_rx is ...@@ -153,7 +153,7 @@ architecture struc of masterfip_rx is
-- retreived bytes into 32-bit regs -- retreived bytes into 32-bit regs
signal byte0, byte1, byte2, byte3 : std_logic_vector(7 downto 0) := (others => '0'); signal byte0, byte1, byte2, byte3 : std_logic_vector(7 downto 0) := (others => '0');
signal word32 : std_logic_vector(31 downto 0); signal word32 : std_logic_vector(31 downto 0);
signal word32_num : integer range 0 to 31; signal word32_num : integer range 0 to 65;
-- bytes counter -- bytes counter
signal rx_byte_index, rx_byte_index_d1 : unsigned(8 downto 0) := (others => '0'); signal rx_byte_index, rx_byte_index_d1 : unsigned(8 downto 0) := (others => '0');
signal bytes_c_rst : std_logic; signal bytes_c_rst : std_logic;
......
rtl/masterfip_tx.vhd
View file @ bc4cc976
...@@ -137,7 +137,7 @@ architecture struc of masterfip_tx is ...@@ -137,7 +137,7 @@ architecture struc of masterfip_tx is
signal prod_bytes_c : unsigned(8 downto 0); signal prod_bytes_c : unsigned(8 downto 0);
signal ctrl_byte, tx_byte : std_logic_vector(7 downto 0); signal ctrl_byte, tx_byte : std_logic_vector(7 downto 0);
signal prod_frame : tx_frame_t; signal prod_frame : tx_frame_t;
signal word32_num : integer range 0 to 31; signal word32_num : integer range 0 to 65;
signal word32 : std_logic_vector(31 downto 0); signal word32 : std_logic_vector(31 downto 0);
-- bytes counter -- bytes counter
signal bytes_num : std_logic_vector(8 downto 0); signal bytes_num : std_logic_vector(8 downto 0);
......
rtl/wbgen/fmc_masterfip_csr.wb
View file @ bc4cc976
...@@ -146,9 +146,33 @@ peripheral { ...@@ -146,9 +146,33 @@ peripheral {
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field {
name = "pulses counter reset";
prefix = "p_cnt_rst";
description = "resets the pulses counter";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
}; };
reg {
name = "ext sync pulses cnt";
prefix = "ext_sync_p_cnt";
field {
name = "ext_sync_p_cnt";
description = "number of ext sync pulses";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- bus termination -- -- bus termination --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -301,21 +325,7 @@ peripheral { ...@@ -301,21 +325,7 @@ peripheral {
}; };
}; };
reg {
name = "ext sync tstamp";
prefix = "ext_sync_tstamp";
field {
name = "ext_sync_tstamp";
description = "timestamp of the last external sync pulse received";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- serializer ctrl -- -- serializer ctrl --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
......
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