Skip to content

M
MasterFIP - Gateware
Commit d30c6031 authored by Evangelia Gousiou's avatar Evangelia Gousiou
Browse files
Options

- corrected relays control(0: relay ON; Z: relay OFF instead of 0: relay ON; 1: relay OFF) 

- general code cleanup
parent 6921cd9e
Hide whitespace changes
Inline Side-by-side
Showing with 961 additions and 794 deletions
rtl/fmc_masterFIP_core.vhd
View file @ d30c6031
......@@ -12,7 +12,84 @@
---------------------------------------------------------------------------------------------------
-- File fmc_masterFIP_core.vhd |
-- |
-- Description The masterFIP core top level instantiates all the modules needed to provide
-- Description The masterFIP_core instantiates all the modules needed to establish WorldFIP |
-- communication. Figure 1 shows the modules of the core. |
-- |
-- _ ________________________________________________________________ |
-- | | | fmc_masterFIP_core | |
-- |W| | _________________ ____________ ____________ ______ | |
-- |O| | | | | macrocycle | | silence | | | | |
-- |R| <--| | masterfip_tx | | time cnt | | time cnt | | | | |
-- |L| | _________________| |____________| |____________| | | | |
-- |D| | _________________ ____________ ____________ | fmc | | |
-- |F| -->| | | | turnaround | | | |master| | <-processor-> |
-- |I| | | masterfip_rx | | time cnt | | resets | | FIP | | |
-- |P| | |_________________| |____________| |____________| | csr | | |
-- |_| | | | | |
-- | _________________ | | | |
-- sync pulse -->| | ext sync pulse | | | | |
-- | |_________________| | | | |
-- | _______ | | | |
-- LEDs <--| | aux | | | | |
-- | |_______| |______| | |
-- |________________________________________________________________| |
-- Figure 1 |
-- |
-- The fmc_masterfip_csr module establishes the interface with the processor, usually|
-- a Mock Turtle core. The module has been generated through the wbgen2 application. |
-- Please consult the fmc_masterfip_csr.htm for the registers map. |
-- |
-- The masterfip_tx is placing a complete WorldFIP frame on the bus. |
-- The masterfip_tx is ignorant of the frame type (ID_DAT/RT_DAT/RP_MSG etc..) or the|
-- macrocycle sequence, as well as of timing issues (it does not for example measure |
-- internally the turnaround time after the delivery of an ID_DAT); the processor |
-- (Mock Turtle for example) is responsible for managing all these issues and |
-- for providing to the masterfip_tx (through the fmc_masterfip_csr) the data to |
-- serialise and a start pulse. The communication between the processor (MT) and the |
-- masterfip_tx is through a set of control (from the MT) and status (from the |
-- masterfip_tx) registers. Upon a rising edge on the tx_start control pulse, the |
-- masterfip_tx is copying all the data registers (tx_data_ctrl, |
-- tx_data_reg1..tx_data_reg66) and then it initiates a WorldFIP frame, starting with|
-- the FSS, the tx_data_ctrl and then the number of data bytes indicated by the |
-- tx_bytes_num register; it finally adds the CRC and FES and signals the processor |
-- through the status bit tx_stop. |
-- ______________________________________________________________________________ |
-- |_____FSS_____|__Ctrl__|_____________tx_data______________|_____CRC____|__FES__| |
-- |
-- <-- 2 byes --><-1byte-><--------- tx_bytes_num --------><-- 2 byes --><-1byte-> |
-- |
-- The masterfip_rx is retrieving a WorldFIP frame from the bus. |
-- Similar to the masterfip_tx, the masterfip_rx has no intelligence regarding the |
-- macrocycle sequence; it is controlled and monitored by the processor through the |
-- fmc_masterfip_csr and a set of control and status registers. |
-- As long as it is not under reset, the masterfip_rx is looking at the WorldFIP bus |
-- trying to identify the FSS sequence of a WorldFIP frame. Upon the FSS detection |
-- it signals the processor (MT) through the status bit fss_received and continues |
-- with following the rest of the frame. It stores the first byte after the FSS to |
-- the rx_data_ctrl register and the rest of the bytes to the registers |
-- rx_data_reg1..rx_data_reg66. Upon the detection of a FES the masterfip_rx is |
-- checking the CRC of the frame and enables the status bit rx_frame_ok or |
-- rx_frame_error accordingly. Upon the rx_frame_ok, the status register |
-- rx_bytes_num indicates the number of bytes that were in the frame (this indicates |
-- the number of rx_data_regs and the number of bytes inside the last rx_data_reg to |
-- be retrieved by the processor). |
-- ______________________________________________________________________________ |
-- |_____FSS_____|__Ctrl__|_____________rx_data______________|_____CRC____|__FES__| |
-- |
-- <-- 2 byes --><-1byte-><--------- rx_bytes_num --------><-- 2 byes --><-1byte-> |
-- |
-- The modules regarding the ext_sync_pulse are counting the number of rising-edge |
-- pulses that are arriving to the ext_sync input of the board and provide the result|
-- to the dedicated fmc_masterfip_csr register to be accessed by the processor (MT). |
-- |
-- The modules regarding the macrocycle are counting the time of a macrocycle using |
-- the 10ns input clock as well as the number of macrocycles since the |
-- startup/a reset. Dedicated registers in the fmc_masterfip_csr provide the counters|
-- values to the processor. |
-- |
-- The modules regarding the turnaround and silence time are counting the respective |
-- time using the 10ns clock. Dedicated registers in the fmc_masterfip_csr provide |
-- the counters values to the processor. |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 07/2014 |
......@@ -70,21 +147,21 @@ entity fmc_masterFIP_core is
-- 5 Mbps : speed_b1 = 1, speed_b0 = 1
-- Bus termination
bus_term_en_n_o : out std_logic; -- 150 Ohms termination of the bus -- check again
-- External synchronisation pulse transceiver
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enable 50 Ohms termination of the pulse
ext_sync_dir_o : out std_logic; -- transceiver direction
ext_sync_dir_o : out std_logic; -- transceiver direction
ext_sync_oe_o : out std_logic; -- transceiver output enable
ext_sync_tst_n_o : out std_logic; -- emulation of the LEMO input
ext_sync_i : in std_logic; -- sync pulse
-- Power supplies for the ADC
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
adc_prim_conn_n_o : out std_logic;
adc_sec_conn_n_o : out std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic;
......@@ -130,12 +207,14 @@ architecture rtl of fmc_masterFIP_core is
signal ext_sync_p_cnt : std_logic_vector(31 downto 0);
-- counters
signal macrocyc_load_p, turnar_load_p, silen_load_p : std_logic;
signal num_of_macrocyc_cnt : std_logic_vector(31 downto 0);
signal num_of_macrocyc_cnt_full, num_of_macrocyc_cnt_reinit : std_logic;
signal macrocyc_lgth, turnar_lgth, silen_lgth : std_logic_vector(30 downto 0);
signal macrocyc_host_load, turnar_host_load, silen_host_load : std_logic;
signal macrocyc_host_load_p, turnar_host_load_p : std_logic;
signal silen_host_load_p : std_logic;
signal macrocyc_cnt, turnar_cnt, silen_cnt : std_logic_vector(30 downto 0);
signal macrocyc_cnt_zero_p : std_logic;
signal macrocyc_cnt_zero_p : std_logic;
-- tx
signal tx_completed_p, tx_completed, tx_start, tx_start_p : std_logic;
signal tx_rst, tx_host_rst, tx_host_rst_p, fd_txd, fd_txck : std_logic;
......@@ -150,9 +229,16 @@ architecture rtl of fmc_masterFIP_core is
signal rx_frame : rx_frame_t;
signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0);
signal rx_byte_index, rx_bytes_num : std_logic_vector(8 downto 0); -- up to 263 bytes
-- ADC
signal adc_sec_conn_n, adc_prim_conn_n : std_logic;
-- ext_sync
signal ext_sync_tst_n : std_logic;
-- LEDs
signal sync_led, out_of_sync_led : std_logic;
-- debug
signal mf_dbg : std_logic_vector(31 downto 0);
signal mf_dbg_p, mf_dbg_p_ext : std_logic;
-- chipscope
-- component chipscope_ila
-- port (
......@@ -173,7 +259,7 @@ architecture rtl of fmc_masterFIP_core is
-- signal TRIG2 : std_logic_vector(31 downto 0);
-- signal TRIG3 : std_logic_vector(31 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -185,212 +271,219 @@ begin
cmp_masterfip_csr: fmc_masterfip_csr
port map
-- wishbone
(rst_n_i => rst_n,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i(9 downto 2),
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => wb_stall_o,
(rst_n_i => rst_n,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i(9 downto 2),
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => wb_stall_o,
-- resets
mf_rstn_core_o => core_rstn_tmp, -- reset has to be confirmed with lock word mf_rstn_lock_o
mf_rstn_fd_o => fd_rstn_tmp, -- reset has to be confirmed with lock word mf_rstn_lock_o
mf_rstn_lock_o => rstn_lock,
mf_rstn_lock_wr_o => rstn_lock_wr,
mf_rstn_core_o => core_rstn_tmp, -- reset has to be confirmed with lock word mf_rstn_lock_o
mf_rstn_fd_o => fd_rstn_tmp, -- reset has to be confirmed with lock word mf_rstn_lock_o
mf_rstn_lock_o => rstn_lock,
mf_rstn_lock_wr_o => rstn_lock_wr,
--dbg
mf_dbg_o => mf_dbg,
-- adc supplies
mf_adc_1v8_shdn_n_o => adc_1v8_shdn_n_o,
mf_adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
mf_adc_5v_en_n_o => adc_5v_en_n_o,
mf_adc_prim_conn_n_o => adc_prim_conn_n_o,
mf_adc_sec_conn_n_o => adc_sec_conn_n_o,
mf_adc_1v8_shdn_n_o => adc_1v8_shdn_n_o,
mf_adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
mf_adc_5v_en_n_o => adc_5v_en_n_o,
mf_adc_prim_conn_n_o => adc_prim_conn_n,
mf_adc_sec_conn_n_o => adc_sec_conn_n,
-- external sync pulse
mf_ext_sync_term_en_o => ext_sync_term_en_o,
mf_ext_sync_dir_o => ext_sync_dir_o,
mf_ext_sync_oe_o => ext_sync_oe,
mf_ext_sync_tst_n_o => ext_sync_tst_n_o,
mf_ext_sync_p_cnt_rst_o => ext_sync_p_cnt_host_rst,
mf_ext_sync_p_cnt_i => ext_sync_p_cnt,
mf_ext_sync_term_en_o => ext_sync_term_en_o,
mf_ext_sync_dir_o => ext_sync_dir_o,
mf_ext_sync_oe_o => ext_sync_oe,
mf_ext_sync_tst_n_o => ext_sync_tst_n,
mf_ext_sync_p_cnt_rst_o => ext_sync_p_cnt_host_rst,
mf_ext_sync_p_cnt_i => ext_sync_p_cnt,
-- bus termination
mf_bus_term_en_n_o => bus_term_en_n_o,
mf_bus_term_en_n_o => bus_term_en_n_o,
-- bus speed
mf_speed_i(1) => speed_b1_i,
mf_speed_i(0) => speed_b0_i,
mf_speed_i(1) => speed_b1_i,
mf_speed_i(0) => speed_b0_i,
-- counters outputs
mf_macrocyc_lgth_o => macrocyc_lgth,
mf_turnar_lgth_o => turnar_lgth,
mf_silen_lgth_o => silen_lgth,
mf_macrocyc_start_o => macrocyc_host_load, -- optional counters loading through the host
mf_turnar_start_o => turnar_host_load,
mf_silen_start_o => silen_host_load,
-- counters inputs
mf_macrocyc_time_cnt_i => macrocyc_cnt,
mf_turnar_time_cnt_i => turnar_cnt,
mf_silen_time_cnt_i => silen_cnt,
mf_macrocyc_lgth_o => macrocyc_lgth,
mf_macrocyc_num_cnt_i => num_of_macrocyc_cnt,
mf_turnar_lgth_o => turnar_lgth,
mf_silen_lgth_o => silen_lgth,
mf_macrocyc_start_o => macrocyc_host_load, -- optional counters loading through the host
mf_turnar_start_o => turnar_host_load,
mf_silen_start_o => silen_host_load,
-- counters inputs
mf_macrocyc_time_cnt_i => macrocyc_cnt,
mf_turnar_time_cnt_i => turnar_cnt,
mf_silen_time_cnt_i => silen_cnt,
-- tx control
mf_tx_ctrl_rst_o => tx_host_rst, -- tx rst; then converted to 1-tick-long pulse
mf_tx_ctrl_start_o => tx_start, -- tx start serializing a frame; then converted to 1-tick-long pulse
mf_tx_ctrl_bytes_num_o => tx_bytes_num, -- number of bytes to serialize; sampled upon tx_start
mf_tx_ctrl_rst_o => tx_host_rst, -- tx rst; then converted to 1-tick-long pulse
mf_tx_ctrl_start_o => tx_start, -- tx start serializing a frame; then converted to 1-tick-long pulse
mf_tx_ctrl_bytes_num_o => tx_bytes_num, -- number of bytes to serialize; sampled upon tx_start
-- tx status
mf_tx_stat_stop_i => tx_completed, -- 16x25ns long pulse upon the end of delivery of a frame
mf_tx_stat_byte_index_i => tx_byte_index, -- index of current byte being serialized
mf_tx_stat_ena_i => fd_txena, -- FIELDRIVE txena, signal generated by the tx_serializer
mf_fd_wdgn_i => fd_wdgn_i, -- FIELDRIVE watchdog, signal comes from the FIELDRIVE
mf_fd_txer_i => fd_txer_i, -- FIELDRIVE txerr, signal comes from the FIELDRIVE
mf_tx_stat_stop_i => tx_completed, -- 16x25ns long pulse upon the end of delivery of a frame
mf_tx_stat_byte_index_i => tx_byte_index, -- index of current byte being serialized
mf_tx_stat_ena_i => fd_txena, -- FIELDRIVE txena, signal generated by the tx_serializer
mf_fd_wdgn_i => fd_wdgn_i, -- FIELDRIVE watchdog, signal comes from the FIELDRIVE
mf_fd_txer_i => fd_txer_i, -- FIELDRIVE txerr, signal comes from the FIELDRIVE
-- rx control/status
mf_rx_ctrl_rst_o => rx_host_rst, -- note: this is not a pulse
mf_rx_ctrl_rst_o => rx_host_rst, -- note: this is not a pulse
-- rx status
mf_rx_stat_pream_ok_i => rx_fss_received,
mf_rx_stat_frame_ok_i => rx_frame_ok,
mf_rx_stat_frame_err_i => rx_crc_wrong,
mf_rx_stat_frame_err_code_i => "000",
mf_rx_stat_bytes_num_i => rx_bytes_num,
mf_rx_stat_pream_ok_i => rx_fss_received,
mf_rx_stat_frame_ok_i => rx_frame_ok,
mf_rx_stat_frame_err_i => rx_crc_wrong,
mf_rx_stat_frame_err_code_i => "000",
mf_rx_stat_bytes_num_i => rx_bytes_num,
-- rx data
mf_rx_data_ctrl_i => rx_ctrl_byte,
mf_rx_data_reg1_i => rx_frame(0),
mf_rx_data_reg2_i => rx_frame(1),
mf_rx_data_reg3_i => rx_frame(2),
mf_rx_data_reg4_i => rx_frame(3),
mf_rx_data_reg5_i => rx_frame(4),
mf_rx_data_reg6_i => rx_frame(5),
mf_rx_data_reg7_i => rx_frame(6),
mf_rx_data_reg8_i => rx_frame(7),
mf_rx_data_reg9_i => rx_frame(8),
mf_rx_data_reg10_i => rx_frame(9),
mf_rx_data_reg11_i => rx_frame(10),
mf_rx_data_reg12_i => rx_frame(11),
mf_rx_data_reg13_i => rx_frame(12),
mf_rx_data_reg14_i => rx_frame(13),
mf_rx_data_reg15_i => rx_frame(14),
mf_rx_data_reg16_i => rx_frame(15),
mf_rx_data_reg17_i => rx_frame(16),
mf_rx_data_reg18_i => rx_frame(17),
mf_rx_data_reg19_i => rx_frame(18),
mf_rx_data_reg20_i => rx_frame(19),
mf_rx_data_reg21_i => rx_frame(20),
mf_rx_data_reg22_i => rx_frame(21),
mf_rx_data_reg23_i => rx_frame(22),
mf_rx_data_reg24_i => rx_frame(23),
mf_rx_data_reg25_i => rx_frame(24),
mf_rx_data_reg26_i => rx_frame(25),
mf_rx_data_reg27_i => rx_frame(26),
mf_rx_data_reg28_i => rx_frame(27),
mf_rx_data_reg29_i => rx_frame(28),
mf_rx_data_reg30_i => rx_frame(29),
mf_rx_data_reg31_i => rx_frame(30),
mf_rx_data_reg32_i => rx_frame(31),
mf_rx_data_reg33_i => rx_frame(32),
mf_rx_data_reg34_i => rx_frame(33),
mf_rx_data_reg35_i => rx_frame(34),
mf_rx_data_reg36_i => rx_frame(35),
mf_rx_data_reg37_i => rx_frame(36),
mf_rx_data_reg38_i => rx_frame(37),
mf_rx_data_reg39_i => rx_frame(38),
mf_rx_data_reg40_i => rx_frame(39),
mf_rx_data_reg41_i => rx_frame(40),
mf_rx_data_reg42_i => rx_frame(41),
mf_rx_data_reg43_i => rx_frame(42),
mf_rx_data_reg44_i => rx_frame(43),
mf_rx_data_reg45_i => rx_frame(44),
mf_rx_data_reg46_i => rx_frame(45),
mf_rx_data_reg47_i => rx_frame(46),
mf_rx_data_reg48_i => rx_frame(47),
mf_rx_data_reg49_i => rx_frame(48),
mf_rx_data_reg50_i => rx_frame(49),
mf_rx_data_reg51_i => rx_frame(50),
mf_rx_data_reg52_i => rx_frame(51),
mf_rx_data_reg53_i => rx_frame(52),
mf_rx_data_reg54_i => rx_frame(53),
mf_rx_data_reg55_i => rx_frame(54),
mf_rx_data_reg56_i => rx_frame(55),
mf_rx_data_reg57_i => rx_frame(56),
mf_rx_data_reg58_i => rx_frame(57),
mf_rx_data_reg59_i => rx_frame(58),
mf_rx_data_reg60_i => rx_frame(59),
mf_rx_data_reg61_i => rx_frame(60),
mf_rx_data_reg62_i => rx_frame(61),
mf_rx_data_reg63_i => rx_frame(62),
mf_rx_data_reg64_i => rx_frame(63),
mf_rx_data_reg65_i => rx_frame(64),
mf_rx_data_reg66_i => rx_frame(65),
mf_rx_data_ctrl_i => rx_ctrl_byte,
mf_rx_data_reg1_i => rx_frame(0),
mf_rx_data_reg2_i => rx_frame(1),
mf_rx_data_reg3_i => rx_frame(2),
mf_rx_data_reg4_i => rx_frame(3),
mf_rx_data_reg5_i => rx_frame(4),
mf_rx_data_reg6_i => rx_frame(5),
mf_rx_data_reg7_i => rx_frame(6),
mf_rx_data_reg8_i => rx_frame(7),
mf_rx_data_reg9_i => rx_frame(8),
mf_rx_data_reg10_i => rx_frame(9),
mf_rx_data_reg11_i => rx_frame(10),
mf_rx_data_reg12_i => rx_frame(11),
mf_rx_data_reg13_i => rx_frame(12),
mf_rx_data_reg14_i => rx_frame(13),
mf_rx_data_reg15_i => rx_frame(14),
mf_rx_data_reg16_i => rx_frame(15),
mf_rx_data_reg17_i => rx_frame(16),
mf_rx_data_reg18_i => rx_frame(17),
mf_rx_data_reg19_i => rx_frame(18),
mf_rx_data_reg20_i => rx_frame(19),
mf_rx_data_reg21_i => rx_frame(20),
mf_rx_data_reg22_i => rx_frame(21),
mf_rx_data_reg23_i => rx_frame(22),
mf_rx_data_reg24_i => rx_frame(23),
mf_rx_data_reg25_i => rx_frame(24),
mf_rx_data_reg26_i => rx_frame(25),
mf_rx_data_reg27_i => rx_frame(26),
mf_rx_data_reg28_i => rx_frame(27),
mf_rx_data_reg29_i => rx_frame(28),
mf_rx_data_reg30_i => rx_frame(29),
mf_rx_data_reg31_i => rx_frame(30),
mf_rx_data_reg32_i => rx_frame(31),
mf_rx_data_reg33_i => rx_frame(32),
mf_rx_data_reg34_i => rx_frame(33),
mf_rx_data_reg35_i => rx_frame(34),
mf_rx_data_reg36_i => rx_frame(35),
mf_rx_data_reg37_i => rx_frame(36),
mf_rx_data_reg38_i => rx_frame(37),
mf_rx_data_reg39_i => rx_frame(38),
mf_rx_data_reg40_i => rx_frame(39),
mf_rx_data_reg41_i => rx_frame(40),
mf_rx_data_reg42_i => rx_frame(41),
mf_rx_data_reg43_i => rx_frame(42),
mf_rx_data_reg44_i => rx_frame(43),
mf_rx_data_reg45_i => rx_frame(44),
mf_rx_data_reg46_i => rx_frame(45),
mf_rx_data_reg47_i => rx_frame(46),
mf_rx_data_reg48_i => rx_frame(47),
mf_rx_data_reg49_i => rx_frame(48),
mf_rx_data_reg50_i => rx_frame(49),
mf_rx_data_reg51_i => rx_frame(50),
mf_rx_data_reg52_i => rx_frame(51),
mf_rx_data_reg53_i => rx_frame(52),
mf_rx_data_reg54_i => rx_frame(53),
mf_rx_data_reg55_i => rx_frame(54),
mf_rx_data_reg56_i => rx_frame(55),
mf_rx_data_reg57_i => rx_frame(56),
mf_rx_data_reg58_i => rx_frame(57),
mf_rx_data_reg59_i => rx_frame(58),
mf_rx_data_reg60_i => rx_frame(59),
mf_rx_data_reg61_i => rx_frame(60),
mf_rx_data_reg62_i => rx_frame(61),
mf_rx_data_reg63_i => rx_frame(62),
mf_rx_data_reg64_i => rx_frame(63),
mf_rx_data_reg65_i => rx_frame(64),
mf_rx_data_reg66_i => rx_frame(65),
-- tx data
mf_tx_data_ctrl_o => tx_ctrl_byte,
mf_tx_data_reg1_o => tx_frame(0),
mf_tx_data_reg2_o => tx_frame(1),
mf_tx_data_reg3_o => tx_frame(2),
mf_tx_data_reg4_o => tx_frame(3),
mf_tx_data_reg5_o => tx_frame(4),
mf_tx_data_reg6_o => tx_frame(5),
mf_tx_data_reg7_o => tx_frame(6),
mf_tx_data_reg8_o => tx_frame(7),
mf_tx_data_reg9_o => tx_frame(8),
mf_tx_data_reg10_o => tx_frame(9),
mf_tx_data_reg11_o => tx_frame(10),
mf_tx_data_reg12_o => tx_frame(11),
mf_tx_data_reg13_o => tx_frame(12),
mf_tx_data_reg14_o => tx_frame(13),
mf_tx_data_reg15_o => tx_frame(14),
mf_tx_data_reg16_o => tx_frame(15),
mf_tx_data_reg17_o => tx_frame(16),
mf_tx_data_reg18_o => tx_frame(17),
mf_tx_data_reg19_o => tx_frame(18),
mf_tx_data_reg20_o => tx_frame(19),
mf_tx_data_reg21_o => tx_frame(20),
mf_tx_data_reg22_o => tx_frame(21),
mf_tx_data_reg23_o => tx_frame(22),
mf_tx_data_reg24_o => tx_frame(23),
mf_tx_data_reg25_o => tx_frame(24),
mf_tx_data_reg26_o => tx_frame(25),
mf_tx_data_reg27_o => tx_frame(26),
mf_tx_data_reg28_o => tx_frame(27),
mf_tx_data_reg29_o => tx_frame(28),
mf_tx_data_reg30_o => tx_frame(29),
mf_tx_data_reg31_o => tx_frame(30),
mf_tx_data_reg32_o => tx_frame(31),
mf_tx_data_reg33_o => tx_frame(32),
mf_tx_data_reg34_o => tx_frame(33),
mf_tx_data_reg35_o => tx_frame(34),
mf_tx_data_reg36_o => tx_frame(35),
mf_tx_data_reg37_o => tx_frame(36),
mf_tx_data_reg38_o => tx_frame(37),
mf_tx_data_reg39_o => tx_frame(38),
mf_tx_data_reg40_o => tx_frame(39),
mf_tx_data_reg41_o => tx_frame(40),
mf_tx_data_reg42_o => tx_frame(41),
mf_tx_data_reg43_o => tx_frame(42),
mf_tx_data_reg44_o => tx_frame(43),
mf_tx_data_reg45_o => tx_frame(44),
mf_tx_data_reg46_o => tx_frame(45),
mf_tx_data_reg47_o => tx_frame(46),
mf_tx_data_reg48_o => tx_frame(47),
mf_tx_data_reg49_o => tx_frame(48),
mf_tx_data_reg50_o => tx_frame(49),
mf_tx_data_reg51_o => tx_frame(50),
mf_tx_data_reg52_o => tx_frame(51),
mf_tx_data_reg53_o => tx_frame(52),
mf_tx_data_reg54_o => tx_frame(53),
mf_tx_data_reg55_o => tx_frame(54),
mf_tx_data_reg56_o => tx_frame(55),
mf_tx_data_reg57_o => tx_frame(56),
mf_tx_data_reg58_o => tx_frame(57),
mf_tx_data_reg59_o => tx_frame(58),
mf_tx_data_reg60_o => tx_frame(59),
mf_tx_data_reg61_o => tx_frame(60),
mf_tx_data_reg62_o => tx_frame(61),
mf_tx_data_reg63_o => tx_frame(62),
mf_tx_data_reg64_o => tx_frame(63),
mf_tx_data_reg65_o => tx_frame(64),
mf_tx_data_reg66_o => tx_frame(65));
mf_tx_data_ctrl_o => tx_ctrl_byte,
mf_tx_data_reg1_o => tx_frame(0),
mf_tx_data_reg2_o => tx_frame(1),
mf_tx_data_reg3_o => tx_frame(2),
mf_tx_data_reg4_o => tx_frame(3),
mf_tx_data_reg5_o => tx_frame(4),
mf_tx_data_reg6_o => tx_frame(5),
mf_tx_data_reg7_o => tx_frame(6),
mf_tx_data_reg8_o => tx_frame(7),
mf_tx_data_reg9_o => tx_frame(8),
mf_tx_data_reg10_o => tx_frame(9),
mf_tx_data_reg11_o => tx_frame(10),
mf_tx_data_reg12_o => tx_frame(11),
mf_tx_data_reg13_o => tx_frame(12),
mf_tx_data_reg14_o => tx_frame(13),
mf_tx_data_reg15_o => tx_frame(14),
mf_tx_data_reg16_o => tx_frame(15),
mf_tx_data_reg17_o => tx_frame(16),
mf_tx_data_reg18_o => tx_frame(17),
mf_tx_data_reg19_o => tx_frame(18),
mf_tx_data_reg20_o => tx_frame(19),
mf_tx_data_reg21_o => tx_frame(20),
mf_tx_data_reg22_o => tx_frame(21),
mf_tx_data_reg23_o => tx_frame(22),
mf_tx_data_reg24_o => tx_frame(23),
mf_tx_data_reg25_o => tx_frame(24),
mf_tx_data_reg26_o => tx_frame(25),
mf_tx_data_reg27_o => tx_frame(26),
mf_tx_data_reg28_o => tx_frame(27),
mf_tx_data_reg29_o => tx_frame(28),
mf_tx_data_reg30_o => tx_frame(29),
mf_tx_data_reg31_o => tx_frame(30),
mf_tx_data_reg32_o => tx_frame(31),
mf_tx_data_reg33_o => tx_frame(32),
mf_tx_data_reg34_o => tx_frame(33),
mf_tx_data_reg35_o => tx_frame(34),
mf_tx_data_reg36_o => tx_frame(35),
mf_tx_data_reg37_o => tx_frame(36),
mf_tx_data_reg38_o => tx_frame(37),
mf_tx_data_reg39_o => tx_frame(38),
mf_tx_data_reg40_o => tx_frame(39),
mf_tx_data_reg41_o => tx_frame(40),
mf_tx_data_reg42_o => tx_frame(41),
mf_tx_data_reg43_o => tx_frame(42),
mf_tx_data_reg44_o => tx_frame(43),
mf_tx_data_reg45_o => tx_frame(44),
mf_tx_data_reg46_o => tx_frame(45),
mf_tx_data_reg47_o => tx_frame(46),
mf_tx_data_reg48_o => tx_frame(47),
mf_tx_data_reg49_o => tx_frame(48),
mf_tx_data_reg50_o => tx_frame(49),
mf_tx_data_reg51_o => tx_frame(50),
mf_tx_data_reg52_o => tx_frame(51),
mf_tx_data_reg53_o => tx_frame(52),
mf_tx_data_reg54_o => tx_frame(53),
mf_tx_data_reg55_o => tx_frame(54),
mf_tx_data_reg56_o => tx_frame(55),
mf_tx_data_reg57_o => tx_frame(56),
mf_tx_data_reg58_o => tx_frame(57),
mf_tx_data_reg59_o => tx_frame(58),
mf_tx_data_reg60_o => tx_frame(59),
mf_tx_data_reg61_o => tx_frame(60),
mf_tx_data_reg62_o => tx_frame(61),
mf_tx_data_reg63_o => tx_frame(62),
mf_tx_data_reg64_o => tx_frame(63),
mf_tx_data_reg65_o => tx_frame(64),
mf_tx_data_reg66_o => tx_frame(65));
adc_sec_conn_n_o <= '0' when adc_sec_conn_n = '0' else 'Z';
adc_prim_conn_n_o <= '0' when adc_prim_conn_n = '0' else 'Z';
ext_sync_tst_n_o <= '0' when ext_sync_tst_n= '0' else 'Z';
---------------------------------------------------------------------------------------------------
-- resets --
---------------------------------------------------------------------------------------------------
rst_n <= not rst_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- reset generation
p_host_reset : process(clk_i)
......@@ -415,10 +508,12 @@ begin
core_rst_n <= not core_rst;
---------------------------------------------------------------------------------------------------
-- external sync --
---------------------------------------------------------------------------------------------------
-- TODO: add antiglitch filter; maybe also disable the reception of a new pulse for some time after
-- the previous pulse
-- synchronizer and edge detection
cmp_ext_sync_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
......@@ -435,17 +530,17 @@ begin
(clk_i => clk_i,
counter_incr_i => ext_sync_p,
counter_reinit_i => ext_sync_p_cnt_rst,
counter_o => ext_sync_p_cnt);
counter_o => ext_sync_p_cnt);
-- -- -- -- -- -- -- -- -- -- --
ext_sync_p_cnt_rst <= ext_sync_p_cnt_host_rst or core_rst;
--
--
---------------------------------------------------------------------------------------------------
-- macrocycle counter --
---------------------------------------------------------------------------------------------------
-- macrocycle counter
cmp_macrocycle_cnt: decr_counter
-- counter counting the macrocycle time
cmp_macrocycle_time_cnt: decr_counter
generic map(width => 31)
port map
(clk_i => clk_i,
......@@ -454,7 +549,7 @@ begin
counter_top_i => macrocyc_lgth,
counter_o => macrocyc_cnt,
counter_is_zero_o => macrocyc_cnt_zero_p);
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
macrocyc_load_p <= macrocyc_cnt_zero_p or macrocyc_host_load_p or ext_sync_p;
-- edge detection of the macrocyc_host_load signal
......@@ -487,8 +582,19 @@ begin
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => ext_sync_p,
extended_o => sync_led);
extended_o => sync_led);
-- counter counting the number of macrocycles; when it fills up it restarts
cmp_macrocycles_cnt:incr_counter
generic map(g_counter_lgth => 32)
port map
(clk_i => clk_i,
counter_incr_i => macrocyc_cnt_zero_p,
counter_reinit_i => num_of_macrocyc_cnt_reinit,
counter_is_full_o => num_of_macrocyc_cnt_full,
counter_o => num_of_macrocyc_cnt);
num_of_macrocyc_cnt_reinit <= core_rst_n or num_of_macrocyc_cnt_full;
---------------------------------------------------------------------------------------------------
-- turnaround counter --
---------------------------------------------------------------------------------------------------
......@@ -505,7 +611,7 @@ begin
-- -- -- -- -- -- -- -- -- -- --
turnar_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or turnar_host_load_p;
-- edge detection of the turnar_host_load signal
-- edge detection of the turnar_host_load signal
cmp_turnar_host_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map
......@@ -513,8 +619,8 @@ begin
rst_n_i => core_rst_n,
data_i => turnar_host_load,
ppulse_o => turnar_host_load_p);
--------------------------------------------------------------------------------------------------
-- silence counter --
--------------------------------------------------------------------------------------------------
......@@ -542,7 +648,7 @@ begin
data_i => silen_host_load,
ppulse_o => silen_host_load_p);
--------------------------------------------------------------------------------------------------
-- signals for tx --
--------------------------------------------------------------------------------------------------
......@@ -569,7 +675,7 @@ begin
ppulse_o => rx_host_rst_p);
-- -- -- -- -- -- -- -- -- -- --
rx_rst <= rx_host_rst_p or fd_txena;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- registering the number of received bytes
p_rx_bytes_num : process(clk_i)
......@@ -586,8 +692,8 @@ begin
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- extending the rx_fss_received_p until a core_rst or rx_rst is received
p_rx_fss_received_extend : process(clk_i)
begin
......@@ -601,8 +707,8 @@ begin
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- extending the rx_crc_wrong_p until a core_rst or rx_rst is received
p_rx_crc_wrong_extend : process(clk_i)
begin
......@@ -616,13 +722,13 @@ begin
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- rx --
---------------------------------------------------------------------------------------------------
cmp_masterfip_rx: masterfip_rx
port map
(clk_40m_i => clk_i,
(clk_i => clk_i,
rst_i => core_rst,
speed_i => speed,
fd_rxd_a_i => fd_rxd_i,
......@@ -640,16 +746,16 @@ begin
-------------------------------------------------------------
speed <= speed_b1_i & speed_b0_i;
---------------------------------------------------------------------------------------------------
-- tx --
---------------------------------------------------------------------------------------------------
cmp_masterfip_tx: masterfip_tx
port map
(clk_40m_i => clk_i,
(clk_i => clk_i,
rst_i => tx_rst,
speed_i => speed,
tx_bytes_num_i => tx_bytes_num,
......@@ -663,16 +769,29 @@ begin
tx_enable_o => fd_txena,
tx_clk_o => fd_txck);
-------------------------------------------------------------
tx_rst <= core_rst or tx_host_rst_p;
fd_txena_o <= fd_txena;
-- fd_txena_o <= fd_txena;
fd_txd_o <= fd_txd;
fd_txck_o <= fd_txck;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- delay for 1 cycle the fd_txena
fd_txena_delay : process(clk_i)
begin
if rising_edge(clk_i) then
if(tx_rst = '1') then
fd_txena_o <= '0';
else
fd_txena_o <= fd_txena;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------
-- signals for tx --
--------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------
-- edge detection on the tx_host_rst signal
cmp_tx_host_rst_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
......@@ -681,35 +800,55 @@ begin
rst_n_i => rst_n,
data_i => tx_host_rst,
ppulse_o => tx_host_rst_p);
-- extension of the tx_completed_p so as to ensure capturing by the wrnc
-- TODO: keep high and only reset upon reading from the MT
cmp_tx_extend_p : gc_extend_pulse
generic map (g_width => 32)
generic map (g_width => 32) -- 32 ticks long
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => tx_completed_p,
extended_o => tx_completed);
extended_o => tx_completed);
---------------------------------------------------------------------------------------------------
-- aux --
---------------------------------------------------------------------------------------------------
-- aux --
---------------------------------------------------------------------------------------------------
aux_o(7) <= out_of_sync_led;
aux_o(6) <= macrocyc_host_load_p;
aux_o(5) <= macrocyc_load_p;
aux_o(4) <= rx_byte_ready_p;
aux_o(3) <= macrocyc_cnt_zero_p;
aux_o(2) <= ext_sync_p;--tx_completed;
aux_o(1) <= tx_start;
aux_o(0) <= sync_led;
aux_o(6) <= mf_dbg_p_ext;--macrocyc_host_load_p;
aux_o(5) <= mf_dbg(5);--macrocyc_load_p;
aux_o(4) <= mf_dbg(4);--rx_byte_ready_p;
aux_o(3) <= mf_dbg(3);--macrocyc_cnt_zero_p;
aux_o(2) <= mf_dbg(2);--core_rst;--ext_sync_p;--tx_completed;
aux_o(1) <= mf_dbg(1);--tx_start;
aux_o(0) <= mf_dbg(0);--sync_led;
ext_sync_oe_o <= ext_sync_oe;
-- edge detection on the mf_dbg signal
-- cmp_mf_dbg_pulse_detect: gc_sync_ffs
-- generic map(g_sync_edge => "positive")
-- port map
-- (clk_i => clk_i,
-- rst_n_i => rst_n,
-- data_i => mf_dbg,
-- ppulse_o => mf_dbg_p);
-- extension of the mf_dbg_p to capture it easier on the scope
-- cmp_mf_dbg_p_extend : gc_extend_pulse
-- generic map (g_width => 32) -- 32 ticks long
-- port map
-- (clk_i => clk_i,
-- rst_n_i => core_rst_n,
-- pulse_i => mf_dbg_p,
-- extended_o => mf_dbg_p_ext);
---------------------------------------------------------------------------------------------------
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
......@@ -721,7 +860,7 @@ begin
-- chipscope_icon_1 : chipscope_icon
-- port map ( CONTROL0 => CONTROL);
-- TRIG0(8 downto 0) <= tx_bytes_num;
-- TRIG0(9) <= tx_start;
-- TRIG0(10) <= tx_start_p;
......@@ -741,12 +880,12 @@ begin
-- TRIG2(26 downto 19) <= rx_ctrl_byte;
-- TRIG2(27) <= rx_frame_ok_p;
-- TRIG2(28) <= rx_crc_wrong_p;
-- TRIG2(29) <= core_rst;
-- TRIG2(31 downto 30) <= speed_b1_i & speed_b0_i;
-- TRIG3 <= rx_frame(0);
--TRIG0(17) <= tx_start_p;
--TRIG0(18) <= rx_fss_crc_fes_ok_p;
--TRIG0(19) <= start_tx_p;
......@@ -757,11 +896,11 @@ begin
--TRIG1(15 downto 8) <= rx_byte_index;
--TRIG0(16) <= start_from_fpga;
--TRIG0(16) <= start_from_fpga;
--TRIG0(24 downto 17) <= retrig_nb_offset(7 downto 0);
--TRIG0(31 downto 25) <= clk_i_cycles_offset(6 downto 0);
--TRIG0(31 downto 25) <= clk_i_cycles_offset(6 downto 0);
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
......
rtl/fmc_masterfip_csr.vhd
View file @ d30c6031
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 11/17/15 15:00:50
-- Created : 12/04/15 19:19:40
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -34,6 +34,8 @@ entity fmc_masterfip_csr is
-- Ports for PASS_THROUGH field: 'reset magic value' in reg: 'rstn'
mf_rstn_lock_o : out std_logic_vector(15 downto 0);
mf_rstn_lock_wr_o : out std_logic;
-- Port for std_logic_vector field: 'debugging' in reg: 'dbg'
mf_dbg_o : out std_logic_vector(31 downto 0);
-- Port for BIT field: '1v8_shdn_n' in reg: 'adc'
mf_adc_1v8_shdn_n_o : out std_logic;
-- Port for BIT field: 'm5v_shdn_n' in reg: 'adc'
......@@ -74,6 +76,8 @@ entity fmc_masterfip_csr is
mf_silen_start_o : out std_logic;
-- Port for std_logic_vector field: 'macrocycle time counter' in reg: 'macrocycle time cnt'
mf_macrocyc_time_cnt_i : in std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'number of macrocycles' in reg: 'macrocycles number cnt'
mf_macrocyc_num_cnt_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'turnaround time counter' in reg: 'turnaround time cnt'
mf_turnar_time_cnt_i : in std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'silence time counter' in reg: 'silence time cnt'
......@@ -381,6 +385,7 @@ architecture syn of fmc_masterfip_csr is
signal mf_rstn_core_int : std_logic ;
signal mf_rstn_fd_int : std_logic ;
signal mf_dbg_int : std_logic_vector(31 downto 0);
signal mf_adc_1v8_shdn_n_int : std_logic ;
signal mf_adc_m5v_shdn_n_int : std_logic ;
signal mf_adc_5v_en_n_int : std_logic ;
......@@ -499,6 +504,7 @@ begin
mf_rstn_core_int <= '0';
mf_rstn_fd_int <= '0';
mf_rstn_lock_wr_o <= '0';
mf_dbg_int <= "00000000000000000000000000000000";
mf_adc_1v8_shdn_n_int <= '0';
mf_adc_m5v_shdn_n_int <= '0';
mf_adc_5v_en_n_int <= '0';
......@@ -648,6 +654,13 @@ begin
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000010" =>
if (wb_we_i = '1') then
mf_dbg_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_dbg_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000011" =>
if (wb_we_i = '1') then
mf_adc_1v8_shdn_n_int <= wrdata_reg(0);
mf_adc_m5v_shdn_n_int <= wrdata_reg(1);
......@@ -689,7 +702,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000011" =>
when "00000100" =>
if (wb_we_i = '1') then
mf_ext_sync_term_en_int <= wrdata_reg(0);
mf_ext_sync_dir_int <= wrdata_reg(1);
......@@ -731,13 +744,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000100" =>
when "00000101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_ext_sync_p_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000101" =>
when "00000110" =>
if (wb_we_i = '1') then
mf_bus_term_en_n_int <= wrdata_reg(0);
end if;
......@@ -775,7 +788,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000110" =>
when "00000111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(1 downto 0) <= mf_speed_i;
......@@ -811,7 +824,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000111" =>
when "00001000" =>
if (wb_we_i = '1') then
mf_macrocyc_lgth_int <= wrdata_reg(30 downto 0);
mf_macrocyc_start_int <= wrdata_reg(31);
......@@ -820,7 +833,7 @@ begin
rddata_reg(31) <= mf_macrocyc_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001000" =>
when "00001001" =>
if (wb_we_i = '1') then
mf_turnar_lgth_int <= wrdata_reg(30 downto 0);
mf_turnar_start_int <= wrdata_reg(31);
......@@ -829,7 +842,7 @@ begin
rddata_reg(31) <= mf_turnar_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001001" =>
when "00001010" =>
if (wb_we_i = '1') then
mf_silen_lgth_int <= wrdata_reg(30 downto 0);
mf_silen_start_int <= wrdata_reg(31);
......@@ -838,28 +851,34 @@ begin
rddata_reg(31) <= mf_silen_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001010" =>
when "00001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= mf_macrocyc_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001011" =>
when "00001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_macrocyc_num_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= mf_turnar_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001100" =>
when "00001110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= mf_silen_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001101" =>
when "00001111" =>
if (wb_we_i = '1') then
mf_tx_ctrl_rst_int <= wrdata_reg(0);
mf_tx_ctrl_start_int <= wrdata_reg(1);
......@@ -891,7 +910,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001110" =>
when "00010000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mf_tx_stat_stop_i;
......@@ -920,7 +939,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001111" =>
when "00010001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mf_fd_wdgn_i;
......@@ -957,7 +976,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010000" =>
when "00010010" =>
if (wb_we_i = '1') then
mf_rx_ctrl_rst_int <= wrdata_reg(0);
end if;
......@@ -995,7 +1014,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010001" =>
when "00010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mf_rx_stat_pream_ok_i;
......@@ -1022,7 +1041,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010010" =>
when "00010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= mf_rx_data_ctrl_i;
......@@ -1052,403 +1071,403 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010011" =>
when "00010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010100" =>
when "00010110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010101" =>
when "00010111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010110" =>
when "00011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg4_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010111" =>
when "00011001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg5_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011000" =>
when "00011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg6_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011001" =>
when "00011011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg7_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011010" =>
when "00011100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg8_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011011" =>
when "00011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg9_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011100" =>
when "00011110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg10_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011101" =>
when "00011111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg11_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011110" =>
when "00100000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg12_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011111" =>
when "00100001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg13_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100000" =>
when "00100010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg14_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100001" =>
when "00100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg15_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100010" =>
when "00100100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg16_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100011" =>
when "00100101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg17_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100100" =>
when "00100110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg18_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100101" =>
when "00100111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg19_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100110" =>
when "00101000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg20_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100111" =>
when "00101001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg21_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101000" =>
when "00101010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg22_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101001" =>
when "00101011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg23_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101010" =>
when "00101100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg24_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101011" =>
when "00101101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg25_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101100" =>
when "00101110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg26_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101101" =>
when "00101111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg27_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101110" =>
when "00110000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg28_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101111" =>
when "00110001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg29_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110000" =>
when "00110010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg30_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110001" =>
when "00110011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg31_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110010" =>
when "00110100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg32_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110011" =>
when "00110101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg33_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110100" =>
when "00110110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg34_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110101" =>
when "00110111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg35_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110110" =>
when "00111000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg36_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110111" =>
when "00111001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg37_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111000" =>
when "00111010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg38_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111001" =>
when "00111011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg39_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111010" =>
when "00111100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg40_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111011" =>
when "00111101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg41_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111100" =>
when "00111110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg42_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111101" =>
when "00111111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg43_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111110" =>
when "01000000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg44_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111111" =>
when "01000001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg45_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000000" =>
when "01000010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg46_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000001" =>
when "01000011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg47_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000010" =>
when "01000100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg48_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000011" =>
when "01000101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg49_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000100" =>
when "01000110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg50_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000101" =>
when "01000111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg51_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000110" =>
when "01001000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg52_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000111" =>
when "01001001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg53_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001000" =>
when "01001010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg54_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001001" =>
when "01001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg55_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001010" =>
when "01001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg56_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001011" =>
when "01001101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg57_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001100" =>
when "01001110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg58_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001101" =>
when "01001111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg59_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001110" =>
when "01010000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg60_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001111" =>
when "01010001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg61_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010000" =>
when "01010010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg62_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010001" =>
when "01010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg63_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010010" =>
when "01010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg64_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010011" =>
when "01010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg65_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010100" =>
when "01010110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_rx_data_reg66_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010101" =>
when "01010111" =>
if (wb_we_i = '1') then
mf_tx_data_ctrl_int <= wrdata_reg(7 downto 0);
end if;
......@@ -1479,462 +1498,462 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010110" =>
when "01011000" =>
if (wb_we_i = '1') then
mf_tx_data_reg1_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg1_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010111" =>
when "01011001" =>
if (wb_we_i = '1') then
mf_tx_data_reg2_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg2_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011000" =>
when "01011010" =>
if (wb_we_i = '1') then
mf_tx_data_reg3_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg3_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011001" =>
when "01011011" =>
if (wb_we_i = '1') then
mf_tx_data_reg4_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg4_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011010" =>
when "01011100" =>
if (wb_we_i = '1') then
mf_tx_data_reg5_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg5_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011011" =>
when "01011101" =>
if (wb_we_i = '1') then
mf_tx_data_reg6_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg6_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011100" =>
when "01011110" =>
if (wb_we_i = '1') then
mf_tx_data_reg7_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg7_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011101" =>
when "01011111" =>
if (wb_we_i = '1') then
mf_tx_data_reg8_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg8_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011110" =>
when "01100000" =>
if (wb_we_i = '1') then
mf_tx_data_reg9_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg9_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011111" =>
when "01100001" =>
if (wb_we_i = '1') then
mf_tx_data_reg10_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg10_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100000" =>
when "01100010" =>
if (wb_we_i = '1') then
mf_tx_data_reg11_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg11_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100001" =>
when "01100011" =>
if (wb_we_i = '1') then
mf_tx_data_reg12_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg12_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100010" =>
when "01100100" =>
if (wb_we_i = '1') then
mf_tx_data_reg13_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg13_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100011" =>
when "01100101" =>
if (wb_we_i = '1') then
mf_tx_data_reg14_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg14_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100100" =>
when "01100110" =>
if (wb_we_i = '1') then
mf_tx_data_reg15_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg15_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100101" =>
when "01100111" =>
if (wb_we_i = '1') then
mf_tx_data_reg16_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg16_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100110" =>
when "01101000" =>
if (wb_we_i = '1') then
mf_tx_data_reg17_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg17_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100111" =>
when "01101001" =>
if (wb_we_i = '1') then
mf_tx_data_reg18_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg18_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101000" =>
when "01101010" =>
if (wb_we_i = '1') then
mf_tx_data_reg19_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg19_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101001" =>
when "01101011" =>
if (wb_we_i = '1') then
mf_tx_data_reg20_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg20_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101010" =>
when "01101100" =>
if (wb_we_i = '1') then
mf_tx_data_reg21_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg21_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101011" =>
when "01101101" =>
if (wb_we_i = '1') then
mf_tx_data_reg22_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg22_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101100" =>
when "01101110" =>
if (wb_we_i = '1') then
mf_tx_data_reg23_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg23_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101101" =>
when "01101111" =>
if (wb_we_i = '1') then
mf_tx_data_reg24_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg24_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101110" =>
when "01110000" =>
if (wb_we_i = '1') then
mf_tx_data_reg25_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg25_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101111" =>
when "01110001" =>
if (wb_we_i = '1') then
mf_tx_data_reg26_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg26_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110000" =>
when "01110010" =>
if (wb_we_i = '1') then
mf_tx_data_reg27_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg27_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110001" =>
when "01110011" =>
if (wb_we_i = '1') then
mf_tx_data_reg28_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg28_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110010" =>
when "01110100" =>
if (wb_we_i = '1') then
mf_tx_data_reg29_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg29_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110011" =>
when "01110101" =>
if (wb_we_i = '1') then
mf_tx_data_reg30_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg30_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110100" =>
when "01110110" =>
if (wb_we_i = '1') then
mf_tx_data_reg31_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg31_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110101" =>
when "01110111" =>
if (wb_we_i = '1') then
mf_tx_data_reg32_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg32_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110110" =>
when "01111000" =>
if (wb_we_i = '1') then
mf_tx_data_reg33_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg33_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110111" =>
when "01111001" =>
if (wb_we_i = '1') then
mf_tx_data_reg34_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg34_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111000" =>
when "01111010" =>
if (wb_we_i = '1') then
mf_tx_data_reg35_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg35_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111001" =>
when "01111011" =>
if (wb_we_i = '1') then
mf_tx_data_reg36_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg36_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111010" =>
when "01111100" =>
if (wb_we_i = '1') then
mf_tx_data_reg37_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg37_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111011" =>
when "01111101" =>
if (wb_we_i = '1') then
mf_tx_data_reg38_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg38_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111100" =>
when "01111110" =>
if (wb_we_i = '1') then
mf_tx_data_reg39_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg39_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111101" =>
when "01111111" =>
if (wb_we_i = '1') then
mf_tx_data_reg40_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg40_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111110" =>
when "10000000" =>
if (wb_we_i = '1') then
mf_tx_data_reg41_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg41_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111111" =>
when "10000001" =>
if (wb_we_i = '1') then
mf_tx_data_reg42_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg42_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000000" =>
when "10000010" =>
if (wb_we_i = '1') then
mf_tx_data_reg43_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg43_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000001" =>
when "10000011" =>
if (wb_we_i = '1') then
mf_tx_data_reg44_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg44_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000010" =>
when "10000100" =>
if (wb_we_i = '1') then
mf_tx_data_reg45_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg45_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000011" =>
when "10000101" =>
if (wb_we_i = '1') then
mf_tx_data_reg46_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg46_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000100" =>
when "10000110" =>
if (wb_we_i = '1') then
mf_tx_data_reg47_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg47_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000101" =>
when "10000111" =>
if (wb_we_i = '1') then
mf_tx_data_reg48_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg48_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000110" =>
when "10001000" =>
if (wb_we_i = '1') then
mf_tx_data_reg49_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg49_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000111" =>
when "10001001" =>
if (wb_we_i = '1') then
mf_tx_data_reg50_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg50_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001000" =>
when "10001010" =>
if (wb_we_i = '1') then
mf_tx_data_reg51_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg51_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001001" =>
when "10001011" =>
if (wb_we_i = '1') then
mf_tx_data_reg52_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg52_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001010" =>
when "10001100" =>
if (wb_we_i = '1') then
mf_tx_data_reg53_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg53_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001011" =>
when "10001101" =>
if (wb_we_i = '1') then
mf_tx_data_reg54_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg54_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001100" =>
when "10001110" =>
if (wb_we_i = '1') then
mf_tx_data_reg55_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg55_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001101" =>
when "10001111" =>
if (wb_we_i = '1') then
mf_tx_data_reg56_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg56_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001110" =>
when "10010000" =>
if (wb_we_i = '1') then
mf_tx_data_reg57_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg57_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001111" =>
when "10010001" =>
if (wb_we_i = '1') then
mf_tx_data_reg58_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg58_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010000" =>
when "10010010" =>
if (wb_we_i = '1') then
mf_tx_data_reg59_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg59_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010001" =>
when "10010011" =>
if (wb_we_i = '1') then
mf_tx_data_reg60_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg60_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010010" =>
when "10010100" =>
if (wb_we_i = '1') then
mf_tx_data_reg61_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg61_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010011" =>
when "10010101" =>
if (wb_we_i = '1') then
mf_tx_data_reg62_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg62_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010100" =>
when "10010110" =>
if (wb_we_i = '1') then
mf_tx_data_reg63_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg63_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010101" =>
when "10010111" =>
if (wb_we_i = '1') then
mf_tx_data_reg64_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg64_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010110" =>
when "10011000" =>
if (wb_we_i = '1') then
mf_tx_data_reg65_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= mf_tx_data_reg65_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010111" =>
when "10011001" =>
if (wb_we_i = '1') then
mf_tx_data_reg66_int <= wrdata_reg(31 downto 0);
end if;
......@@ -1961,6 +1980,8 @@ begin
-- reset magic value
-- pass-through field: reset magic value in register: rstn
mf_rstn_lock_o <= wrdata_reg(31 downto 16);
-- debugging
mf_dbg_o <= mf_dbg_int;
-- 1v8_shdn_n
mf_adc_1v8_shdn_n_o <= mf_adc_1v8_shdn_n_int;
-- m5v_shdn_n
......@@ -1998,6 +2019,7 @@ begin
-- silence cnt start
mf_silen_start_o <= mf_silen_start_int;
-- macrocycle time counter
-- number of macrocycles
-- turnaround time counter
-- silence time counter
-- tx rst
......
rtl/masterFIP_pkg.vhd
View file @ d30c6031
......@@ -13,21 +13,13 @@
-- File masterFIP_pkg.vhd |
-- |
-- Description Definitions of constants, types, entities, functions |
-- Author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 11/01/2011 |
-- Version v0.05 |
-- Author Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 30/09/2015 |
-- Version v0.01 |
-- |
---------------- |
-- Last changes |
-- 8/2010 v0.01 EG byte_array of all vars cleaned_up (ex: subs_i removed) |
-- 10/2010 v0.02 EG base_addr unsigned(8 downto 0) instead of |
-- std_logic_vector (9 downto 0) to simplify calculations; cleaning-up |
-- 1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs |
-- added DualClkRam |
-- 2/2011 v0.04 EG function for manch_encoder; cleaning up of constants+generics |
-- added CTRL bytes for RP_DAT_MSG and RP_DAT_RQ and RP_DAT_RQ_MSG |
-- 2/2011 v0.05 EG JTAG variables added |
-- 11/2011 v0.06 EG c_SESSION_TIMEOUT_C_LGTH, c_JTAG_TIMEOUT_C_LGTH added |
-- 09/2015 v0.01 EG First version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -188,11 +180,13 @@ package masterFIP_pkg is
mf_rstn_lock_o : out std_logic_vector(15 downto 0);
mf_rstn_lock_wr_o : out std_logic;
mf_dbg_o : out std_logic_vector(31 downto 0);
mf_adc_1v8_shdn_n_o : out std_logic;
mf_adc_m5v_shdn_n_o : out std_logic;
mf_adc_5v_en_n_o : out std_logic;
mf_adc_prim_conn_n_o : out std_logic;
mf_adc_sec_conn_n_o : out std_logic;
mf_adc_prim_conn_n_o : out std_logic;
mf_adc_sec_conn_n_o : out std_logic;
mf_ext_sync_term_en_o : out std_logic;
mf_ext_sync_dir_o : out std_logic;
......@@ -206,6 +200,7 @@ package masterFIP_pkg is
mf_macrocyc_lgth_o : out std_logic_vector(30 downto 0);
mf_macrocyc_start_o : out std_logic;
mf_macrocyc_num_cnt_i : in std_logic_vector(31 downto 0);
mf_turnar_lgth_o : out std_logic_vector(30 downto 0);
mf_turnar_start_o : out std_logic;
mf_silen_lgth_o : out std_logic_vector(30 downto 0);
......@@ -457,7 +452,7 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
component masterfip_rx is
port (
clk_40m_i : in std_logic;
clk_i : in std_logic;
speed_i : in std_logic_vector (1 downto 0);
fd_rxd_a_i : in std_logic;
rst_i : in std_logic;
......@@ -478,7 +473,7 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
component masterfip_tx is
port (
clk_40m_i : in std_logic;
clk_i : in std_logic;
speed_i : in std_logic_vector (1 downto 0);
rst_i : in std_logic;
tx_start_p_i : in std_logic;
......
rtl/masterfip_rx.vhd
View file @ d30c6031
......@@ -23,9 +23,10 @@
-- |
-- o bytes_c : for the counting of the retrieved bytes |
-- |
-- o create_32bit_words: for the formation of 32-bit words to be provided to the WRNC|
-- o create_32bit_words: for the formation of 32-bit words to be provided to the |
-- processor (Mock Turtle for example) |
-- |
-- WRNC |
-- Mock Turtle |
-- ___________________________________________________________ |
-- | | |
-- | _________ _______________________ | |
......@@ -94,13 +95,13 @@ use work.wf_package.all;
--=================================================================================================
entity masterfip_rx is port(
-- INPUTS
clk_40m_i : in std_logic; -- 40 MHZ clock
clk_i : in std_logic; -- 100 MHZ clock
rst_i : in std_logic; -- core rst, synched with clk_40m_i
rst_i : in std_logic; -- core rst, synched with clk_i
rx_rst_i : in std_logic; -- rx reset during production or
-- reset pulse from the WRNC when during
-- reception a frame is rejected
-- reset pulse from the processor (eg. MT)
-- when during reception a frame is rejected
-- (ex: RP_DAT > 133 bytes, wrong CTRL byte)
speed_i : in std_logic_vector(1 downto 0); -- WorldFIP bit rate
......@@ -123,7 +124,7 @@ entity masterfip_rx is port(
-- structure with 66 words of 32-bit each
-- this represents the max length of a frame
-- upon the rx_fss_crc_fes_ok_p_o only
-- rx_byte_index_o bytes have to be read by the WRNC
-- rx_byte_index_o bytes have to be read by the processor
rx_fss_crc_fes_ok_p_o : out std_logic; -- indication of a frame with
-- correct FSS, FES & CRC; pulse upon FES detection
......@@ -170,7 +171,7 @@ begin
cmp_rx_deglitcher: wf_rx_deglitcher
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
nfip_rst_i => rst_i,
fd_rxd_a_i => fd_rxd_a_i,
-----------------------------------------------------------------
......@@ -183,7 +184,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_deserializer: wf_rx_deserializer
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
nfip_rst_i => rst_i,
rx_rst_i => rx_rst_i,
fd_rxd_f_edge_p_i => s_fd_rxd_filt_f_edge_p,
......@@ -208,7 +209,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_osc: wf_rx_osc
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
rate_i => speed_i,
nfip_rst_i => rst_i,
fd_rxd_edge_p_i => s_rxd_filt_edge_p,
......@@ -227,7 +228,7 @@ begin
cmp_rx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 9)
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
counter_reinit_i => bytes_c_rst,
counter_incr_i => rx_byte_ready_p,
counter_is_full_o => open,
......@@ -241,9 +242,9 @@ begin
---------------------------------------------------------------------------------------------------
-- combination of four retrieved bytes to a 32-bit word --
---------------------------------------------------------------------------------------------------
create_32bit_words: process (clk_40m_i)
create_32bit_words: process (clk_i)
begin
if rising_edge (clk_40m_i) then
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
byte0 <= (others => '0');
byte1 <= (others => '0');
......@@ -272,9 +273,9 @@ begin
---------------------------------------------------------------------------------------------------
-- transfer 32bit words to the cons_frame registers
delay: process (clk_40m_i)
delay: process (clk_i)
begin
if rising_edge (clk_40m_i) then
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
rx_byte_index_d1 <= (others =>'0'); -- needed for synching
else
......@@ -286,9 +287,9 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
data_transfer_to_regs: process (clk_40m_i)
data_transfer_to_regs: process (clk_i)
begin
if rising_edge (clk_40m_i) then
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
word32_num <= 0;
rx_frame_o <= (others =>(others =>'0'));
......
rtl/masterfip_tx.vhd
View file @ d30c6031
......@@ -15,20 +15,21 @@
-- Description The unit groups the main actions that regard FIELDRIVE data transmission. |
-- It instantiates the units/processes: |
-- |
-- o wf_tx_serializer: that receives bytes from the WRNC trough the tx_frame , |
-- structure, encodes them (Manchester 2), adds the FSS, FCS, FES|
-- fields and puts one by one bits to the FIELDRIVE output FD_TXD|
-- following the synchronization signals from the wf_tx_osc unit.|
-- o wf_tx_serializer: that receives bytes from the processor (Mock Turtle for |
-- example) trough the tx_frame structure, encodes them |
-- (Manchester 2), adds the FSS, FCS, FES fields and puts one by |
-- one bits to the FIELDRIVE output FD_TXD following the |
-- synchronization signals from the wf_tx_osc unit. |
-- Also generates the output FD_TXENA. |
-- |
-- o wf_tx_osc : that generates the output FD_TXCK and the array of pulses |
-- tx_sched_p_buff, used for the synchronization of the |
-- wf_tx_serializer's actions. |
-- |
-- o data_retrieval : that copies the bytes provided by the WRNC upon the activation|
-- of the signal tx_start |
-- o data_retrieval : that copies the bytes provided by the processor upon the |
-- activation of the signal tx_start. |
-- |
-- WRNC |
-- Mock Turtle |
-- ___________________________________________________________ |
-- | _______________________________ | |
-- | | | | |
......@@ -96,9 +97,9 @@ use work.wf_package.all;
entity masterfip_tx is port(
-- INPUTS
clk_40m_i : in std_logic; -- 40 MHz clock
clk_i : in std_logic; -- 100 MHz clock
rst_i : in std_logic; -- core rst, synched with clk_40m_i
rst_i : in std_logic; -- core rst, synched with clk_i
speed_i : in std_logic_vector(1 downto 0); -- WorldFIP bit rate
......@@ -166,9 +167,9 @@ begin
-- All the frame bytes are copied to local registers; like this the frame data remain stable
-- until the next tx_start_p_i arrives.
data_retrieval: process (clk_40m_i)
data_retrieval: process (clk_i)
begin
if rising_edge (clk_40m_i) then
if rising_edge (clk_i) then
if rst_i = '1' then
prod_frame <= ((others => (others=>'0')));
ctrl_byte <= (others=>'0');
......@@ -188,9 +189,9 @@ begin
-- Mux to select the right byte --
---------------------------------------------------------------------------------------------------
-- The process retrieves sequentially one by one the byte to be sent to the serializer.
select_byte: process (clk_40m_i)
select_byte: process (clk_i)
begin
if rising_edge (clk_40m_i) then
if rising_edge (clk_i) then
if rst_i = '1' then
word32_num <= 0;
else
......@@ -207,7 +208,7 @@ begin
cmp_tx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 9)
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
counter_reinit_i => tx_start_p_i,
counter_incr_i => tx_byte_request_p,
counter_is_full_o => open,
......@@ -231,7 +232,7 @@ begin
cmp_tx_serializer: wf_tx_serializer
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
nfip_rst_i => rst_i,
byte_i => tx_byte,
tx_start_p_i => tx_start_p_i,
......@@ -249,7 +250,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_tx_osc: wf_tx_osc
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
rate_i => speed_i,
nfip_rst_i => rst_i,
tx_osc_rst_p_i => s_tx_osc_rst_p,
......@@ -267,9 +268,9 @@ begin
prod_data_lgth_match <= '1' when prod_bytes_c = unsigned(bytes_num) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
synch_signals: process (clk_40m_i)
synch_signals: process (clk_i)
begin
if rising_edge (clk_40m_i) then
if rising_edge (clk_i) then
if rst_i = '1' then
last_data_byte_p <= '0'; -- indication of the last data byte (CRC, FES not included)
last_data_byte_p_d <= '0';
......
rtl/wbgen/fmc_masterfip_csr.wb
View file @ d30c6031
......@@ -62,6 +62,23 @@ peripheral {
};
};
-------------------------------------------------------------------------------
-- debugging --
-------------------------------------------------------------------------------
reg {
name = "dbg";
description = "for debugging purpuses";
prefix = "dbg";
field {
name = "debugging";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-------------------------------------------------------------------------------
-- ADC power supplies --
......@@ -318,7 +335,21 @@ peripheral {
};
};
reg {
name = "macrocycles number cnt";
prefix = "macrocyc_num_cnt";
field {
name = "number of macrocycles";
description = "current amount of macrocycles";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "turnaround time cnt";
prefix = "turnar_time_cnt";
......
sim/spec/data_vectors/masterFIP_test.vec
View file @ d30c6031
......@@ -60,115 +60,115 @@ wait %d20
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000030034 F 00000001
wr 000000000003003C F 00000001
wait %d10
wr 0000000000030034 F 00000000
wr 000000000003003C F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030154 F 00000003
wr 000000000003015C F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 0000000000030158 F 00000305
wr 0000000000030160 F 00000305
wait %d20
-- tx_start
wr 0000000000030034 F 00000202
wr 000000000003003C F 00000202
wait %d20000
--------------- RP_DAT ---------------
-- tx_rst
wr 0000000000030034 F 00000001
wr 000000000003003C F 00000001
wait %d10
wr 0000000000030034 F 00000000
wr 000000000003003C F 00000000
wait %d20
-- control byte of rp_dat
wr 0000000000030154 F 00000002
wr 000000000003015C F 00000002
wait %d20
-- data bytes
wr 0000000000030158 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wr 0000000000030160 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wait %d20
wr 000000000003015c F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
-- tx_start
wr 0000000000030034 F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wr 000000000003003C F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wait %d40000
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000030034 F 00000001
wr 000000000003003C F 00000001
wait %d10
wr 0000000000030034 F 00000000
wr 000000000003003C F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030154 F 00000003
wr 000000000003015C F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 0000000000030158 F 00000314
wr 0000000000030160 F 00000314
wait %d20
-- tx_start
wr 0000000000030034 F 00000202
wr 000000000003003C F 00000202
wait %d20
-- deactivate tx_start
wr 0000000000030034 F 00000000
wr 000000000003003C F 00000000
-- release rx_rst
wr 0000000000030040 F 00000000
wr 0000000000030048 F 00000000
wait %d40000
-- read received data
rd 0000000000030048 F 00000002
rd 0000000000030050 F 00000002
wait %d20
rd 000000000003004c F 03800550
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 0000000000030034 F 00000001
wr 000000000003003C F 00000001
wait %d10
wr 0000000000030034 F 00000000
wr 000000000003003C F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030154 F 00000003
wr 000000000003015C F 00000003
wait %d20
-- data bytes varid = 0603 for agent to produce
wr 0000000000030158 F 00000306
wr 0000000000030160 F 00000306
wait %d20
-- tx_start
wr 0000000000030034 F 00000202
wr 000000000003003C F 00000202
wait %d20
-- deactivate tx_start
wr 0000000000030034 F 00000000
wr 000000000003003C F 00000000
-- release rx_rst
wr 0000000000030040 F 00000000
wr 0000000000030048 F 00000000
wait %d40000
-- read received data
rd 0000000000030048 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
rd 0000000000030050 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
wait %d20
rd 000000000003004c F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
rd 0000000000030054 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
wait %d20
rd 0000000000030050 F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
rd 0000000000030058 F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
wait %d20
rd 0000000000030054 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 000000000003005C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030058 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000030060 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003005C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
......@@ -236,13 +236,13 @@ wait %d40000
--------------- RP_FIN ---------------
-- control byte of rp_fin
wr 0000000000030154 F 00000040
wr 000000000003015C F 00000040
wait %d20
-- rx_rst
wr 0000000000030040 F 00000001
wr 0000000000030048 F 00000001
wait %d20
-- tx_start
wr 0000000000030034 F 00000002
wr 000000000003003C F 00000002
wait %d20000
\ No newline at end of file
syn/spec/spec_masterFIP.xise
View file @ d30c6031
......@@ -16,11 +16,11 @@
<files>
<file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
......@@ -28,7 +28,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../../rtl/irq_generator.vhd" xil_pn:type="FILE_VHDL">
......@@ -60,7 +60,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
......@@ -76,7 +76,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
......@@ -120,43 +120,43 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
......@@ -180,19 +180,19 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
......@@ -308,7 +308,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
......@@ -628,39 +628,39 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
......@@ -670,15 +670,11 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../top/spec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterFIP_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../rtl/masterFIP_pkg.vhd" xil_pn:type="FILE_VHDL">
......@@ -686,7 +682,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../top/spec/spec_masterFIP.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
......@@ -698,11 +694,11 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/tb_masterFIP.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/gnum_model/util.vhd" xil_pn:type="FILE_VHDL">
......@@ -710,19 +706,19 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/gnum_model/cmd_router.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/gnum_model/gn412x_bfm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/gnum_model/mem_model.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/gnum_model/textutil.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/dualram_512x8.vhd" xil_pn:type="FILE_VHDL">
......@@ -730,15 +726,15 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/nanofip.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterfip_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/gnum_model/cmd_router1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/fmc_masterfip_eic.vhd" xil_pn:type="FILE_VHDL">
......@@ -746,7 +742,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_wb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_crc.vhd" xil_pn:type="FILE_VHDL">
......@@ -774,7 +770,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../rtl/masterfip_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
......@@ -786,7 +782,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../rtl/masterfip_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../rtl/from_nanofip/wf_package.vhd" xil_pn:type="FILE_VHDL">
......@@ -794,15 +790,15 @@
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_cons_bytes_processor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_cons_outcome.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_consumption.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_dualram_512x8_clka_rd_clkb_wr.vhd" xil_pn:type="FILE_VHDL">
......@@ -810,47 +806,47 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_engine_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_fd_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_fd_transmitter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_jtag_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_model_constr_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_prod_bytes_retriever.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_prod_data_lgth_calc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_prod_permit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_production.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_reset_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP/wf_status_bytes_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec/spec_masterFIP.ucf" xil_pn:type="FILE_UCF">
......@@ -889,47 +885,47 @@
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/slone_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/slone_monitor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/user_access_monitor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/user_config.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/user_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/user_sequencer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/wishbone_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/wishbone_monitor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/tb_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/board_settings.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="94"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../sim/spec/testbench/encounter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
......@@ -960,35 +956,39 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="261"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="262"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_64x512.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_64x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="271"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_64x512.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="272"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="280"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="281"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="316"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......@@ -1257,8 +1257,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_masterFIP/dut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spec_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -1281,7 +1281,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_masterFIP" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spec_masterFIP" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
syn/spec_wrnode/spec_masterfip_wrnode.xise
View file @ d30c6031
......@@ -863,9 +863,6 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
</file>
<file xil_pn:name="../../top/spec_wrnode/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......@@ -1313,6 +1310,10 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="389"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec_wrnode/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="391"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......
top/spec/spec_masterFIP.ucf
View file @ d30c6031
......@@ -20,10 +20,6 @@ TIMESPEC TS_p2l_clk_n_i = PERIOD "p2l_clk_n_i" 5 ns HIGH 50%;
#----------------------------------------
# FMC slot
#----------------------------------------
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
......@@ -54,7 +50,6 @@ NET "speed_b0_i" IOSTANDARD = "LVCMOS25";
NET "speed_b1_i" LOC = AB5;
NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = C19;
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
......@@ -102,7 +97,6 @@ NET "adc_sec_conn_n_o" IOSTANDARD = "LVCMOS25";
#NET "mezz_onewire_b" LOC = "A19";
#NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
#NET "mezz_sys_scl_b" LOC = "F7";
#NET "mezz_sys_scl_b" IOSTANDARD = "LVCMOS25";
#NET "mezz_sys_sda_b" LOC = "F8";
......
top/spec/spec_masterFIP.vhd
View file @ d30c6031
--_________________________________________________________________________________________________
-- |
-- |SPEC TDC| |
-- |SPEC masterFIP| |
-- |
-- CERN,BE/CO-HT |
-- CERN, BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- spec_masterFIP |
-- spec_masterFIP |
-- |
---------------------------------------------------------------------------------------------------
-- File spec_masterFIP.vhd |
-- |
-- Description TDC top level for a SPEC carrier, without White Rabbit support. |
-- Description Top level of a simple masterFIP on a SPEC carrier. |
-- Figure 1 shows the architecture of the unit. |
-- |
-- For the communication with the PCIe, the ohwr.org GN4124 core is instantiated. |
-- This design does not use the Mock Turtle core and can only be used for very |
-- simple WorldFIP manipulations. |
-- |
-- The fmc_masterFIP_core mainly implements the WorldFIP serializer and deserialiser.|
-- Its interface component fmc_masterfip_csr provides a set of registers to basically|
-- - control the serialiser to send out WorldFIP frames and |
-- - monitor if a WorldFIP frame has arrived to the deserialiser |
-- The core accesses all the WorldFIP-specific parts of the masterFIP mezzanine board|
-- However there is no access to the ADC part of the masterFIP mezzanine board. |
-- |
-- The SPEC_CSR module provides general information on the SPEC PCB version, PLLs |
-- locking state etc. |
-- |
-- The carrier_info module provides general information on the SPEC PCB version, PLLs|
-- locking state etc. |
-- The 1-Wire core provides communication with the SPEC Thermometer&UniqueID chip. |
-- |
-- All the cores communicate with the GN4124 core through the SDB crossbar. The SDB |
-- crossbar is responsible for managing the access to the GN4124 core. |
-- |
-- The speed of all the cores (TDC mezzanine, VIC, carrier csr, 1-Wire, SDB as well |
-- as the GN4124 core) is 40 MHz. |
-- The design has only one clock domain, 100 MHz generated by a Xilinx internal PLL |
-- which is using the 20 MHz VCXO on the SPEC. |
-- |
-- The 40 MHz clock comes from an internal Xilinx PLL, which is using the 20MHz VCXO |
-- of the carrier. |
-- __________________________________________________________________ |
-- _________ | ___ _____ | |
-- | | | ____________________________ | | | | | |
-- |FielDrive| | | | | | | | | |
-- | |<->| | masterFIP mezzanine | --- | | | | | |
-- |_________| | |--|____________________________| | | | G | | |
-- mezz | | | | | | | |
-- | | ____________________________ | S | | N | | |
-- | |->| | | | | | | |
-- | | Vector Interrupt Controller| ---- | D | <--> | 4 | | |
-- | |____________________________| | | | | | |
-- | | B | | 1 | | |
-- | ____________________________ | | | | | |
-- | | | | | | 2 | | |
-- SPEC 1Wire <-> | | 1-Wire | ---- | | | | | |
-- | |____________________________| | | | 4 | | |
-- | / | | | | | |
-- | ____________________________ / | | | | | |
-- | | | / | | | | | |
-- | | carrier_info | / | | | | | |
-- | |____________________________| | | | | | |
-- | |___| |_____| | |
-- | | |
-- | ______________________________________________ | |
-- SPEC LEDs <-> | |___________________LEDs_______________________| | |
-- | | |
-- |__________________________________________________________________| |
-- __________________________________________________________________ |
-- | SPEC FPGA | |
-- ___________ | ___ _____ | |
-- | | | ____________________________ | | | | | |
-- | masterFIP | | | | | | | | | |
-- | mezz |<->| | masterFIP mezzanine | --- | | | | | |
-- |___________| | |____________________________| | | | G | | |
-- | | | | N | | |
-- | ____________________________ | S | | 4 | | |
-- SPEC 1Wire <->| | SPEC 1-Wire | ---- | D | <--> | 1 | | |
-- | |____________________________| | B | | 2 | | |
-- | | | | 4 | | |
-- | ____________________________ | | | | | |
-- | | SPEC CSR | ---- | | | | | |
-- | |____________________________| | | | | | |
-- | |___| |_____| | |
-- |__________________________________________________________________| |
-- Figure 1 |
-- |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 07/2014 |
-- Version v1 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 07/2014 v1 EG First version |
-- |
-- 07/2014 v1 EG concept validation using very basic board |
-- 07/2015 v2 EG validation of the masterFIP v1 prototype board |
-- 01/2016 v3 EG cleaned-up version to be used by PTS team |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -103,19 +101,21 @@ entity spec_masterFIP is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
values_for_simul : boolean := FALSE); -- this generic is set to TRUE
-- when instantiated in a test-bench
values_for_simul : boolean := FALSE); -- set to TRUE in test-bench instantiation
port
(-- SPEC carrier
clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
carrier_scl_b : inout std_logic; -- SPEC EEPROM
carrier_sda_b : inout std_logic;
carrier_onewire_b : inout std_logic; -- 1-wire
button1_i : in std_logic := '1'; -- reset button
button2_i : in std_logic := '1'; -- not used button
carrier_onewire_b : inout std_logic; -- SPEC 1-wire
led_green_o : out std_logic; -- LEDs carrier front pannel
led_red_o : out std_logic;
button1_i : in std_logic := '1';
button2_i : in std_logic := '1';
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic; -- mezzanine presence
-- Interface with GN4124
rst_n_a_i : in std_logic;
......@@ -144,29 +144,13 @@ entity spec_masterFIP is
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 8
irq_aux_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 9, aux signal
-- Bus Speed
speed_b0_i : in std_logic;
-- masterFIP mezzanine
speed_b0_i : in std_logic; -- WorldFIP bus Speed
speed_b1_i : in std_logic;
-- Bus termination
bus_term_en_n_o : out std_logic;
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_o : out std_logic;
ext_sync_tst_n_o : out std_logic;
ext_sync_i : in std_logic;
bus_term_en_n_o : out std_logic; -- WorldFIP bus termination
-- Power supplies for the ADC
adc_1v8_shdn_n_o : out std_logic;
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
adc_prim_conn_n_o : out std_logic;
adc_sec_conn_n_o : out std_logic;
-- FielDrive
fd_rxcdn_i : in std_logic;
fd_rxcdn_i : in std_logic; -- FielDrive
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
......@@ -175,18 +159,22 @@ entity spec_masterFIP is
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
-- LEDs mezzanine
led_tx_err_n_o : out std_logic;
ext_sync_term_en_o : out std_logic; -- External synch pulse transceiver
ext_sync_dir_o : out std_logic;
ext_sync_oe_o : out std_logic;
ext_sync_tst_n_o : out std_logic;
ext_sync_i : in std_logic;
adc_1v8_shdn_n_o : out std_logic; -- Power supplies for the ADC
adc_m5v_shdn_n_o : out std_logic;
adc_5v_en_n_o : out std_logic;
adc_prim_conn_n_o : out std_logic;
adc_sec_conn_n_o : out std_logic;
led_tx_err_n_o : out std_logic; -- LEDs mezzanine front pannel
led_tx_act_n_o : out std_logic;
led_rx_err_n_o : out std_logic;
led_rx_act_n_o : out std_logic;
-- LEDs spec
led_green_o : out std_logic;
led_red_o : out std_logic;
-- Carrier other signals
pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
prsnt_m2c_n_i : in std_logic); -- Mezzanine presence (active low)
led_rx_act_n_o : out std_logic);
end spec_masterFIP;
......@@ -202,9 +190,9 @@ architecture rtl of spec_masterFIP is
-- Master ports on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 3;
constant c_WB_SLAVE_SPEC_ONEWIRE: integer := 0; -- Carrier onewire interface
constant c_WB_SLAVE_SPEC_INFO : integer := 1; -- Info on SPEC control and status registers
constant c_WB_SLAVE_MASTERFIP : integer := 2; -- TDC core configuration
constant c_WB_SLAVE_SPEC_ONEWIRE: integer := 0; -- SPEC 1-wire
constant c_WB_SLAVE_SPEC_INFO : integer := 1; -- SPEC CSR
constant c_WB_SLAVE_MASTERFIP : integer := 2; -- masterFIP core
-- SDB header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
......@@ -226,37 +214,30 @@ architecture rtl of spec_masterFIP is
-- Signals --
---------------------------------------------------------------------------------------------------
-- SPEC VCXO clock
signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic;
-- masterFIP core clock and reset
signal clk_40m_sys, rst_sys : std_logic;
signal rst_sys_n : std_logic;
signal pllout_clk_sys, pllout_clk_sys_fb : std_logic;
signal sys_locked, pll_status : std_logic;
-- clocks
signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic;
signal clk_100m_sys, pllout_clk_sys : std_logic;
signal pllout_clk_sys_fb : std_logic;
signal sys_locked, pll_status : std_logic;
-- reset
signal rst_sys, rst_sys_n : std_logic;
-- WISHBONE from crossbar master port
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- WISHBONE to crossbar slave port
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal gn_wb_adr : std_logic_vector(31 downto 0);
-- Carrier CSR info
signal gn4124_status : std_logic_vector(31 downto 0);
-- Carrier 1-wire
signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
-- VIC
signal fmc_eic_irq, irq_to_gn4124 : std_logic;
signal fmc_eic_irq_synch : std_logic_vector (1 downto 0);
-- EEPROM on mezzanine
signal tdc_scl_out, tdc_scl_in, tdc_sda_out, tdc_sda_in: std_logic;
signal tdc_scl_oen, tdc_sda_oen : std_logic;
signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
signal gn_wb_adr : std_logic_vector(31 downto 0);
-- GN4124
signal gn4124_status : std_logic_vector(31 downto 0);
-- SPEC 1-wire
signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
-- aux
signal aux : std_logic_vector(7 downto 0);
signal pll_sclk, pll_sdi, pll_dac_sync, pll_cs,led_red , tx_start_p, irq_p: std_logic;
signal aux : std_logic_vector(7 downto 0);
-- LEDs
signal led_clk_40m_divider : unsigned(22 downto 0);
signal led_clk_40m_aux : std_logic_vector(7 downto 0);
signal rx_err, rx_act, fd_txena : std_logic;
signal led_clk_100m_divider : unsigned(22 downto 0);
signal led_clk_100m_aux : std_logic_vector(7 downto 0);
signal rx_err, rx_act, fd_txena : std_logic;
--=================================================================================================
......@@ -264,9 +245,8 @@ architecture rtl of spec_masterFIP is
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- 125 MHz clk and Reset for TDC core --
-- 100 MHz universal clk generation --
---------------------------------------------------------------------------------------------------
cmp_spec_clk_ibuf : IBUFG
......@@ -283,10 +263,10 @@ begin
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 10, -- 40 MHz ----***---- 25 10
CLKOUT0_DIVIDE => 10, -- 100 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 125 MHz, not used
CLKOUT1_DIVIDE => 8,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
......@@ -306,38 +286,38 @@ begin
RST => '0',
CLKFBIN => pllout_clk_sys_fb,
CLKIN => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sys_clk_buf : BUFG
port map
(O => clk_40m_sys,
(O => clk_100m_sys,
I => pllout_clk_sys);
---------------------------------------------------------------------------------------------------
-- Reset for 62.5 MHz clk domain --
-- RESET --
---------------------------------------------------------------------------------------------------
cmp_spec_rst_gen : spec_reset_gen
port map
(clk_sys_i => clk_40m_sys,
rst_pcie_n_a_i => rst_n_a_i,
rst_button_n_a_i => button1_i,
(clk_sys_i => clk_100m_sys,
rst_pcie_n_a_i => rst_n_a_i, -- reset from GN4124 chip
rst_button_n_a_i => button1_i, -- reset from SPEC button
rst_n_o => rst_sys_n);
-- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_sys <= not rst_sys_n;
---------------------------------------------------------------------------------------------------
-- CSR WISHBONE CROSSBAR --
---------------------------------------------------------------------------------------------------
-- 0x00000 -> SDB
-- 0x10000 -> Carrier 1-wire master
-- 0x20000 -> Carrier CSR information
-- 0x30000 -> Vector Interrupt Controller
-- 0x40000 -> masterFIP mezzanine SDB
-- 0x10000 -> masterFIP core configuration and data retrieval
-- 0x11000 -> masterFIP Mezzanine 1-wire master
-- 0x12000 -> masterFIP Mezzanine Embedded Interrupt Controller
-- 0x13000 -> masterFIP Mezzanine I2C master
-- 0x10000 -> SPEC 1-wire master
-- 0x20000 -> SPEC CSR information
-- 0x30000 -> masterFIP mezzanine SDB
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map
(g_num_masters => c_NUM_WB_SLAVES,
......@@ -347,50 +327,52 @@ begin
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
port map
(clk_sys_i => clk_40m_sys,
(clk_sys_i => clk_100m_sys,
rst_n_i => rst_sys_n,
slave_i => cnx_slave_in,
slave_o => cnx_slave_out,
master_i => cnx_master_in,
master_o => cnx_master_out);
---------------------------------------------------------------------------------------------------
-- GN4124 CORE --
---------------------------------------------------------------------------------------------------
cmp_gn4124_core: gn4124_core
port map
(rst_n_a_i => rst_n_a_i,
status_o => gn4124_status,
-- P2L Direction Source Sync DDR related signals
-- P2L Direction Source Sync DDR related signals
p2l_clk_p_i => p2l_clk_p_i,
p2l_clk_n_i => p2l_clk_n_i,
p2l_data_i => p2l_data_i,
p2l_dframe_i => p2l_dframe_i,
p2l_valid_i => p2l_valid_i,
-- P2L Control
-- P2L Control
p2l_rdy_o => p2l_rdy_o,
p_wr_req_i => p_wr_req_i,
p_wr_rdy_o => p_wr_rdy_o,
rx_error_o => rx_error_o,
-- L2P Direction Source Sync DDR related signals
-- L2P Direction Source Sync DDR related signals
l2p_clk_p_o => l2p_clk_p_o,
l2p_clk_n_o => l2p_clk_n_o,
l2p_data_o => l2p_data_o ,
l2p_dframe_o => l2p_dframe_o,
l2p_valid_o => l2p_valid_o,
l2p_edb_o => l2p_edb_o,
-- L2P Control
-- L2P Control
l2p_rdy_i => l2p_rdy_i,
l_wr_rdy_i => l_wr_rdy_i,
p_rd_d_rdy_i => p_rd_d_rdy_i,
tx_error_i => tx_error_i,
vc_rdy_i => vc_rdy_i,
-- Interrupt interface
-- Interrupt interface
dma_irq_o => open,
irq_p_i => irq_to_gn4124,
irq_p_i => '0',
irq_p_o => irq_p_o,
-- CSR WISHBONE interface (master pipelined)
csr_clk_i => clk_40m_sys,
-- CSR WISHBONE interface (master pipelined)
csr_clk_i => clk_100m_sys,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
csr_sel_o => cnx_slave_in(c_MASTER_GENNUM).sel,
......@@ -400,24 +382,24 @@ begin
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
csr_err_i => cnx_slave_out(c_MASTER_GENNUM).err,
csr_rty_i => cnx_slave_out(c_MASTER_GENNUM).rty,
csr_int_i => '0',
-- DMA: not used
dma_clk_i => clk_40m_sys,
csr_err_i => cnx_slave_out(c_MASTER_GENNUM).err,
csr_rty_i => cnx_slave_out(c_MASTER_GENNUM).rty,
csr_int_i => '0',
-- DMA: not used
dma_clk_i => clk_100m_sys,
dma_adr_o => open,
dma_cyc_o => open,
dma_dat_o => open,
dma_sel_o => open,
dma_stb_o => open,
dma_we_o => open,
dma_err_i => '0',
dma_err_i => '0',
dma_ack_i => '1',
dma_rty_i => '0',
dma_int_i => '0',
dma_rty_i => '0',
dma_int_i => '0',
dma_dat_i => (others => '0'),
dma_stall_i => '0',
dma_reg_clk_i => clk_40m_sys,
dma_reg_clk_i => clk_100m_sys,
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
......@@ -434,16 +416,22 @@ begin
---------------------------------------------------------------------------------------------------
-- masterFIP BOARD --
-- masterFIP core --
---------------------------------------------------------------------------------------------------
cmp_masterFIP_core : fmc_masterFIP_core
generic map
(g_span => 32,
g_width => 32,
values_for_simul => FALSE)
port map
(clk_i => clk_40m_sys,
(clk_i => clk_100m_sys,
rst_i => rst_sys,
-- Bus speed
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- Bus termination
bus_term_en_n_o => bus_term_en_n_o,
-- FielDrive
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
......@@ -453,11 +441,6 @@ begin
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txena_o => fd_txena,
-- Bus bit rate
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- Bus termination
bus_term_en_n_o => bus_term_en_n_o,
-- External synchronisation pulse transceiver
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_dir_o => ext_sync_dir_o,
......@@ -482,45 +465,44 @@ begin
wb_stall_o => cnx_master_in(c_WB_SLAVE_MASTERFIP).stall,
-- Aux
aux_o => aux);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_MASTERFIP).err <= '0';
cnx_master_in(c_WB_SLAVE_MASTERFIP).rty <= '0';
cnx_master_in(c_WB_SLAVE_MASTERFIP).int <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
fd_txena_o <= fd_txena;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- LEDs font panel
-- led_tx_err_n_o <= fd_txer_i;
-- led_tx_act_n_o <= fd_txena;
-- led_rx_err_n_o <= rx_err;
-- led_rx_act_n_o <= rx_act;
led_tx_err_n_o <= fd_txer_i;
led_tx_act_n_o <= fd_txena;
led_rx_err_n_o <= rx_err;
led_rx_act_n_o <= rx_act;
-- cmp_rx_err_extend_p : gc_extend_pulse
-- generic map (
-- g_width => 50000)
-- port map (
-- clk_i => clk_40m_sys,
-- rst_n_i => rst_sys_n,
-- pulse_i => aux(0),
-- extended_o => rx_err);
-- cmp_rx_act_extend_p : gc_extend_pulse
-- generic map (
-- g_width => 50000)
-- port map (
-- clk_i => clk_40m_sys,
-- rst_n_i => rst_sys_n,
-- pulse_i => aux(1),
-- extended_o => rx_act);
led_tx_err_n_o <= aux(5);
led_tx_act_n_o <= aux(0);
led_rx_err_n_o <= aux(2);
led_rx_act_n_o <= aux(6);
cmp_rx_err_extend_p: gc_extend_pulse
generic map (g_width => 50000)
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_sys_n,
pulse_i => aux(0),
extended_o => rx_err);
cmp_rx_act_extend_p: gc_extend_pulse
generic map (g_width => 50000)
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_sys_n,
pulse_i => aux(1),
extended_o => rx_act);
---------------------------------------------------------------------------------------------------
-- Carrier 1-wire MASTER DS18B20 (thermometer + unique ID) --
-- SPEC 1-wire --
---------------------------------------------------------------------------------------------------
cmp_carrier_onewire : xwb_onewire_master
generic map
(g_interface_mode => CLASSIC,
......@@ -529,7 +511,7 @@ begin
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0")
port map
(clk_sys_i => clk_40m_sys,
(clk_sys_i => clk_100m_sys,
rst_n_i => rst_sys_n,
slave_i => cnx_master_out(c_WB_SLAVE_SPEC_ONEWIRE),
slave_o => cnx_master_in(c_WB_SLAVE_SPEC_ONEWIRE),
......@@ -546,12 +528,13 @@ begin
---------------------------------------------------------------------------------------------------
-- Carrier CSR information --
---------------------------------------------------------------------------------------------------
-- Information on carrier type, mezzanine presence, pcb version
cmp_carrier_csr : carrier_info
port map
(rst_n_i => rst_sys_n,
clk_sys_i => clk_40m_sys,
clk_sys_i => clk_100m_sys,
wb_adr_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_SPEC_INFO).dat,
......@@ -577,6 +560,7 @@ begin
carrier_info_rst_fmc0_n_i => '1',
carrier_info_rst_fmc0_n_load_o => open,
carrier_info_rst_reserved_o => open);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
......@@ -587,36 +571,35 @@ begin
---------------------------------------------------------------------------------------------------
-- SPEC LEDs --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
clk_40m_sys_drive_led : process (clk_40m_sys)
led_clk_100m_sys: process (clk_100m_sys)
begin
if rising_edge(clk_40m_sys) then
if rising_edge(clk_100m_sys) then
if(rst_sys_n = '0') then
led_clk_40m_aux <= "01111111";
led_clk_40m_divider <= (others => '0');
led_clk_100m_aux <= "01111111";
led_clk_100m_divider <= (others => '0');
else
led_clk_40m_divider <= led_clk_40m_divider+ 1;
if(led_clk_40m_divider = 0) then
led_clk_40m_aux <= led_clk_40m_aux(6 downto 0) & led_clk_40m_aux(7);
led_clk_100m_divider <= led_clk_100m_divider+ 1;
if(led_clk_100m_divider = 0) then
led_clk_100m_aux <= led_clk_100m_aux(6 downto 0) & led_clk_100m_aux(7);
end if;
end if;
end if;
end process;
-- -- -- -- --
led_green_o <= led_clk_40m_aux(0);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
led_green_o <= led_clk_100m_aux(0);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
spec_red_led: gc_extend_pulse
generic map
(g_width => 5000000)
port map
(clk_i => clk_40m_sys,
(clk_i => clk_100m_sys,
rst_n_i => rst_sys_n,
pulse_i => (aux(0)),
extended_o => led_red);
-- -- -- -- -- -- --
led_red_o <= led_red;
extended_o => led_red_o);
end rtl;
......
top/spec/synthesis_descriptor.vhd
View file @ d30c6031
......@@ -42,16 +42,16 @@ package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "masterFIP_tdc ",
syn_module_name => "spec_masterFIP ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000134",
syn_date => x"20140731",
syn_tool_version => x"00000147",
syn_date => x"20160128",
syn_username => "egousiou ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "http://svn.ohwr.org/masterFIP "
repo_url => "http://svn.ohwr.org/projects/masterFIP "
);
end package synthesis_descriptor;
top/spec_wrnode/spec_top.vhd
View file @ d30c6031
......@@ -376,14 +376,14 @@ begin
end if;
end process;
-- -- -- -- -- --
led_tx_err_n_o <= led_clk_40m_aux(0);
led_tx_act_n_o <= aux(3);
--led_tx_err_n_o <= aux(5);
led_rx_err_n_o <= aux(2);
led_rx_act_n_o <= aux(6);
led_out_of_sync_n_o <= aux(7);
led_sync_n_o <= aux(0);
-- led_tx_err_n_o <= led_clk_40m_aux(0);
led_tx_act_n_o <= aux(0); -- R5
led_tx_err_n_o <= aux(1); -- R8
led_rx_act_n_o <= aux(2); -- R6
led_rx_err_n_o <= aux(3); -- R9
led_out_of_sync_n_o <= aux(4); -- R7
led_sync_n_o <= aux(5); -- R2
......
top/spec_wrnode/synthesis_descriptor.vhd
View file @ d30c6031
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SVEC (Simple VME FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2014-03-18
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SVEC carrier.
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
......@@ -42,16 +42,16 @@ package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec-wrnode-demo",
syn_module_name => "masterFIP_MT ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20150327",
syn_username => "twlostow ");
syn_date => x"20160128",
syn_username => "egousiou ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/wr-node-core "
repo_url => "http://svn.ohwr.org/projects/masterFIP "
);
end package synthesis_descriptor;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment