cleanup

e149a38c · Evangelia Gousiou · ab937ea1 · ab937ea1 · e149a38c · e149a38c
Commit e149a38c authored Jul 17, 2015 by Evangelia Gousiou
31 changed files
--- a/rtl/data_engine.vhd
+++ b/rtl/data_engine.vhd
--- a/rtl/fmc_masterFIP_core.vhd
+++ b/rtl/fmc_masterFIP_core.vhd
--- a/rtl/fmc_masterFIP_mezzanine.vhd
+++ b/rtl/fmc_masterFIP_mezzanine.vhd
--- a/rtl/fmc_masterfip_csr.vhd
+++ b/rtl/fmc_masterfip_csr.vhd
--- a/rtl/tdc_eic.vhd
+++ b/rtl/tdc_eic.vhd
 ---------------------------------------------------------------------------------------
-- Title          : Wishbone slave core for TDC EIC
+-- Title          : Wishbone slave core for masterFIP EIC
 ---------------------------------------------------------------------------------------
-- File           : output.vhd
-- Author         : auto-generated by wbgen2 from tdc_eic.wb
-- Created        : 01/21/14 15:13:26
+-- File           : fmc_masterfip_eic.vhd
+-- Author         : auto-generated by wbgen2 from fmc_masterfip_eic.wb
+-- Created        : 07/17/15 11:52:38
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc_eic.wb
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_eic.wb
 -- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
 ---------------------------------------------------------------------------------------

@@ -15,7 +15,7 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use work.wbgen2_pkg.all;

-entity tdc_eic is
+entity fmc_masterfip_eic is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
@@ -29,24 +29,28 @@ entity tdc_eic is
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    wb_int_o                                 : out    std_logic;
-    irq_tdc_tstamps_i                        : in     std_logic;
-    irq_tdc_time_i                           : in     std_logic;
-    irq_tdc_acam_err_i                       : in     std_logic
+    irq_macrocy_start_i                      : in     std_logic;
+    irq_silen_time_expire_i                  : in     std_logic;
+    irq_turnar_time_expire_i                 : in     std_logic;
+    irq_tx_completed_i                       : in     std_logic;
+    irq_rx_fss_ok_i                          : in     std_logic;
+    irq_rx_frame_ok_i                        : in     std_logic;
+    irq_rx_crc_wrong_i                       : in     std_logic
  );
-end tdc_eic;
+end fmc_masterfip_eic;

-architecture syn of tdc_eic is
+architecture syn of fmc_masterfip_eic is

-signal eic_idr_int                              : std_logic_vector(2 downto 0);
+signal eic_idr_int                              : std_logic_vector(6 downto 0);
 signal eic_idr_write_int                        : std_logic      ;
-signal eic_ier_int                              : std_logic_vector(2 downto 0);
+signal eic_ier_int                              : std_logic_vector(6 downto 0);
 signal eic_ier_write_int                        : std_logic      ;
-signal eic_imr_int                              : std_logic_vector(2 downto 0);
-signal eic_isr_clear_int                        : std_logic_vector(2 downto 0);
-signal eic_isr_status_int                       : std_logic_vector(2 downto 0);
-signal eic_irq_ack_int                          : std_logic_vector(2 downto 0);
+signal eic_imr_int                              : std_logic_vector(6 downto 0);
+signal eic_isr_clear_int                        : std_logic_vector(6 downto 0);
+signal eic_isr_status_int                       : std_logic_vector(6 downto 0);
+signal eic_irq_ack_int                          : std_logic_vector(6 downto 0);
 signal eic_isr_write_int                        : std_logic      ;
-signal irq_inputs_vector_int                    : std_logic_vector(2 downto 0);
+signal irq_inputs_vector_int                    : std_logic_vector(6 downto 0);
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
 signal rddata_reg                               : std_logic_vector(31 downto 0);
 signal wrdata_reg                               : std_logic_vector(31 downto 0);
@@ -171,11 +175,7 @@ begin
          when "10" => 
            if (wb_we_i = '1') then
            end if;
-            rddata_reg(2 downto 0) <= eic_imr_int(2 downto 0);
-            rddata_reg(3) <= 'X';
-            rddata_reg(4) <= 'X';
-            rddata_reg(5) <= 'X';
-            rddata_reg(6) <= 'X';
+            rddata_reg(6 downto 0) <= eic_imr_int(6 downto 0);
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
@@ -207,11 +207,7 @@ begin
            if (wb_we_i = '1') then
              eic_isr_write_int <= '1';
            end if;
-            rddata_reg(2 downto 0) <= eic_isr_status_int(2 downto 0);
-            rddata_reg(3) <= 'X';
-            rddata_reg(4) <= 'X';
-            rddata_reg(5) <= 'X';
-            rddata_reg(6) <= 'X';
+            rddata_reg(6 downto 0) <= eic_isr_status_int(6 downto 0);
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
@@ -253,15 +249,15 @@ begin
 -- Drive the data output bus
  wb_dat_o <= rddata_reg;
 -- extra code for reg/fifo/mem: Interrupt disable register
-  eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
+  eic_idr_int(6 downto 0) <= wrdata_reg(6 downto 0);
 -- extra code for reg/fifo/mem: Interrupt enable register
-  eic_ier_int(2 downto 0) <= wrdata_reg(2 downto 0);
+  eic_ier_int(6 downto 0) <= wrdata_reg(6 downto 0);
 -- extra code for reg/fifo/mem: Interrupt status register
-  eic_isr_clear_int(2 downto 0) <= wrdata_reg(2 downto 0);
+  eic_isr_clear_int(6 downto 0) <= wrdata_reg(6 downto 0);
 -- extra code for reg/fifo/mem: IRQ_CONTROLLER
  eic_irq_controller_inst : wbgen2_eic
    generic map (
-      g_num_interrupts     => 3,
+      g_num_interrupts     => 7,
      g_irq00_mode         => 0,
      g_irq01_mode         => 0,
      g_irq02_mode         => 0,
@@ -311,9 +307,13 @@ begin
      wb_irq_o             => wb_int_o
    );
  
-  irq_inputs_vector_int(0) <= irq_tdc_tstamps_i;
-  irq_inputs_vector_int(1) <= irq_tdc_time_i;
-  irq_inputs_vector_int(2) <= irq_tdc_acam_err_i;
+  irq_inputs_vector_int(0) <= irq_macrocy_start_i;
+  irq_inputs_vector_int(1) <= irq_silen_time_expire_i;
+  irq_inputs_vector_int(2) <= irq_turnar_time_expire_i;
+  irq_inputs_vector_int(3) <= irq_tx_completed_i;
+  irq_inputs_vector_int(4) <= irq_rx_fss_ok_i;
+  irq_inputs_vector_int(5) <= irq_rx_frame_ok_i;
+  irq_inputs_vector_int(6) <= irq_rx_crc_wrong_i;
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
 -- ACK signal generation. Just pass the LSB of ACK counter.

--- a/rtl/wf_crc.vhd
+++ b/rtl/wf_crc.vhd
@@ -61,7 +61,7 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
 use IEEE.NUMERIC_STD.all;    -- conversion functions
 -- Specific library
 library work;
-use work.masterFIP_pkg.all;     -- definitions of types, constants, entities
+use work.WF_PACKAGE.all;     -- definitions of types, constants, entities


 --=================================================================================================
@@ -73,7 +73,7 @@ entity wf_crc is port(
    uclk_i             : in std_logic;              -- 40 MHz clock

    -- Signal from the wf_reset_unit
-    core_rst_i         : in std_logic;              -- nanoFIP internal reset
+    nfip_rst_i         : in std_logic;              -- nanoFIP internal reset

    -- Signals from the wf_rx_deserializer/ wf_tx_serializer units
    data_bit_i         : in std_logic;              -- incoming data bit stream
@@ -130,7 +130,7 @@ begin
  begin
    if rising_edge (uclk_i) then

-      if core_rst_i = '1' then
+      if nfip_rst_i = '1' then
        s_q     <= (others => '0');

      else

--- a/rtl/wf_decr_counter.vhd
+++ b/rtl/wf_decr_counter.vhd
@@ -50,7 +50,7 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
 use IEEE.NUMERIC_STD.all;    -- conversion functions
 -- Specific library
 library work;
-use work.masterFIP_pkg.all;     -- definitions of types, constants, entities
+use work.WF_PACKAGE.all;     -- definitions of types, constants, entities


 --=================================================================================================

--- a/rtl/wf_incr_counter.vhd
+++ b/rtl/wf_incr_counter.vhd
@@ -48,7 +48,7 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
 use IEEE.NUMERIC_STD.all;    -- conversion functions
 -- Specific library
 library work;
-use work.masterFIP_pkg.all;     -- definitions of types, constants, entities
+use work.WF_PACKAGE.all;     -- definitions of types, constants, entities


 --=================================================================================================

--- a/rtl/from_nanofip/wf_package.vhd
+++ b/rtl/from_nanofip/wf_package.vhd
--- a/rtl/wf_rx_deglitcher.vhd
+++ b/rtl/wf_rx_deglitcher.vhd
@@ -53,7 +53,7 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
 use IEEE.NUMERIC_STD.all;    -- conversion functions
 -- Specific library
 library work;
-use work.masterFIP_pkg.all;     -- definitions of types, constants, entities
+use work.WF_PACKAGE.all;     -- definitions of types, constants, entities


 --=================================================================================================
@@ -66,7 +66,7 @@ entity wf_rx_deglitcher is port(
    uclk_i                 : in std_logic;  -- 40 MHz clock

    -- Signal from the wf_reset_unit
-    core_rst_i             : in std_logic;  -- nanoFIP internal reset
+    nfip_rst_i             : in std_logic;  -- nanoFIP internal reset

    -- nanoFIP FIELDRIVE (synchronized with uclk)
    fd_rxd_a_i             : in std_logic;  -- receiver data
@@ -109,7 +109,7 @@ begin
  FD_RXD_synchronizer: process (uclk_i)
  begin
    if rising_edge (uclk_i) then
-      if core_rst_i = '1' then
+      if nfip_rst_i = '1' then
       s_fd_rxd_synch <= (others => '0');

      else
@@ -132,7 +132,7 @@ begin
  FD_RXD_deglitcher: process (uclk_i)
  begin
    if rising_edge (uclk_i) then
-      if core_rst_i = '1' then
+      if nfip_rst_i = '1' then
        s_filt_c          <= to_unsigned (c_DEGLITCH_THRESHOLD, s_filt_c'length) srl 1;-- middle value
        s_fd_rxd_filt     <= '0';
        s_fd_rxd_filt_d1  <= '0';

--- a/rtl/wf_rx_deserializer.vhd
+++ b/rtl/wf_rx_deserializer.vhd
@@ -113,8 +113,7 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
 use IEEE.NUMERIC_STD.all;    -- conversion functions
 -- Specific library
 library work;
-use work.masterFIP_pkg.all;     -- definitions of types, constants, entities
-
+use work.wf_package.all;     -- definitions of types, constants, entities

 --=================================================================================================
 --                           Entity declaration for wf_rx_deserializer
@@ -126,7 +125,7 @@ entity wf_rx_deserializer is port(
    uclk_i               : in std_logic; -- 40 MHz clock

    -- Signal from the wf_reset_unit
-    core_rst_i           : in std_logic; -- nanoFIP internal reset
+    nfip_rst_i           : in std_logic; -- nanoFIP internal reset

    -- Signal from the wf_engine_control unit
    rx_rst_i             : in std_logic; -- reset during production or
@@ -149,7 +148,7 @@ entity wf_rx_deserializer is port(

  -- OUTPUTS
    -- Signals to the wf_consumption and the wf_engine_control units
-    tx_byte_o               : out std_logic_vector (7 downto 0) ;   -- retrieved data byte
+    byte_o               : out std_logic_vector (7 downto 0) ;   -- retrieved data byte
    byte_ready_p_o       : out std_logic; -- pulse indicating a new retrieved data byte
    fss_crc_fes_ok_p_o   : out std_logic; -- indication of a frame (ID_DAT or RP_DAT) with
                                          -- correct FSS, FES and CRC
@@ -218,7 +217,7 @@ begin
  Deserializer_FSM_Sync: process (uclk_i)
    begin
      if rising_edge (uclk_i) then
-        if core_rst_i = '1' or rx_rst_i = '1' or s_session_timedout = '1' then
+        if nfip_rst_i = '1' or rx_rst_i = '1' or s_session_timedout = '1' then
          rx_st <= IDLE;
        else
          rx_st <= nx_rx_st;
@@ -415,7 +414,7 @@ begin
  Append_Bit_To_Byte: process (uclk_i)
  begin
    if rising_edge (uclk_i) then
-      if core_rst_i = '1' then
+      if nfip_rst_i = '1' then
        s_byte_ready_p_d1       <= '0';
        s_sample_manch_bit_p_d1 <= '0';
        s_byte                  <= (others => '0');
@@ -447,7 +446,7 @@ begin
  generic map(g_counter_lgth => 4)
  port map(
    uclk_i            => uclk_i,
-    counter_rst_i     => core_rst_i,
+    counter_rst_i     => nfip_rst_i,
    counter_top_i     => s_manch_bit_index_top,
    counter_load_i    => s_manch_bit_index_load_p,
    counter_decr_i    => s_manch_bit_index_decr_p,
@@ -517,7 +516,7 @@ begin
  CRC_Verification : wf_crc
  port map(
    uclk_i             => uclk_i,
-    core_rst_i         => core_rst_i,
+    nfip_rst_i         => nfip_rst_i,
    start_crc_p_i      => s_receiving_fsd,
    data_bit_ready_p_i => s_write_bit_to_byte_p,
    data_bit_i         => fd_rxd_i,
@@ -535,7 +534,7 @@ begin
  CRC_OK_pulse_delay: process (uclk_i)
  begin
    if rising_edge (uclk_i) then
-      if core_rst_i = '1' or s_receiving_bytes = '0' then
+      if nfip_rst_i = '1' or s_receiving_bytes = '0' then
        s_CRC_ok_p_d       <= '0';
        s_CRC_ok_p_found   <= '0';
      else
@@ -571,7 +570,7 @@ begin
  generic map(g_counter_lgth => c_SESSION_TIMEOUT_C_LGTH)
  port map(
    uclk_i            => uclk_i,
-    counter_rst_i     => core_rst_i,
+    counter_rst_i     => nfip_rst_i,
    counter_top_i     => (others => '1'),
    counter_load_i    => s_idle,
    counter_decr_i    => '1', -- on each uclk tick
@@ -596,7 +595,7 @@ begin
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  -- output signals concurrent assignments :

-  tx_byte_o                    <= s_byte;
+  byte_o                    <= s_byte;
  byte_ready_p_o            <= s_byte_ready_p_d1;
  rx_osc_rst_o              <= s_idle;
  fss_received_p_o          <= s_receiving_fsd  and s_fsd_last_bit;

--- a/rtl/wf_rx_osc.vhd
+++ b/rtl/wf_rx_osc.vhd
@@ -85,7 +85,7 @@ entity wf_rx_osc is port(
    rate_i                  : in  std_logic_vector (1 downto 0); -- WorldFIP bit rate

    -- Signal from the wf_reset_unit
-    core_rst_i              : in std_logic;   -- nanoFIP internal reset
+    nfip_rst_i              : in std_logic;   -- nanoFIP internal reset

    -- Signal from the wf_deglitcher unit
    fd_rxd_edge_p_i         : in std_logic;   -- indication of an edge on fd_rxd
@@ -176,7 +176,7 @@ begin
    --                        if rx_osc_rst_i is active                     or
    --                        if an edge is detected in the expected window or
    --                        if it fills up
-    s_period_c_reinit <= core_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i)
+    s_period_c_reinit <= nfip_rst_i or rx_osc_rst_i or (s_signif_edge_window and fd_rxd_edge_p_i)
                        or s_period_c_is_full;


@@ -218,7 +218,7 @@ begin

  begin
    if rising_edge (uclk_i) then
-      if (core_rst_i = '1') then
+      if (nfip_rst_i = '1') then
        s_manch_clk                <= '0';
        s_bit_clk                  <= '0';
        s_bit_clk_d1               <= '0';

--- a/rtl/wf_tx_osc.vhd
+++ b/rtl/wf_tx_osc.vhd
@@ -63,7 +63,7 @@ use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
 use IEEE.NUMERIC_STD.all;    -- conversion functions
 -- Specific library
 library work;
-use work.masterFIP_pkg.all;     -- definitions of types, constants, entities
+use work.WF_PACKAGE.all;     -- definitions of types, constants, entities


 --=================================================================================================
@@ -78,7 +78,7 @@ entity wf_tx_osc is
    rate_i            : in std_logic_vector (1 downto 0); -- WorldFIP bit rate

    -- Signal from the wf_reset_unit
-    core_rst_i        : in std_logic;                 -- nanoFIP internal reset
+    nfip_rst_i        : in std_logic;                 -- nanoFIP internal reset

    -- Signals from the wf_engine_control
    tx_osc_rst_p_i    : in std_logic;                 -- transmitter timeout
@@ -142,10 +142,10 @@ begin
    ------------------------------------------

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  -- counter reinitialized : if the core_rst_i is active or
+  -- counter reinitialized : if the nfip_rst_i is active or
  --                         if the tx_osc_rst_p_i is active or
  --                         if it fills up
-  s_period_c_reinit <= core_rst_i or tx_osc_rst_p_i or s_period_c_is_full;
+  s_period_c_reinit <= nfip_rst_i or tx_osc_rst_p_i or s_period_c_is_full;



@@ -180,7 +180,7 @@ begin
  clk_Signals_Construction: process (uclk_i)
  begin
    if rising_edge (uclk_i) then
-      if (core_rst_i = '1') or (tx_osc_rst_p_i = '1') then
+      if (nfip_rst_i = '1') or (tx_osc_rst_p_i = '1') then
        s_tx_sched_p_buff <= (others => '0');
        s_tx_clk_d1       <= '0';
      else

--- a/rtl/wf_tx_serializer.vhd
+++ b/rtl/wf_tx_serializer.vhd
--- a/rtl/incr_counter.vhd
+++ b/rtl/incr_counter.vhd
 --_________________________________________________________________________________________________
 --                                                                                                |
--                                           |TDC core|                                           |
+--                                         |The nanoFIP|                                          |
 --                                                                                                |
 --                                         CERN,BE/CO-HT                                          |
 --________________________________________________________________________________________________|
@@ -11,24 +11,16 @@
 --                                                                                                |
 ---------------------------------------------------------------------------------------------------
 -- File         incr_counter.vhd                                                                  |
--                                                                                                |
-- Description  Stop counter. Configurable "counter_top_i" and "width".                           |
--				"Current count value" and "counting done" signals available.                      |
--				"Counting done" signal asserted simultaneous to"current count value=counter_top_i"|
--				Needs a rst_i to restart.                                                         |
--                                                                                                |
--                                                                                                |
-- Authors      Gonzalo Penacoba  (Gonzalo.Penacoba@cern.ch)                                      |
--              Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
-- Date         04/2012                                                                           |
-- Version      v0.11                                                                             |
-- Depends on                                                                                     |
--                                                                                                |
+-- Description  Increasing counter with synchronous reinitialise and increase enable              |
+-- Authors      Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)                             |
+--              Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)                                 |
+-- Date         01/2011                                                                           |
+-- Version      v0.011                                                                            |
+-- Depends on   -                                                                                 |
 ----------------                                                                                  |
 -- Last changes                                                                                   |
--     05/2011  v0.1  GP  First version                                                           |
--     04/2012  v0.11 EG  Revamping; Comments added, signals renamed                              |
--                                                                                                |
+--     10/2010  EG  v0.01   first version                                                         |
+--     01/2011  EG  v0.011  counter_full became a constant                                        |
 ---------------------------------------------------------------------------------------------------

 ---------------------------------------------------------------------------------------------------
@@ -47,81 +39,77 @@


 --=================================================================================================
--                                       Libraries & Packages
+--                                      Libraries & Packages
 --=================================================================================================

 -- Standard library
 library IEEE;
 use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
 use IEEE.NUMERIC_STD.all;    -- conversion functions
+-- Specific library
+library work;
+use work.masterFIP_pkg.all;     -- definitions of types, constants, entities


 --=================================================================================================
--                            Entity declaration for incr_counter
+--                           Entity declaration for incr_counter
 --=================================================================================================

 entity incr_counter is
-  generic
-    (width             : integer := 32);                        -- default size
-  port
+  generic(g_counter_lgth : natural := 4);                       -- default length
+  port(
  -- INPUTS
-     -- Signals from the clk_rst_manager
-    (clk_i             : in std_logic;
-     rst_i             : in std_logic;
+   -- nanoFIP User Interface general signal
+   clk_i            : in std_logic;                             -- 40 MHz clock
+
+   -- Signals from any unit
+   counter_incr_i    : in std_logic;                             -- increment enable
+   counter_reinit_i  : in std_logic;                             -- reinitializes counter to 0

-     -- Signals from any unit
-     counter_top_i     : in std_logic_vector(width-1 downto 0); -- max value to be counted; when reached
-                                                                -- counter stays at it, until a reset
-     counter_incr_en_i : in std_logic;                          -- enables counting

-  -- OUTPUTS
-     -- Signals to any unit
-     counter_o         : out std_logic_vector(width-1 downto 0);
-     counter_is_full_o : out std_logic);                        -- counter reahed counter_top_i value
+  -- OUTPUT
+    -- Signal to any unit
+   counter_o         : out std_logic_vector (g_counter_lgth-1 downto 0); -- counter
+   counter_is_full_o : out std_logic);                           -- counter full indication
+                                                                 -- (all bits to '1')
+end entity incr_counter;

-  end incr_counter;

 --=================================================================================================
 --                                    architecture declaration
 --=================================================================================================
 architecture rtl of incr_counter is

-  constant zeroes : unsigned(width-1 downto 0) := (others=>'0');
-  signal counter  : unsigned(width-1 downto 0) := (others=>'0'); -- init to avoid sim warnings
+constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
+signal   s_counter      : unsigned (g_counter_lgth-1 downto 0);


 --=================================================================================================
 --                                       architecture begin
 --=================================================================================================
 begin
-	
-  incr_counting: process (clk_i)
-  begin
-    if rising_edge (clk_i) then
-      if rst_i = '1' then
-        counter_is_full_o   <= '0';
-        counter             <= zeroes;

-      elsif counter = unsigned (counter_top_i) then
-        counter_is_full_o   <= '1';
-        counter             <= unsigned (counter_top_i);

-      elsif counter_incr_en_i ='1' then
+---------------------------------------------------------------------------------------------------
+  -- Synchronous process Incr_Counter

-        if counter = unsigned(counter_top_i) - "1" then
-          counter_is_full_o <= '1';
-          counter           <= counter + "1";
-        else
-          counter_is_full_o <= '0';
-          counter           <= counter + "1";
-        end if;
+  Incr_Counter: process (clk_i)
+  begin
+    if rising_edge (clk_i) then
+      if counter_reinit_i = '1' then
+        s_counter   <= (others => '0');
+
+      elsif counter_incr_i = '1' then
+        s_counter   <= s_counter + 1;

      end if;
    end if;
  end process;

-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  counter_o                 <= std_logic_vector(counter);
+ --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+
+  counter_o         <= std_logic_vector(s_counter);
+  counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0';


 end architecture rtl;
@@ -130,4 +118,4 @@ end architecture rtl;
 --=================================================================================================
 ---------------------------------------------------------------------------------------------------
 --                                      E N D   O F   F I L E
---------------------------------------------------------------------------------------------------
+---------------------------------------------------------------------------------------------------
\ No newline at end of file
--- a/rtl/masterFIP_pkg.vhd
+++ b/rtl/masterFIP_pkg.vhd
--- a/rtl/reg_ctrl.vhd
+++ b/rtl/reg_ctrl.vhd
--- a/rtl/wbgen/fmc_masterfip_eic.wb
+++ b/rtl/wbgen/fmc_masterfip_eic.wb
--- a/rtl/wbgen/masterfip.wb
+++ b/rtl/wbgen/masterfip.wb
--- a/rtl/wbgen/tdc_eic.wb
+++ b/rtl/wbgen/tdc_eic.wb
--- a/rtl/wf_cons_bytes_processor.vhd
+++ b/rtl/wf_cons_bytes_processor.vhd
--- a/rtl/wf_cons_outcome.vhd
+++ b/rtl/wf_cons_outcome.vhd
--- a/rtl/wf_fd_receiver.vhd
+++ b/rtl/wf_fd_receiver.vhd
--- a/rtl/wf_fd_transmitter.vhd
+++ b/rtl/wf_fd_transmitter.vhd
--- a/rtl/wf_prod_bytes_retriever.vhd
+++ b/rtl/wf_prod_bytes_retriever.vhd
--- a/rtl/wf_prod_data_lgth_calc.vhd
+++ b/rtl/wf_prod_data_lgth_calc.vhd
--- a/sim/spec/data_vectors/masterFIP_test.vec
+++ b/sim/spec/data_vectors/masterFIP_test.vec
--- a/sim/spec/testbench/gnum_model/cmd_router.vhd
+++ b/sim/spec/testbench/gnum_model/cmd_router.vhd
--- a/syn/spec/no_wrabbit/data_vectors/masterFIP_test.vec
+++ b/syn/spec/no_wrabbit/data_vectors/masterFIP_test.vec
--- a/syn/spec/no_wrabbit/spec_masterFIP.xise
+++ b/syn/spec/no_wrabbit/spec_masterFIP.xise
--- a/top/spec/no_wrabbit/spec_masterFIP.vhd
+++ b/top/spec/no_wrabbit/spec_masterFIP.vhd