Skip to content

M
MasterFIP - Gateware
Commit fd652d45 authored by Evangelia Gousiou's avatar Evangelia Gousiou
Browse files
Options

added more bits to tx and rx bytes counters so as to be compatible with the PTS… 

added more bits to tx and rx bytes counters so as to be compatible with the PTS that needs to send 1024 bytes.
parent 38045178
Hide whitespace changes
Inline Side-by-side
Showing with 8363 additions and 1556 deletions
rtl/fmc_masterFIP_core.vhd
View file @ fd652d45
......@@ -491,7 +491,7 @@ begin
speed_i => speed,
rx_d_a_i => fd_rxd_a_i,
rx_byte_index_o => rx_byte_index, -- current byte index
rx_word_index_o => reg_to_mt.rx_stat_curr_word_indx_i,
rx_word_index_o => reg_to_mt.rx_stat_curr_word_indx_i(C_FRAME_WORDS_CNT_LGTH-1 downto 0),
rx_ctrl_byte_o => reg_to_mt.rx_payld_ctrl_i,
rx_frame_o => rx_frame,
rx_fss_crc_fes_ok_p_o => rx_frame_ok_p,
......@@ -520,7 +520,7 @@ begin
else
if rx_frame_ok_p = '1' then
reg_to_mt.rx_stat_frame_ok_i <= rx_frame_ok_p;
reg_to_mt.rx_stat_bytes_num_i <= rx_byte_index - 3; -- data payload, without FSS, CTRL,
reg_to_mt.rx_stat_bytes_num_i(C_FRAME_BYTES_CNT_LGTH-1 downto 0) <= rx_byte_index - 3; -- data payload, without FSS, CTRL,
end if; -- CRC, FES
end if;
end if;
......@@ -576,11 +576,12 @@ begin
(clk_i => clk_i,
rst_i => tx_rst,
speed_i => speed,
tx_bytes_num_i => reg_from_mt.tx_ctrl_bytes_num_o,-- num of bytes to serialize; sampled upon tx_start_p
tx_bytes_num_i => reg_from_mt.tx_ctrl_bytes_num_o(C_FRAME_BYTES_CNT_LGTH-1 downto 0),-- num of bytes to serialize; sampled upon tx_start_p
tx_start_p_i => reg_from_mt.tx_ctrl_start_o, -- monostable, 1-clk-tick-long pulse
tx_frame_i => tx_frame,
tx_ctrl_byte_i => reg_from_mt.tx_payld_ctrl_o,
tx_byte_index_o => reg_to_mt.tx_stat_curr_byte_indx_i,-- indx of current byte being serialized,
tx_byte_index_o => reg_to_mt.tx_stat_curr_byte_indx_i(C_FRAME_BYTES_CNT_LGTH-1 downto 0),
-- indx of current byte being serialized,
-- counting starts from 0 (indx 0 is
-- the Control byte) up to 262 bytes
tx_end_p_o => tx_completed_p,
......
rtl/masterfip_wbgen2_csr.vhd
View file @ fd652d45
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_csr.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 04/12/17 12:25:04
-- Created : 04/21/17 11:57:29
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -67,7 +67,7 @@ signal masterfip_tx_ctrl_rst_dly0 : std_logic ;
signal masterfip_tx_ctrl_rst_int : std_logic ;
signal masterfip_tx_ctrl_start_dly0 : std_logic ;
signal masterfip_tx_ctrl_start_int : std_logic ;
signal masterfip_tx_ctrl_bytes_num_int : std_logic_vector(8 downto 0);
signal masterfip_tx_ctrl_bytes_num_int : std_logic_vector(15 downto 0);
signal masterfip_rx_ctrl_rst_dly0 : std_logic ;
signal masterfip_rx_ctrl_rst_int : std_logic ;
signal masterfip_tx_payld_ctrl_int : std_logic_vector(7 downto 0);
......@@ -188,7 +188,7 @@ begin
masterfip_silen_start_int <= '0';
masterfip_tx_ctrl_rst_int <= '0';
masterfip_tx_ctrl_start_int <= '0';
masterfip_tx_ctrl_bytes_num_int <= "000000000";
masterfip_tx_ctrl_bytes_num_int <= "0000000000000000";
masterfip_rx_ctrl_rst_int <= '0';
masterfip_tx_payld_ctrl_int <= "00000000";
masterfip_tx_payld_reg1_int <= "00000000000000000000000000000000";
......@@ -523,24 +523,17 @@ begin
if (wb_we_i = '1') then
masterfip_tx_ctrl_rst_int <= wrdata_reg(0);
masterfip_tx_ctrl_start_int <= wrdata_reg(1);
masterfip_tx_ctrl_bytes_num_int <= wrdata_reg(16 downto 8);
masterfip_tx_ctrl_bytes_num_int <= wrdata_reg(23 downto 8);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(16 downto 8) <= masterfip_tx_ctrl_bytes_num_int;
rddata_reg(23 downto 8) <= masterfip_tx_ctrl_bytes_num_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......@@ -556,7 +549,7 @@ begin
end if;
rddata_reg(0) <= regs_i.tx_stat_stop_i;
rddata_reg(8) <= regs_i.tx_stat_ena_i;
rddata_reg(17 downto 9) <= regs_i.tx_stat_curr_byte_indx_i;
rddata_reg(31 downto 16) <= regs_i.tx_stat_curr_byte_indx_i;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
......@@ -564,20 +557,13 @@ begin
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010010" =>
......@@ -679,19 +665,12 @@ begin
rddata_reg(0) <= regs_i.rx_stat_pream_ok_i;
rddata_reg(1) <= regs_i.rx_stat_frame_ok_i;
rddata_reg(2) <= regs_i.rx_stat_frame_crc_err_i;
rddata_reg(16 downto 8) <= regs_i.rx_stat_bytes_num_i;
rddata_reg(23 downto 8) <= regs_i.rx_stat_bytes_num_i;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......@@ -705,8 +684,7 @@ begin
when "00011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(6 downto 0) <= regs_i.rx_stat_curr_word_indx_i;
rddata_reg(7) <= 'X';
rddata_reg(7 downto 0) <= regs_i.rx_stat_curr_word_indx_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
......
rtl/masterfip_wbgen2_pkg.vhd
View file @ fd652d45
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 04/12/17 12:25:04
-- Created : 04/21/17 11:57:29
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -31,7 +31,7 @@ package masterfip_wbgen2_pkg is
silen_time_cnt_i : std_logic_vector(30 downto 0);
tx_stat_stop_i : std_logic;
tx_stat_ena_i : std_logic;
tx_stat_curr_byte_indx_i : std_logic_vector(8 downto 0);
tx_stat_curr_byte_indx_i : std_logic_vector(15 downto 0);
fd_wdg_i : std_logic;
fd_cd_i : std_logic;
fd_wdg_tstamp_i : std_logic_vector(31 downto 0);
......@@ -40,8 +40,8 @@ package masterfip_wbgen2_pkg is
rx_stat_pream_ok_i : std_logic;
rx_stat_frame_ok_i : std_logic;
rx_stat_frame_crc_err_i : std_logic;
rx_stat_bytes_num_i : std_logic_vector(8 downto 0);
rx_stat_curr_word_indx_i : std_logic_vector(6 downto 0);
rx_stat_bytes_num_i : std_logic_vector(15 downto 0);
rx_stat_curr_word_indx_i : std_logic_vector(7 downto 0);
rx_stat_crc_err_cnt_i : std_logic_vector(31 downto 0);
rx_payld_ctrl_i : std_logic_vector(7 downto 0);
rx_payld_reg1_i : std_logic_vector(31 downto 0);
......@@ -233,7 +233,7 @@ package masterfip_wbgen2_pkg is
silen_start_o : std_logic;
tx_ctrl_rst_o : std_logic;
tx_ctrl_start_o : std_logic;
tx_ctrl_bytes_num_o : std_logic_vector(8 downto 0);
tx_ctrl_bytes_num_o : std_logic_vector(15 downto 0);
rx_ctrl_rst_o : std_logic;
tx_payld_ctrl_o : std_logic_vector(7 downto 0);
tx_payld_reg1_o : std_logic_vector(31 downto 0);
......
rtl/wbgen/build_from_wb.sh
View file @ fd652d45
#!/bin/bash
wbgen2 -V master_wbgen2_csr.vhd -H record -p master_wbgen2_pkg.vhd -s defines -C master_wbgen2_csr.h -D master_wbgen2_csr.html master_csr.wb
wbgen2 -V masterfip_wbgen2_csr.vhd -H record -p masterfip_wbgen2_pkg.vhd -s defines -C masterfip_wbgen2_csr.h -D masterfip_wbgen2_csr.html masterfip_csr.wb
echo ""
echo "Moving WB generated files to the following locations..."
......
rtl/wbgen/masterfip_csr.wb
View file @ fd652d45
......@@ -461,7 +461,7 @@ peripheral {
256 Data bytes, the number of bytes to serialize = 263 (Control byte+6 address bytes+256 Data bytes)";
prefix = "bytes_num";
type = SLV;
size = 9;
size = 16; -- under normal conditions the value should be max 262
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -505,7 +505,8 @@ peripheral {
and counts up to 262 for the max frame (counting stops before the CRC bytes)";
prefix = "curr_byte_indx";
type = SLV;
size = 9;
align = 8;
size = 16; -- under normal conditions the value should be max 262
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......@@ -664,7 +665,7 @@ peripheral {
OR upon a rx_ctrl_rst OR upon a rst_core).";
prefix = "bytes_num";
type = SLV;
size = 9;
size = 16; -- under normal conditions the value should be max 262
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
......@@ -686,7 +687,7 @@ peripheral {
The register keeps its value until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core).";
type = SLV;
size = 7;
size = 8; -- under normal conditions the value should be max 67
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......
rtl/wbgen/masterfip_wbgen2_csr.h
View file @ fd652d45
......@@ -3,7 +3,7 @@
* File : masterfip_wbgen2_csr.h
* Author : auto-generated by wbgen2 from masterfip_csr.wb
* Created : 04/12/17 12:25:05
* Created : 04/21/17 11:57:29
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -147,10 +147,10 @@
#define MASTERFIP_TX_CTRL_START WBGEN2_GEN_MASK(1, 1)
/* definitions for field: tx number of bytes in reg: tx ctrl */
#define MASTERFIP_TX_CTRL_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 9)
#define MASTERFIP_TX_CTRL_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MASTERFIP_TX_CTRL_BYTES_NUM_SHIFT 8
#define MASTERFIP_TX_CTRL_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 9)
#define MASTERFIP_TX_CTRL_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 9)
#define MASTERFIP_TX_CTRL_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MASTERFIP_TX_CTRL_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: tx status */
......@@ -161,10 +161,10 @@
#define MASTERFIP_TX_STAT_ENA WBGEN2_GEN_MASK(8, 1)
/* definitions for field: tx status current byte index in reg: tx status */
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_MASK WBGEN2_GEN_MASK(9, 9)
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_SHIFT 9
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_W(value) WBGEN2_GEN_WRITE(value, 9, 9)
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_R(reg) WBGEN2_GEN_READ(reg, 9, 9)
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_MASK WBGEN2_GEN_MASK(16, 16)
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_SHIFT 16
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: FielDrive wdgn, cdn */
......@@ -197,10 +197,10 @@
#define MASTERFIP_RX_STAT_FRAME_CRC_ERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: rx number of payload bytes in reg: rx status */
#define MASTERFIP_RX_STAT_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 9)
#define MASTERFIP_RX_STAT_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MASTERFIP_RX_STAT_BYTES_NUM_SHIFT 8
#define MASTERFIP_RX_STAT_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 9)
#define MASTERFIP_RX_STAT_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 9)
#define MASTERFIP_RX_STAT_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MASTERFIP_RX_STAT_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: rx current word index */
......
rtl/wbgen/masterfip_wbgen2_csr.html
View file @ fd652d45
......@@ -4089,7 +4089,7 @@ masterfip_tx_ctrl_start_o
</td>
<td class="td_pblock_right">
masterfip_tx_ctrl_bytes_num_o[8:0]
masterfip_tx_ctrl_bytes_num_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -4174,7 +4174,7 @@ masterfip_tx_stat_ena_i
</td>
<td class="td_pblock_right">
masterfip_tx_stat_curr_byte_indx_i[8:0]
masterfip_tx_stat_curr_byte_indx_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -4548,7 +4548,7 @@ masterfip_rx_stat_frame_crc_err_i
</td>
<td class="td_pblock_right">
masterfip_rx_stat_bytes_num_i[8:0]
masterfip_rx_stat_bytes_num_i[15:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -4599,7 +4599,7 @@ masterfip_rx_stat_bytes_num_i[8:0]
</td>
<td class="td_pblock_right">
masterfip_rx_stat_curr_word_indx_i[6:0]
masterfip_rx_stat_curr_word_indx_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -15910,29 +15910,29 @@ TX_CTRL
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
BYTES_NUM[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
BYTES_NUM[8:8]
<td >
</td>
</tr>
</table>
......@@ -16122,29 +16122,29 @@ TX_STAT
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
CURR_BYTE_INDX[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
</tr>
</table>
......@@ -16176,26 +16176,26 @@ TX_STAT
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
CURR_BYTE_INDX[7:0]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
CURR_BYTE_INDX[8:7]
<td >
</td>
<td >
......@@ -16230,29 +16230,29 @@ CURR_BYTE_INDX[8:7]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=7 class="td_field">
CURR_BYTE_INDX[6:0]
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ENA
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td class="td_unused">
-
</td>
<td >
<td style="border: solid 1px black;" colspan=1 class="td_field">
ENA
</td>
</tr>
</table>
......@@ -17739,29 +17739,29 @@ RX_STAT
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
BYTES_NUM[15:8]
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td class="td_unused">
-
<td >
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
BYTES_NUM[8:8]
<td >
</td>
</tr>
</table>
......@@ -18117,11 +18117,11 @@ RX_STAT_CURR_WORD_INDX
</td>
</tr>
<tr>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=8 class="td_field">
RX_STAT_CURR_WORD_INDX[7:0]
</td>
<td style="border: solid 1px black;" colspan=7 class="td_field">
RX_STAT_CURR_WORD_INDX[6:0]
<td >
</td>
<td >
......
syn/spec/spec_masterfip_mt.par
View file @ fd652d45
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PCBE13457:: Thu Apr 20 22:28:26 2017
PCBE13457:: Fri Apr 21 12:05:42 2017
par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_map.ncd
spec_masterfip_mt.ncd spec_masterfip_mt.pcf
......@@ -20,7 +20,7 @@ WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your license support version '2017.04' for ISE expires in 10 days after which you will not qualify
WARNING:Security:42 - Your license support version '2017.04' for ISE expires in 9 days after which you will not qualify
for Xilinx software updates or new releases.
----------------------------------------------------------------------
......@@ -36,16 +36,16 @@ Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 12,622 out of 54,576 23%
Number used as Flip Flops: 12,620
Number of Slice Registers: 12,689 out of 54,576 23%
Number used as Flip Flops: 12,687
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 2
Number of Slice LUTs: 15,763 out of 27,288 57%
Number used as logic: 12,382 out of 27,288 45%
Number using O6 output only: 10,259
Number using O5 output only: 392
Number using O5 and O6: 1,731
Number of Slice LUTs: 16,786 out of 27,288 61%
Number used as logic: 13,604 out of 27,288 49%
Number using O6 output only: 11,485
Number using O5 output only: 396
Number using O5 and O6: 1,723
Number used as ROM: 0
Number used as Memory: 2,828 out of 6,408 44%
Number used as Dual Port RAM: 2,828
......@@ -54,18 +54,18 @@ Slice Logic Utilization:
Number using O5 and O6: 32
Number used as Single Port RAM: 0
Number used as Shift Register: 0
Number used exclusively as route-thrus: 553
Number with same-slice register load: 524
Number with same-slice carry load: 29
Number used exclusively as route-thrus: 354
Number with same-slice register load: 324
Number with same-slice carry load: 30
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 5,213 out of 6,822 76%
Number of MUXCYs used: 1,452 out of 13,644 10%
Number of LUT Flip Flop pairs used: 18,849
Number with an unused Flip Flop: 7,405 out of 18,849 39%
Number with an unused LUT: 3,086 out of 18,849 16%
Number of fully used LUT-FF pairs: 8,358 out of 18,849 44%
Number of occupied Slices: 5,830 out of 6,822 85%
Number of MUXCYs used: 1,456 out of 13,644 10%
Number of LUT Flip Flop pairs used: 20,927
Number with an unused Flip Flop: 9,004 out of 20,927 43%
Number with an unused LUT: 4,141 out of 20,927 19%
Number of fully used LUT-FF pairs: 7,782 out of 20,927 37%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -136,324 +136,137 @@ WARNING:Par:288 - The signal fmc_prsnt_m2c_n_i_IBUF has no load. PAR will not a
WARNING:Par:288 - The signal l2p_rdy_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem7_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem8_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem44_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem5_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem30_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem3_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem25_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem15_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem26_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem24_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem12_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem23_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem18_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem43_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem4_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem29_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem13_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem11_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem15_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem16_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem27_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMB_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem25_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMC_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem26_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem18_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem17_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem11_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem29_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem30_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem32_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem27_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem28_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem23_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem21_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem19_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem17_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMB_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem19_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMC_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem2_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem3_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem31_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMB_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMC_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem24_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem22_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem4_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem43_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem21_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem44_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem20_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem7_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMB_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMC_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem31_RAMD_O
has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 110609 unrouted; REAL time: 20 secs
Phase 2 : 101920 unrouted; REAL time: 23 secs
Phase 3 : 51722 unrouted; REAL time: 1 mins 2 secs
Phase 4 : 52377 unrouted; (Setup:0, Hold:8043, Component Switching Limit:0) REAL time: 1 mins 12 secs
Updating file: spec_masterfip_mt.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:7336, Component Switching Limit:0) REAL time: 5 mins 24 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:7336, Component Switching Limit:0) REAL time: 5 mins 24 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:7336, Component Switching Limit:0) REAL time: 5 mins 24 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:7336, Component Switching Limit:0) REAL time: 5 mins 24 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 25 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 5 mins 30 secs
Total REAL time to Router completion: 5 mins 30 secs
Total CPU time to Router completion: 5 mins 39 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/clk_ | | | | | |
| sys | BUFGMUX_X2Y3| No | 4364 | 0.548 | 1.759 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
| _Core/sys_clk | BUFGMUX_X3Y13| No | 220 | 0.493 | 1.704 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
| _Core/io_clk | Local| | 41 | 0.064 | 1.562 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 6
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_pllout_clk_sys_0 = PER | SETUP | 0.034ns| 9.966ns| 0| 0
IOD TIMEGRP "cmp_mock_turtle_pllo | HOLD | 0.277ns| | 0| 0
ut_clk_sys_0" TS_clk_125m_pllref_n_i / 0. | | | | |
8 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | SETUP | 0.092ns| 4.908ns| 0| 0
24_Core_cmp_clk_in_rx_pllout_x1 = | HOLD | 0.037ns| | 0| 0
PERIOD TIMEGRP "cmp_mock_turtle_ | | | | |
gen_with_gennum_U_GN4124_Core_cmp_clk_in_ | | | | |
rx_pllout_x1" TS_cmp_mock_turtle_ | | | | |
gen_with_gennum_U_GN4124_Core_cmp_clk_in_ | | | | |
buf_P_clk PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
24_Core_cmp_clk_in_buf_P_clk = PERIOD | | | | |
TIMEGRP "cmp_mock_turtle_gen | | | | |
_with_gennum_U_GN4124_Core_cmp_clk_in_buf | | | | |
_P_clk" TS_U_Node_Template_U_GN41 | | | | |
24_Core_cmp_clk_in_P_clk HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_U_Node_Template_U_GN4124_Core_cmp_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
in_P_clk = PERIOD TIMEGRP "U_Node | | | | |
_Template/gen_with_gennum.U_GN4124_Core/c | | | | |
mp_clk_in/P_clk" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_p_i = PERIOD TIMEGRP " | MINLOWPULSE | 4.666ns| 3.334ns| 0| 0
clk_125m_pllref_p_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk_125m_pllref_n_i = PERIOD TIMEGRP " | MINLOWPULSE | 4.666ns| 3.334ns| 0| 0
clk_125m_pllref_n_i" 8 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_pllout_clk_sys = PERIO | MINPERIOD | 6.876ns| 3.124ns| 0| 0
D TIMEGRP "cmp_mock_turtle_pllout | | | | |
_clk_sys" TS_clk_125m_pllref_p_i / 0.8 HI | | | | |
GH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | N/A | N/A| N/A| N/A| N/A
24_Core_cmp_clk_in_rx_pllout_xs_int = | | | | |
PERIOD TIMEGRP "cmp_mock_tur | | | | |
tle_gen_with_gennum_U_GN4124_Core_cmp_clk | | | | |
_in_rx_pllout_xs_int" TS_cmp_mock | | | | |
_turtle_gen_with_gennum_U_GN4124_Core_cmp | | | | |
_clk_in_buf_P_clk / 2 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_clk_125m_pllref_p_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_125m_pllref_p_i | 8.000ns| 3.334ns| 2.499ns| 0| 0| 0| 0|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 3.124ns| N/A| 0| 0| 0| 0|
| sys | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_clk_125m_pllref_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_125m_pllref_n_i | 8.000ns| 3.334ns| 7.973ns| 0| 0| 0| 4834021|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 9.966ns| N/A| 0| 0| 4834021| 0|
| sys_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
Derived Constraints for TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_U_Node_Template_U_GN4124_Cor| 5.000ns| 0.925ns| 4.908ns| 0| 0| 0| 4827|
|e_cmp_clk_in_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_ge| 5.000ns| 2.800ns| 4.908ns| 0| 0| 0| 4827|
| nnum_U_GN4124_Core_cmp_clk_in_| | | | | | | |
| buf_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_xs_int | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 5.000ns| 4.908ns| N/A| 0| 0| 4827| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_x1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 71 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 5 mins 37 secs
Total CPU time to PAR completion: 5 mins 45 secs
Peak Memory Usage: 886 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 73
Number of info messages: 1
Writing design to file spec_masterfip_mt.ncd
Phase 1 : 118252 unrouted; REAL time: 20 secs
Phase 2 : 109492 unrouted; REAL time: 24 secs
Phase 3 : 54344 unrouted; REAL time: 1 mins 11 secs
PAR done!
Phase 4 : 66607 unrouted; (Setup:23002, Hold:2614, Component Switching Limit:0) REAL time: 2 mins 1 secs
syn/spec/spec_masterfip_mt.syr
View file @ fd652d45
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/spec/spec_masterfip_mt.twr
View file @ fd652d45
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/spec/spec_masterfip_mt_map.mrp
View file @ fd652d45
This source diff could not be displayed because it is too large. You can view the blob instead.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment