Create a new gateware recipe for the SPEC stress-test

parent e64bfd8f
SUMMARY = "Provides the FPGA bitstream for the SPEC stress-test design"
LICENSE = "GPL-2.0"
LIC_FILES_CHKSUM = "file://${COREBASE}/meta/files/common-licenses/GPL-2.0;md5=801f80980d171dd6425610833a22dbe6"
PR = "r0"
PV = "0.1"
# Patch the top Manifest.py to adapt the old WR-NIC repo to the new HDLMake format.
SRC_URI = "git://ohwr.org/fmc-projects/spec/spec-getting-started/spec-stress-test.git"
SRCREV = "b19cc278dbb3328abe323618f85febaf71e9fb4d"
S = "${WORKDIR}/git/hdl/spec/syn"
FILES_${PN} += "/lib/firmware/fmc"
# Update and init Git submodules to clone some dependent HDL libraries
do_fetch_extra(){
hdlmake fetch
}
addtask fetch_extra after do_unpack before do_patch
# Use HDLMake to analyze the project and generate the Makefile
do_configure() {
hdlmake
}
# Deploy the bitstream into the appropriated target folder
do_install() {
install -d ${D}/lib/firmware/fmc
install -m 0755 ${S}/spec_stress_test.bin ${D}/lib/firmware/fmc/spec_stress_test.bin
}
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