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Mock Turtle
Commit 569a7177 authored by Tristan Gingold's avatar Tristan Gingold
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Change again HMQ convention: IN/OUT are relative to the master. 

Remove unused MQ commands (enqueue, commit).
parent 9d299b10
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Showing with 102 additions and 102 deletions
hdl/rtl/mqueue/mt_mqueue_host.vhd
View file @ 569a7177
......@@ -46,8 +46,8 @@ entity mt_mqueue_host is
host_slave_i : in t_wishbone_slave_in;
host_slave_o : out t_wishbone_slave_out;
-- For HMQ, IN and OUT are always relative to the soft cpu.
-- So IN is from host to cpu, OUT is from cpu to host.
-- IN and OUT are relative to the cpu or soft-cpu.
-- So the OUT hmq of the host is linked to the IN hmq of the soft-cpu.
host_in_irq_o : out std_logic;
host_out_irq_o : out std_logic;
......@@ -112,8 +112,8 @@ begin -- arch
outb_i => host_outgoing_in(i),
outb_o => host_outgoing_out(i));
host_out_status (i) <= not outgoing_stat(i).empty;
cpu_out_status_o (i) <= not outgoing_stat(i).full;
host_in_status (i) <= not outgoing_stat(i).empty;
-- Host to CB direction (incoming slots)
U_In_SlotX : entity work.mt_mqueue_slot
......@@ -128,8 +128,8 @@ begin -- arch
outb_i => cpu_incoming_in(i),
outb_o => cpu_incoming_out(i));
host_in_status (i) <= not incoming_stat(i).full;
cpu_in_status_o (i) <= not incoming_stat(i).empty;
host_out_status (i) <= not incoming_stat(i).full;
end generate gen_slots;
host_out_status_o <= host_out_status;
......@@ -142,8 +142,8 @@ begin -- arch
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
incoming_status_i => incoming_stat,
outgoing_status_i => outgoing_stat,
incoming_status_i => outgoing_stat,
outgoing_status_i => incoming_stat,
incoming_o => host_incoming_in,
incoming_i => host_incoming_out,
outgoing_o => host_outgoing_in,
......
hdl/rtl/mqueue/mt_mqueue_pkg.vhd
View file @ 569a7177
......@@ -118,6 +118,7 @@ package mt_mqueue_pkg is
b"10_0000_0000_0000";
constant c_mqueue_command_claim : natural := 24;
constant c_mqueue_command_purge : natural := 25;
constant c_mqueue_command_ready : natural := 26;
constant c_mqueue_command_discard : natural := 27;
......@@ -128,12 +129,9 @@ package mt_mqueue_pkg is
-- No entry is used.
empty : std_logic;
commit_mask : std_logic;
end record t_slot_status_out;
constant c_dummy_status_out : t_slot_status_out := (
'0', '0', '0');
constant c_dummy_status_out : t_slot_status_out := ('0', '0');
type t_slot_bus_in_array is array(integer range <>) of t_slot_bus_in;
......
hdl/rtl/mqueue/mt_mqueue_remote.vhd
View file @ 569a7177
......@@ -110,10 +110,10 @@ begin -- rtl
clk_i => clk_i,
rst_n_i => rst_n_i,
stat_o => incoming_stat(i),
inb_i => cpu_incoming_in(i),
inb_o => cpu_incoming_out(i),
outb_i => ep_incoming_in(i),
outb_o => ep_incoming_out(i));
outb_i => cpu_incoming_in(i),
outb_o => cpu_incoming_out(i),
inb_i => ep_incoming_in(i),
inb_o => ep_incoming_out(i));
U_In_Rx : entity work.mt_rmq_rx
generic map (
......
hdl/rtl/mqueue/mt_mqueue_slot.vhd
View file @ 569a7177
......@@ -86,23 +86,23 @@ architecture arch of mt_mqueue_slot is
signal wr_state : t_wr_state;
signal rd_state : t_rd_state;
signal in_claim, in_purge, in_ready, in_enqueue, in_commit : std_logic;
signal in_claim, in_purge, in_ready : std_logic;
signal in_cmd_wr, in_stat_rd : std_logic;
signal out_cmd_wr, out_stat_rd : std_logic;
signal status : std_logic_vector(31 downto 0);
signal status : std_logic_vector(31 downto 0) := (others => '0');
signal out_discard, out_purge : std_logic;
signal q_read, q_write : std_logic;
signal n_words_last : std_logic_vector(7 downto 0);
signal purge_int : std_logic;
type t_reg_rd is (REG_RD_STATUS, REG_RD_HEADER, REG_RD_PAYLOAD);
signal in_reg_rd, out_reg_rd : t_reg_rd;
begin
-- Generate mem_we.
p_mem_write : process(inb_i, wr_state)
begin
if(wr_state = IGNORE_MESSAGE) then
......@@ -121,19 +121,13 @@ begin
mem_raddr <= rd_ptr & unsigned(outb_i.adr(g_CONFIG.width_bits+1 downto 2));
hdr_raddr <= rd_ptr & unsigned(outb_i.adr(g_CONFIG.header_bits+1 downto 2));
-- GCR status
status(0) <= full;
status(1) <= empty;
status(7 downto 2) <= std_logic_vector(to_unsigned(g_CONFIG.entries_bits, 6));
status(15 downto 8) <= std_logic_vector(occupied);
status(23 downto 16) <= n_words_last;
status(31 downto 28) <= std_logic_vector(to_unsigned(g_CONFIG.width_bits, 4));
in_claim <= in_cmd_wr and inb_i.dat(24);
in_purge <= in_cmd_wr and inb_i.dat(25);
in_ready <= in_cmd_wr and inb_i.dat(26);
in_enqueue <= in_cmd_wr and inb_i.dat(29);
in_commit <= in_cmd_wr and inb_i.dat(30);
in_cmd_wr <= '1' when (inb_i.sel = '1'
and inb_i.we = '1'
and inb_i.hdr_n = '0'
......@@ -145,8 +139,12 @@ begin
and outb_i.adr = c_mqueue_addr_command(12 downto 0))
else '0';
out_discard <= out_cmd_wr and outb_i.dat(27);
out_purge <= out_cmd_wr and outb_i.dat(25);
in_claim <= in_cmd_wr and inb_i.dat(c_mqueue_command_claim);
in_purge <= in_cmd_wr and inb_i.dat(c_mqueue_command_purge);
in_ready <= in_cmd_wr and inb_i.dat(c_mqueue_command_ready);
out_discard <= out_cmd_wr and outb_i.dat(c_mqueue_command_discard);
out_purge <= out_cmd_wr and outb_i.dat(c_mqueue_command_purge);
p_purge_int : process(clk_i)
begin
......@@ -236,14 +234,8 @@ begin
if rising_edge(clk_i) then
if rst_n_i = '0' or purge_int = '1' then
wr_state <= IDLE;
stat_o.commit_mask <= '0';
else
if in_commit = '1' or in_ready = '1' then
stat_o.commit_mask <= '1';
end if;
case wr_state is
when IDLE =>
if in_claim = '1' then
if full = '1' then
......@@ -261,14 +253,10 @@ begin
when ACCEPT_DATA =>
if in_ready = '1' then
wr_state <= READY_SEND;
elsif in_enqueue = '1' then
stat_o.commit_mask <= '0';
wr_state <= READY_SEND;
end if;
when READY_SEND =>
wr_state <= IDLE;
end case;
end if;
end if;
......@@ -278,9 +266,8 @@ begin
begin
if rising_edge(clk_i) then
if rst_n_i = '0' or purge_int = '1' then
rd_state <= IDLE;
rd_state <= IDLE;
else
case rd_state is
when IDLE =>
if empty = '0' then
......@@ -289,9 +276,8 @@ begin
when WAIT_DISCARD =>
if out_discard = '1' then
rd_state <= IDLE;
rd_state <= IDLE;
end if;
end case;
end if;
end if;
......@@ -308,11 +294,13 @@ begin
wr_ptr <= (others => '0');
occupied <= (others => '0');
else
if q_write = '1' and full = '0' then
if q_write = '1' then
assert full = '0' severity failure;
wr_ptr <= wr_ptr + 1;
end if;
if q_read = '1' and empty = '0' then
if q_read = '1' then
assert empty = '0' severity failure;
rd_ptr <= rd_ptr + 1;
end if;
......@@ -328,6 +316,5 @@ begin
full <= '1' when wr_ptr + 1 = rd_ptr else '0';
empty <= '1' when wr_ptr = rd_ptr else '0';
stat_o.full <= full;
stat_o.empty <= empty;
stat_o <= (full => full, empty => empty);
end architecture arch;
hdl/rtl/mqueue/mt_mqueue_wishbone_slave.vhd
View file @ 569a7177
......@@ -68,9 +68,10 @@ architecture arch of mt_mqueue_wishbone_slave is
signal wb_write : std_logic;
signal wb_read : std_logic;
signal gcr_rd_data : std_logic_vector(31 downto 0) := x"00000000";
signal gcr_rd_data : std_logic_vector(31 downto 0);
signal irq_config : t_mt_irq_config;
signal slot_status : std_logic_vector(31 downto 0) := (others => '0');
begin -- arch
......@@ -90,6 +91,8 @@ begin -- arch
dat => slave_i.dat,
we => wb_write,
wmask => slave_i.sel);
slot_status(i) <= not incoming_status_i(i).empty;
end generate gen_incoming_slots;
gen_outgoing_slots : for i in 0 to g_CONFIG.slot_count-1 generate
......@@ -100,6 +103,7 @@ begin -- arch
dat => slave_i.dat,
we => wb_write,
wmask => slave_i.sel);
slot_status(i+16) <= not outgoing_status_i(i).full;
end generate gen_outgoing_slots;
p_delay : process(clk_i)
......@@ -141,8 +145,8 @@ begin -- arch
if wb_write = '1' and gcr_sel = '1' then
case slave_i.adr(5 downto 2) is
when c_GCR_SLOT_IRQ_MASK =>
irq_config.mask_in <= slave_i.dat(23 downto 16);
irq_config.mask_out <= slave_i.dat(7 downto 0);
irq_config.mask_out <= slave_i.dat(23 downto 16);
irq_config.mask_in <= slave_i.dat(7 downto 0);
when c_GCR_SLOT_IRQ_COALESCE =>
irq_config.threshold <= slave_i.dat(7 downto 0);
irq_config.timeout <= slave_i.dat(23 downto 16);
......@@ -151,27 +155,19 @@ begin -- arch
else
case slave_i.adr(5 downto 2) is
when c_GCR_SLOT_IRQ_MASK =>
gcr_rd_data(23 downto 16) <= irq_config.mask_in;
gcr_rd_data(7 downto 0) <= irq_config.mask_out;
gcr_rd_data(23 downto 16) <= irq_config.mask_out;
gcr_rd_data(7 downto 0) <= irq_config.mask_in;
when c_GCR_SLOT_IRQ_COALESCE =>
gcr_rd_data(7 downto 0) <= irq_config.threshold;
gcr_rd_data(23 downto 16) <= irq_config.timeout;
when c_GCR_SLOT_STATUS =>
for i in 0 to g_CONFIG.slot_count-1 loop
gcr_rd_data(i+16) <= incoming_status_i(i).empty;
end loop; -- i
for i in 0 to g_CONFIG.slot_count-1 loop
gcr_rd_data(i) <= not outgoing_status_i(i).empty;
end loop; -- i
gcr_rd_data <= slot_status;
when c_GCR_SLOT_COUNT =>
gcr_rd_data(7 downto 0) <=
std_logic_vector(to_unsigned(g_CONFIG.slot_count, 8));
gcr_rd_data(15 downto 8) <=
std_logic_vector(to_unsigned(g_CONFIG.slot_count, 8));
when others => null;
end case;
......
hdl/testbench/svec_mt_demo-verification/main.sv
View file @ 569a7177
......@@ -129,13 +129,13 @@ module main;
$display("Loading binary for cpu #0");
drv.load_firmware(0, "../sw/verif/verif.bin", 1'b0);
$display("Start cpu #0");
$display("Start cpu #0 at %t", $time);
drv.reset_core(0, 0);
// Enable all console interrupts
drv.m_csr.writel(`ADDR_MT_CPU_CSR_DBG_IMSK, 8'hff);
// Enable HMQ out irqs.
// Enable HMQ IN irqs.
drv.m_hmq.gcr_write(`MQUEUE_GCR_IRQ_MASK, 8'hff);
// Enable VIC interrupts (unmask)
......@@ -170,7 +170,8 @@ module main;
if (risr[0])
begin
drv.m_hmq.gcr_read(`MQUEUE_GCR_SLOT_STATUS, val);
if ((val & 16'hffff) != 0)
$display("HMQ IN irq: %x", val);
if ((val & 16'hff) != 0)
begin
uint32_t stat;
uint32_t len;
......
hdl/testbench/sw/verif/verif.c
View file @ 569a7177
......@@ -20,9 +20,10 @@ volatile unsigned int counts[8] __attribute__((section(".smem")));
static const int cpu = 0;
static void
failed(void)
failed(char c)
{
puts ("FAILED!\n");
putchar (c);
puts ("-FAILED!\n");
counts[cpu] |= 0xff00;
while (1)
;
......@@ -39,7 +40,7 @@ test_notify (void)
while ((lr_readl(MT_CPU_LR_REG_HOST_INT) & (1 << cpu)) != 0)
;
if (counts[cpu] != v + 1)
failed();
failed('N');
}
static const char msg[] = "Hello!";
......@@ -48,7 +49,7 @@ static void
test_hmq(void)
{
int i;
char *p;
unsigned char *p;
unsigned *hdr;
unsigned int v;
......@@ -68,17 +69,20 @@ test_hmq(void)
while((mq_poll() & 1) == 0)
;
if (counts[cpu] != v + 1)
failed();
failed('H');
// Read answer
hdr = mq_map_in_header(TRTL_HMQ, 0);
if (*hdr != 2)
failed();
failed('h');
p = mq_map_in_buffer(TRTL_HMQ, 0);
for (i = 0; i < sizeof (msg); i++)
if (~p[i] != msg[i])
failed();
if ((~p[i] & 0xff) != msg[i])
failed('K');
mq_discard(TRTL_HMQ, 0);
if ((mq_poll() & 1) != 0)
failed('k');
}
static void
......@@ -100,6 +104,23 @@ test_rmq(void)
hdr = mq_map_out_header(TRTL_RMQ, 0);
*hdr = (sizeof (msg) + 3) / 4;
mq_send(TRTL_RMQ, 0, 0);
// Wait for answer
while((mq_poll() & (1 << 16)) == 0)
;
// Read answer
hdr = mq_map_in_header(TRTL_RMQ, 0);
if (*hdr != (sizeof (msg) + 3) / 4)
failed('R');
p = mq_map_in_buffer(TRTL_RMQ, 0);
for (i = 0; i < sizeof (msg); i++)
if (p[i] != msg[i])
failed('r');
mq_discard(TRTL_RMQ, 0);
if ((mq_poll() & (1 << 16)) != 0)
failed('s');
}
int
......@@ -115,8 +136,7 @@ main(void)
test_hmq();
/* HMQ
RMQ
*/
puts ("Done\n");
return 0;
}
hdl/top/svec_mt_demo/svec_mt_demo.vhd
View file @ 569a7177
......@@ -322,8 +322,8 @@ begin -- architecture arch
rst_n_i => rst_n_sys,
slave_i => cnx_master_out(c_SLAVE_VIC),
slave_o => cnx_master_in(c_SLAVE_VIC),
irqs_i(0) => mt_hmq_out_irq,
irqs_i(1) => mt_hmq_in_irq,
irqs_i(0) => mt_hmq_in_irq,
irqs_i(1) => mt_hmq_out_irq,
irqs_i(2) => mt_console_irq,
irqs_i(3) => mt_notify_irq,
irq_master_o => vic_master_irq);
......
software/include/hw/mockturtle_queue.h
View file @ 569a7177
......@@ -64,10 +64,6 @@
#define TRTL_MQ_SLOT_STATUS_OCCUPIED_SHIFT 8
#define TRTL_MQ_SLOT_STATUS_OCCUPIED_MASK 0xff00
// [23:16] Number of transferred words in the message currently on top of the slot
#define TRTL_MQ_SLOT_STATUS_MSG_SIZE_SHIFT 16
#define TRTL_MQ_SLOT_STATUS_MSG_SIZE_MASK 0xff0000
// [31:28] log2(number of words in the slot).
#define TRTL_MQ_SLOT_STATUS_LOG2_WIDTH_SHIFT 28
#define TRTL_MQ_SLOT_STATUS_LOG2_WIDTH_MASK 0xf0000000
......@@ -92,33 +88,29 @@
// Layout of SLOT_COUNT register
// [7:0] Number of Incoming slots
#define TRTL_MQ_GCR_SLOT_COUNT_N_IN_SHIFT 0
#define TRTL_MQ_GCR_SLOT_COUNT_N_IN_MASK 0xff
// [15:8] Number of Outgoing slots
#define TRTL_MQ_GCR_SLOT_COUNT_N_OUT_SHIFT 8
#define TRTL_MQ_GCR_SLOT_COUNT_N_OUT_MASK 0xff00
// [7:0] Number of slots
#define TRTL_MQ_GCR_SLOT_COUNT_N_SHIFT 0
#define TRTL_MQ_GCR_SLOT_COUNT_N_MASK 0xff
// Layout of SLOT_STATUS register
// [15:0] Outgoing slots status. Each bit indicates a NOT EMPTY status of the corresponding outgoing slot
#define TRTL_MQ_GCR_SLOT_STATUS_OUT_SHIFT 0
#define TRTL_MQ_GCR_SLOT_STATUS_OUT_MASK 0xffff
// [7:0] Incoming slots status. Each bit indicates a not EMPTY status of the corresponding incoming slot (data are available).
#define TRTL_MQ_GCR_SLOT_STATUS_IN_SHIFT 0
#define TRTL_MQ_GCR_SLOT_STATUS_IN_MASK 0xff
// [31:16] Incoming slots status. Each bit indicates an EMPTY status of the corresponding incoming slot
#define TRTL_MQ_GCR_SLOT_STATUS_IN_SHIFT 16
#define TRTL_MQ_GCR_SLOT_STATUS_IN_MASK 0xffff0000
// [23:16] Outgoing slots status. Each bit indicates a NOT FULL status of the corresponding outgoing slot (data can be sent).
#define TRTL_MQ_GCR_SLOT_STATUS_OUT_SHIFT 16
#define TRTL_MQ_GCR_SLOT_STATUS_OUT_MASK 0xffff0000
// Layout of IRQ_MASK register
// [15:0] Outgoing slots status interrupt mask. Each bit enables generation of interrupt on NOT EMPTY status of the corresponding outgoing slot.
// [7:0] Incoming slots status interrupt mask. Each bit enables generation of interrupt on not EMPTY status of the corresponding incoming slot.
#define TRTL_MQ_GCR_IRQ_MASK_OUT_SHIFT 0
#define TRTL_MQ_GCR_IRQ_MASK_OUT_MASK 0xffff
#define TRTL_MQ_GCR_IRQ_MASK_OUT_MASK 0xff
// [31:16] Incoming slots status interrupt mask. Each bit enables generation of interrupt on EMPTY status of the corresponding incoming slot.
// [23:16] Outgoing slots status interrupt mask. Each bit enables generation of interrupt on NOT FULL status of the corresponding outgoing slot.
#define TRTL_MQ_GCR_IRQ_MASK_IN_SHIFT 16
#define TRTL_MQ_GCR_IRQ_MASK_IN_MASK 0xffff0000
#define TRTL_MQ_GCR_IRQ_MASK_IN_MASK 0x00ff0000
// Layout of IRQ_COALSESCE register
// The register is left for future IRQ coalescing support (if ever needed)
......
software/rt/lib/mockturtle-rt-common.c
View file @ 569a7177
......@@ -15,6 +15,12 @@
#include "mockturtle-rt-common.h"
int putchar (int c)
{
lr_writel(c, MT_CPU_LR_REG_DBG_CHR);
return 0;
}
/**
* It sends a string over the serial interface
* @param[in] p string to send
......@@ -24,15 +30,14 @@
* If you neeed the new-line or the carriage-return
* you have to add them to your strings.
*/
int puts(const char *p)
{
const char *p_orig = p;
char c;
int i = 0;
while ((c = *(p++))) {
lr_writel(c, MT_CPU_LR_REG_DBG_CHR);
++i;
}
while ((c = *(p++)))
putchar (c);
return i;
return p - p_orig;
}
software/rt/lib/mockturtle-rt-serial.h
View file @ 569a7177
......@@ -144,6 +144,7 @@ static inline int pr_error(const char *fmt, ...)
}
#endif
extern int putchar (int c);
extern int puts(const char *p);
/**@}*/
......
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