hdl: update timing constraints of spec_mt_demo

59a2c707 · Dimitris Lampridis · c3c2a68d · 59a2c707 · 59a2c707 · 59a2c707
Commit 59a2c707 authored Mar 15, 2019 by Dimitris Lampridis
5 changed files
--- a/hdl/syn/spec_mt_demo/.gitignore
+++ b/hdl/syn/spec_mt_demo/.gitignore
@@ -2,3 +2,4 @@
 !.gitignore
 !Manifest.py
 !spec_mt_demo.ucf
+!syn_extra_steps.tcl
--- a/hdl/syn/spec_mt_demo/Manifest.py
+++ b/hdl/syn/spec_mt_demo/Manifest.py
@@ -11,9 +11,12 @@ syn_project = "spec_mt_demo.xise"
 top_module  = "spec_mt_demo"
 syn_tool    = "ise"

-syn_post_project_cmd = "$(TCL_INTERPRETER) " + \
-                       fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
-                       syn_tool + " $(PROJECT_FILE)"
+syn_post_project_cmd = (
+    "$(TCL_INTERPRETER) " + \
+    fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
+    syn_tool + " $(PROJECT_FILE);" \
+    "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
+)

 files = [
    "spec_mt_demo.ucf",

--- a/hdl/syn/spec_mt_demo/spec_mt_demo.ucf
+++ b/hdl/syn/spec_mt_demo/spec_mt_demo.ucf
@@ -149,14 +149,60 @@ NET "brd_button_i[0]" IOSTANDARD = "LVCMOS18";
 NET "brd_button_i[1]" LOC = D21;
 NET "brd_button_i[1]" IOSTANDARD = "LVCMOS18";

-NET "gn_rst_n_i" TIG;

-NET "gn_p2l_clk_p_i" TNM_NET = p2l_clk_p_i;
-TIMESPEC TS_p2l_clk_p_i = PERIOD "p2l_clk_p_i" 5 ns HIGH 50%;
+#===============================================================================
+# Timing constraints and exceptions
+#===============================================================================
+
+# All input clocks
+
 NET "gn_p2l_clk_n_i" TNM_NET = p2l_clk_n_i;
 TIMESPEC TS_p2l_clk_n_i = PERIOD "p2l_clk_n_i" 5 ns HIGH 50%;

-NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
-TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
 NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
 TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
+
+#----------------------------------------
+# Asynchronous resets
+#----------------------------------------
+
+# GN4124
+NET "gn_rst_n_i" TIG;
+NET "cmp_gn4124_core/rst_*" TIG;
+
+# Ignore async reset inputs to reset synchronisers
+NET "*/gc_reset_async_in" TIG;
+
+#----------------------------------------
+# Cross-clock domain sync
+#----------------------------------------
+
+# Declaration of domains
+NET "clk_sys"         TNM_NET = sys_clk_62_5;
+NET "clk_125m_pllref" TNM_NET = clk_125m_pllref;
+
+TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
+
+NET "cmp_gn4124_core/sys_clk" TNM_NET = pci_sys_clk;
+NET "cmp_gn4124_core/io_clk"  TNM_NET = pci_io_clk;
+
+TIMEGRP "pci_clk" = "pci_sys_clk"  "pci_io_clk";
+
+# Exceptions for crossings via gc_sync_ffs
+NET "*/gc_sync_ffs_in" TNM_NET = "sync_ffs";
+
+TIMEGRP "pci_sync_ffs"  = "sync_ffs" EXCEPT "pci_clk";
+TIMEGRP "sys_sync_ffs"  = "sync_ffs" EXCEPT "sys_clk";
+
+TIMESPEC TS_pci_sync_ffs  = FROM pci_clk  TO "pci_sync_ffs"  TIG;
+TIMESPEC TS_sys_sync_ffs  = FROM sys_clk   TO "sys_sync_ffs"  TIG;
+
+# Exceptions for crossings via gc_sync_register
+NET "*/gc_sync_register_in[*]" TNM_NET = "sync_reg";
+
+TIMEGRP "pci_sync_reg"  = "sync_reg" EXCEPT "pci_clk";
+TIMEGRP "sys_sync_reg"  = "sync_reg" EXCEPT "sys_clk";
+
+TIMESPEC TS_pci_sync_reg      = FROM pci_clk         TO "pci_sync_reg"  5ns  DATAPATHONLY;
+TIMESPEC TS_sys_62m5_sync_reg = FROM sys_clk_62_5    TO "sys_sync_reg"  16ns DATAPATHONLY;
+TIMESPEC TS_sys_125m_sync_reg = FROM clk_125m_pllref TO "sys_sync_reg"  8ns  DATAPATHONLY;
--- a/hdl/syn/spec_mt_demo/syn_extra_steps.tcl
+++ b/hdl/syn/spec_mt_demo/syn_extra_steps.tcl
+# get project file from 1st command-line argument
+set project_file [lindex $argv 0]
+
+if {![file exists $project_file]} {
+    report ERROR "Missing file $project_file, exiting."
+    exit -1
+}
+
+xilinx::project open $project_file
+
+# Some of these are not respected by ISE when passed through hdlmake,
+# so we add them all ourselves after creating the project
+#
+# Not respected by ISE when passed through hdlmake:
+# 1. Pack I/O Registers/Latches into IOBs
+# 2. Register Duplication Map
+
+xilinx::project set "Enable Multi-Threading" "2" -process "Map"
+xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
+
+xilinx::project set "Pack I/O Registers into IOBs" "Yes"
+xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+
+xilinx::project set "Register Balancing" "Yes"
+xilinx::project set "Register Duplication Map" "On"
+
+#xilinx::project set "Placer Extra Effort Map" "Normal"
+#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
+
+xilinx::project save
+
+xilinx::project close
--- a/hdl/top/spec_mt_demo/spec_mt_demo.vhd
+++ b/hdl/top/spec_mt_demo/spec_mt_demo.vhd
@@ -125,9 +125,9 @@ architecture arch of spec_mt_demo is
  signal clk_sys         : std_logic;
  signal clk_sys_locked  : std_logic;

-  signal rst_sys_n       : std_logic;
-  signal rstlogic_arst_n : std_logic;
-  signal gn_rst_n_p      : std_logic;
+  signal rst_sys_n     : std_logic;
+  signal rstlogic_arst : std_logic;
+  signal gn_rst_n_p    : std_logic;

  signal gn_wbadr : std_logic_vector(31 downto 0);

@@ -184,7 +184,7 @@ begin  -- architecture arch
      I => pllout_clk_sys);

  -- Detect when gn_rst_n_i goes high (end of reset) and use this edge to
-  -- generate rstlogic_arst_n. This is needed to connect optional PCIe
+  -- generate rstlogic_arst. This is needed to connect optional PCIe
  -- reset. When board runs standalone, we need to ignore PCIe reset being
  -- constantly low.
  cmp_arst_edge: gc_sync_ffs
@@ -196,19 +196,17 @@ begin  -- architecture arch
      data_i   => gn_rst_n_i,
      npulse_o => gn_rst_n_p);

-  -- logic AND of all (possibly) async reset sources (active low)
-  rstlogic_arst_n <= clk_sys_locked and (not gn_rst_n_p);
+  -- logic AND of all (possibly) async reset sources (active high)
+  rstlogic_arst <= (not clk_sys_locked) and gn_rst_n_p;

-  cmp_rstlogic_reset : gc_reset
+  cmp_rstlogic_reset : gc_reset_multi_aasd
    generic map (
-      g_clocks    => 1,
-      g_logdelay  => 4,
-      g_syncdepth => 3)
+      g_CLOCKS  => 1,
+      g_RST_LEN => 16)
    port map (
-      free_clk_i => clk_125m_pllref,
-      locked_i   => rstlogic_arst_n,
+      arst_i     => rstlogic_arst,
      clks_i(0)  => clk_sys,
-      rstn_o(0)  => rst_sys_n);
+      rst_n_o(0) => rst_sys_n);

  U_Intercon : xwb_sdb_crossbar
    generic map (