Commit 5c0d2ab3 authored by Dimitris Lampridis's avatar Dimitris Lampridis

Revert "hdl: proposed fix for svec_mt_demo to prevent gpio pins from being…

Revert "hdl: proposed fix for svec_mt_demo to prevent gpio pins from being trimmed away during synthesis"

This reverts commit e7f9469c.

Not needed anymore, and it causes trouble during mapping of the GPIO pins.
parent 5a374dec
...@@ -256,14 +256,17 @@ NET "fp_gpio2_a2b_o" IOSTANDARD="LVCMOS33"; ...@@ -256,14 +256,17 @@ NET "fp_gpio2_a2b_o" IOSTANDARD="LVCMOS33";
NET "fp_gpio34_a2b_o" LOC=V28; NET "fp_gpio34_a2b_o" LOC=V28;
NET "fp_gpio34_a2b_o" IOSTANDARD="LVCMOS33"; NET "fp_gpio34_a2b_o" IOSTANDARD="LVCMOS33";
NET "fp_gpio_in[0]" LOC=R30; NET "fp_gpio1_b" LOC=R30;
NET "fp_gpio_in[0]" IOSTANDARD="LVCMOS33"; NET "fp_gpio1_b" IOSTANDARD="LVCMOS33";
NET "fp_gpio_in[1]" LOC=T28;
NET "fp_gpio_in[1]" IOSTANDARD="LVCMOS33"; NET "fp_gpio2_b" LOC=T28;
NET "fp_gpio_in[2]" LOC=U29; NET "fp_gpio2_b" IOSTANDARD="LVCMOS33";
NET "fp_gpio_in[2]" IOSTANDARD="LVCMOS33";
NET "fp_gpio_in[3]" LOC=V27; NET "fp_gpio3_b" LOC=U29;
NET "fp_gpio_in[3]" IOSTANDARD="LVCMOS33"; NET "fp_gpio3_b" IOSTANDARD="LVCMOS33";
NET "fp_gpio4_b" LOC=V27;
NET "fp_gpio4_b" IOSTANDARD="LVCMOS33";
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i; NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%; TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
......
...@@ -56,7 +56,10 @@ entity svec_mt_demo is ...@@ -56,7 +56,10 @@ entity svec_mt_demo is
fp_gpio1_a2b_o : out std_logic; fp_gpio1_a2b_o : out std_logic;
fp_gpio2_a2b_o : out std_logic; fp_gpio2_a2b_o : out std_logic;
fp_gpio34_a2b_o : out std_logic; fp_gpio34_a2b_o : out std_logic;
fp_gpio_b : inout std_logic_vector(3 downto 0); fp_gpio1_b : inout std_logic;
fp_gpio2_b : inout std_logic;
fp_gpio3_b : inout std_logic;
fp_gpio4_b : inout std_logic;
-- Bypass VME core, useful only in simulation -- Bypass VME core, useful only in simulation
-- synthesis translate_off -- synthesis translate_off
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in; sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
...@@ -167,11 +170,6 @@ architecture arch of svec_mt_demo is ...@@ -167,11 +170,6 @@ architecture arch of svec_mt_demo is
signal powerup_rst_n : std_logic := '0'; signal powerup_rst_n : std_logic := '0';
signal sys_locked : std_logic; signal sys_locked : std_logic;
signal fp_gpio_in : std_logic_vector(3 downto 0);
attribute keep : string;
attribute keep of fp_gpio_in : signal is "true";
begin -- architecture arch begin -- architecture arch
U_Buf_CLK_PLL : IBUFGDS U_Buf_CLK_PLL : IBUFGDS
...@@ -382,19 +380,16 @@ begin -- architecture arch ...@@ -382,19 +380,16 @@ begin -- architecture arch
fp_gpio34_a2b_o <= cpu_gpio_oen(2); fp_gpio34_a2b_o <= cpu_gpio_oen(2);
-- FP GPIO bidir in/out (3 and 4 share the same direction line) -- FP GPIO bidir in/out (3 and 4 share the same direction line)
fp_gpio_gen : for i in 0 to 3 generate fp_gpio1_b <= cpu_gpio_out(0) when cpu_gpio_oen(0) = '1' else 'Z';
fp_gpio2_b <= cpu_gpio_out(1) when cpu_gpio_oen(1) = '1' else 'Z';
fp_gpio_b(i) <= cpu_gpio_out(i) when cpu_gpio_oen(i) = '1' else 'Z'; fp_gpio3_b <= cpu_gpio_out(2) when cpu_gpio_oen(2) = '1' else 'Z';
fp_gpio_in(i) <= fp_gpio_b(i); fp_gpio4_b <= cpu_gpio_out(3) when cpu_gpio_oen(2) = '1' else 'Z';
gpio_sync_ffs : gc_sync_ffs -- gpio inputs (same for both CPUs)
port map ( cpu_gpio_in(0) <= fp_gpio1_b;
clk_i => clk_sys, cpu_gpio_in(1) <= fp_gpio2_b;
rst_n_i => rst_n_sys, cpu_gpio_in(2) <= fp_gpio3_b;
data_i => fp_gpio_in(i), cpu_gpio_in(3) <= fp_gpio4_b;
synced_o => cpu_gpio_in(i));
end generate fp_gpio_gen;
cpu_gpio_in(23 downto 4) <= cpu_gpio_out(23 downto 4); cpu_gpio_in(23 downto 4) <= cpu_gpio_out(23 downto 4);
......
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