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Mock Turtle
Commit 5e8ad5b4 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: introduce SW reset signals for MT CPUs. 

There is one reset signal per CPU. Their behavior is the same as the reset bit in the control registers (it resets the corresponding CPU while leaving the RAM intact).
parent 38f7d4bc
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Showing with 84 additions and 74 deletions
.gitignore
View file @ 5e8ad5b4
......@@ -6,3 +6,4 @@ GPATH
GRTAGS
GTAGS
Makefile.specific
*.swp
doc/hdl/index.rst
View file @ 5e8ad5b4
......@@ -202,6 +202,7 @@ A VHDL component declaration for the MT top-level entity is included in the **mo
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
cpu_ext_rst_n_i : in std_logic_vector(g_CONFIG.cpu_count-1 downto 0) := (others=>'1');
sp_master_o : out t_wishbone_master_out;
sp_master_i : in t_wishbone_master_in := c_DUMMY_WB_MASTER_IN;
dp_master_o : out t_wishbone_master_out_array(0 to g_CONFIG.cpu_count-1);
......
hdl/rtl/cpu/mt_cpu_cb.vhd
View file @ 5e8ad5b4
......@@ -33,39 +33,40 @@ entity mt_cpu_cb is
g_SYSTEM_CLOCK_FREQ : integer;
g_WITH_WHITE_RABBIT : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_ref_i : in std_logic;
tm_i : in t_mt_timing_if;
sh_master_i : in t_wishbone_master_in := c_DUMMY_WB_MASTER_IN;
sh_master_o : out t_wishbone_master_out;
dp_master_i : in t_wishbone_master_in := c_DUMMY_WB_MASTER_IN;
dp_master_o : out t_wishbone_master_out;
hmq_slave_i : in t_wishbone_slave_in;
hmq_slave_o : out t_wishbone_slave_out;
rmq_src_o : out t_mt_stream_source_out_array(0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_src_i : in t_mt_stream_source_in_array(0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_snk_o : out t_mt_stream_sink_out_array(0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_snk_i : in t_mt_stream_sink_in_array(0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_src_config_o : out t_mt_stream_config_out_array( 0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_src_config_i : in t_mt_stream_config_in_array( 0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_snk_config_o : out t_mt_stream_config_out_array( 0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_snk_config_i : in t_mt_stream_config_in_array( 0 to g_CPU_CONFIG.rmq_config.slot_count-1);
cb_csr_i : in t_mt_per_cb_csr_out;
cb_csr_o : out t_mt_per_cb_csr_in;
gpio_i : in std_logic_vector(31 downto 0);
gpio_o : out std_logic_vector(31 downto 0);
uart_drdy_o : out std_logic;
uart_dack_i : in std_logic;
uart_data_o : out std_logic_vector(7 downto 0));
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
cpu_ext_rst_n_i : in std_logic;
clk_ref_i : in std_logic;
rst_n_ref_i : in std_logic;
tm_i : in t_mt_timing_if;
sh_master_i : in t_wishbone_master_in := c_DUMMY_WB_MASTER_IN;
sh_master_o : out t_wishbone_master_out;
dp_master_i : in t_wishbone_master_in := c_DUMMY_WB_MASTER_IN;
dp_master_o : out t_wishbone_master_out;
hmq_slave_i : in t_wishbone_slave_in;
hmq_slave_o : out t_wishbone_slave_out;
rmq_src_o : out t_mt_stream_source_out_array(0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_src_i : in t_mt_stream_source_in_array(0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_snk_o : out t_mt_stream_sink_out_array(0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_snk_i : in t_mt_stream_sink_in_array(0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_src_config_o : out t_mt_stream_config_out_array( 0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_src_config_i : in t_mt_stream_config_in_array( 0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_snk_config_o : out t_mt_stream_config_out_array( 0 to g_CPU_CONFIG.rmq_config.slot_count-1);
rmq_snk_config_i : in t_mt_stream_config_in_array( 0 to g_CPU_CONFIG.rmq_config.slot_count-1);
cb_csr_i : in t_mt_per_cb_csr_out;
cb_csr_o : out t_mt_per_cb_csr_in;
gpio_i : in std_logic_vector(31 downto 0);
gpio_o : out std_logic_vector(31 downto 0);
uart_drdy_o : out std_logic;
uart_dack_i : in std_logic;
uart_data_o : out std_logic_vector(7 downto 0));
end entity mt_cpu_cb;
architecture arch of mt_cpu_cb is
......@@ -295,17 +296,18 @@ begin -- arch
U_TheCoreCPU : entity work.mt_urv_wrapper
generic map (
g_IRAM_SIZE => g_CPU_CONFIG.memsize,
g_IRAM_INIT => g_CPU_IRAM_INIT,
g_CPU_ID => g_CPU_ID)
g_IRAM_SIZE => g_CPU_CONFIG.memsize,
g_IRAM_INIT => g_CPU_IRAM_INIT,
g_CPU_ID => g_CPU_ID)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
irq_i => x"00000000", -- no irqs, we want to be deterministic...
dwb_o => cpu_dwb_out,
dwb_i => cpu_dwb_in,
cpu_csr_i => cb_csr_i.cpu_o,
cpu_csr_o => cb_csr_o.cpu_i);
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
cpu_ext_rst_n_i => cpu_ext_rst_n_i,
irq_i => x"00000000", -- no irqs, we want to be deterministic...
dwb_o => cpu_dwb_out,
dwb_i => cpu_dwb_in,
cpu_csr_i => cb_csr_i.cpu_o,
cpu_csr_o => cb_csr_o.cpu_i);
U_Local_Registrers : entity work.mt_cpu_lr_wb_slave
port map (
......
hdl/rtl/cpu/mt_urv_wrapper.vhd
View file @ 5e8ad5b4
......@@ -23,17 +23,18 @@ use work.mt_per_cpu_csr_pkg.all;
entity mt_urv_wrapper is
generic(
g_IRAM_SIZE : integer;
g_IRAM_INIT : string;
g_CPU_ID : integer);
g_IRAM_SIZE : integer;
g_IRAM_INIT : string;
g_CPU_ID : integer);
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
irq_i : in std_logic_vector(31 downto 0) := x"00000000";
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
cpu_csr_i : in t_mt_per_cpu_csr_out;
cpu_csr_o : out t_mt_per_cpu_csr_in);
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
cpu_ext_rst_n_i : in std_logic;
irq_i : in std_logic_vector(31 downto 0) := x"00000000";
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
cpu_csr_i : in t_mt_per_cpu_csr_out;
cpu_csr_o : out t_mt_per_cpu_csr_in);
end mt_urv_wrapper;
architecture arch of mt_urv_wrapper is
......@@ -295,6 +296,8 @@ begin
end process p_im_valid;
core_sel_match <= cpu_csr_i.core_sel_o;
cpu_rst <= not rst_n_i or cpu_csr_i.reset_o;
-- Reset of the CPUs
cpu_rst <= (not cpu_ext_rst_n_i) or (not rst_n_i) or cpu_csr_i.reset_o;
end architecture arch;
hdl/rtl/mock_turtle_core.vhd
View file @ 5e8ad5b4
......@@ -46,29 +46,30 @@ entity mock_turtle_core is
-- Enables/disables WR support
g_WITH_WHITE_RABBIT : boolean := FALSE);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
clk_i : in std_logic;
rst_n_i : in std_logic;
cpu_ext_rst_n_i : in std_logic_vector(g_CONFIG.cpu_count-1 downto 0) := (others=>'1');
-- shared peripheral port
sp_master_o : out t_wishbone_master_out;
sp_master_i : in t_wishbone_master_in;
sp_master_o : out t_wishbone_master_out;
sp_master_i : in t_wishbone_master_in;
-- dedicated (per-cpu) peripheral port
dp_master_o : out t_wishbone_master_out_array(0 to g_CONFIG.cpu_count-1);
dp_master_i : in t_wishbone_master_in_array(0 to g_CONFIG.cpu_count-1);
dp_master_o : out t_wishbone_master_out_array(0 to g_CONFIG.cpu_count-1);
dp_master_i : in t_wishbone_master_in_array(0 to g_CONFIG.cpu_count-1);
-- Endpoint interface
rmq_endpoint_o : out t_mt_rmq_endpoint_iface_out;
rmq_endpoint_i : in t_mt_rmq_endpoint_iface_in := c_MT_RMQ_ENDPOINT_IFACE_IN_DEFAULT_VALUE;
host_slave_i : in t_wishbone_slave_in;
host_slave_o : out t_wishbone_slave_out;
clk_ref_i : in std_logic;
tm_i : in t_mt_timing_if;
gpio_o : out std_logic_vector(31 downto 0);
gpio_i : in std_logic_vector(31 downto 0) := x"00000000";
hmq_in_irq_o : out std_logic;
hmq_out_irq_o : out std_logic;
notify_irq_o : out std_logic;
console_irq_o : out std_logic);
rmq_endpoint_o : out t_mt_rmq_endpoint_iface_out;
rmq_endpoint_i : in t_mt_rmq_endpoint_iface_in := c_MT_RMQ_ENDPOINT_IFACE_IN_DEFAULT_VALUE;
host_slave_i : in t_wishbone_slave_in;
host_slave_o : out t_wishbone_slave_out;
clk_ref_i : in std_logic;
tm_i : in t_mt_timing_if;
gpio_o : out std_logic_vector(31 downto 0);
gpio_i : in std_logic_vector(31 downto 0) := x"00000000";
hmq_in_irq_o : out std_logic;
hmq_out_irq_o : out std_logic;
notify_irq_o : out std_logic;
console_irq_o : out std_logic);
end mock_turtle_core;
......@@ -390,6 +391,7 @@ begin -- arch
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
cpu_ext_rst_n_i => cpu_ext_rst_n_i(i),
clk_ref_i => clk_ref_i,
rst_n_ref_i => rst_n_ref,
tm_i => tm_i,
......
hdl/rtl/mock_turtle_pkg.vhd
View file @ 5e8ad5b4
......@@ -129,7 +129,7 @@ package mock_turtle_pkg is
c_MT_STREAM_CONFIG_IN_ARRAY2D_DEFAULT_VALUE,
c_MT_STREAM_CONFIG_IN_ARRAY2D_DEFAULT_VALUE
);
component mock_turtle_core is
generic (
g_CONFIG : t_mt_config := c_DEFAULT_MT_CONFIG;
......@@ -146,6 +146,7 @@ package mock_turtle_pkg is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
cpu_ext_rst_n_i : in std_logic_vector(g_CONFIG.cpu_count-1 downto 0) := (others=>'1');
sp_master_o : out t_wishbone_master_out;
sp_master_i : in t_wishbone_master_in := c_DUMMY_WB_MASTER_IN;
dp_master_o : out t_wishbone_master_out_array(0 to g_CONFIG.cpu_count-1);
......
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