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Commit 80379d02 authored by Tristan Gingold's avatar Tristan Gingold
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Work on rmq rx.

parent 45adb1df
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hdl/rtl/mqueue/mt_rmq_rx.vhd
View file @ 80379d02
......@@ -50,67 +50,109 @@ end mt_rmq_rx;
architecture arch of mt_rmq_rx is
type t_state is (WAIT_SLOT, CLAIM, READY);
signal state : t_state;
type t_state_enum is (WAIT_SLOT, CLAIM, READY);
signal addr : unsigned(12 downto 2);
type t_state is record
state : t_state_enum;
addr : unsigned(12 downto 2);
end record;
signal state, n_state : t_state;
begin
process (clk_i, rst_n_i)
p_fsm_next: process (rst_n_i, state, outb_stat_i, snk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
state <= WAIT_SLOT;
else
case state is
when WAIT_SLOT =>
if outb_stat_i.full = '0' then
snk_o.pkt_ready <= '1';
snk_o.ready <= '1';
-- A packet can be received. Claim it.
outb_o <= (sel => '1',
hdr_n => '0',
adr => c_mqueue_addr_command(12 downto 0),
dat => (c_mqueue_command_claim => '1', others => '0'),
we => '1',
wmask => "1111");
state <= CLAIM;
addr <= unsigned(c_mqueue_addr_header(12 downto 2));
else
snk_o.pkt_ready <= '0';
outb_o.sel <= '0';
end if;
when CLAIM =>
if snk_i.valid = '1' then
outb_o <= (sel => '1',
hdr_n => not snk_i.hdr,
adr => std_logic_vector(addr & "00"),
dat => snk_i.data,
we => '1',
wmask => "1111");
if snk_i.last = '1' then
if snk_i.hdr = '0' then
-- End of payload.
state <= READY;
else
-- End of header.
addr <= unsigned(c_mqueue_addr_payload(12 downto 2));
end if;
if rst_n_i = '0' then
n_state <= (state => WAIT_SLOT,
addr => (others => 'X'));
snk_o <= (pkt_ready => '0',
ready => '0');
outb_o <= (sel => '0',
hdr_n => 'X',
adr => (others => 'X'),
dat => (others => 'X'),
we => 'X',
wmask => "XXXX");
else
case state.state is
when WAIT_SLOT =>
if outb_stat_i.full = '0' then
-- A packet can be received. Claim it.
snk_o <= (pkt_ready => '1',
ready => '1');
outb_o <= (sel => '1',
hdr_n => '0',
adr => c_mqueue_addr_command(12 downto 0),
dat => (c_mqueue_command_claim => '1', others => '0'),
we => '1',
wmask => "1111");
n_state <= (state => CLAIM,
addr => unsigned(c_mqueue_addr_header(12 downto 2)));
else
-- Wait until a slot is ready.
snk_o <= (pkt_ready => '0',
ready => '0');
outb_o <= (sel => '0',
hdr_n => 'X',
adr => (others => 'X'),
dat => (others => 'X'),
we => 'X',
wmask => "XXXX");
end if;
when CLAIM =>
if snk_i.valid = '1' then
-- Data available, store it.
outb_o <= (sel => '1',
hdr_n => not snk_i.hdr,
adr => std_logic_vector(state.addr & "00"),
dat => snk_i.data,
we => '1',
wmask => "1111");
if snk_i.last = '1' then
if snk_i.hdr = '0' then
-- End of payload.
n_state <= (state => READY,
addr => (others => 'X'));
else
addr <= addr + 1;
-- End of header.
n_state <=
(state => CLAIM,
addr => unsigned(c_mqueue_addr_payload(12 downto 2)));
end if;
else
outb_o.sel <= '0';
n_state <= (state => CLAIM,
addr => state.addr + 1);
end if;
when READY =>
outb_o <= (sel => '1',
hdr_n => '0',
adr => c_mqueue_addr_command(12 downto 0),
dat => (c_mqueue_command_ready => '1',
others => '0'),
we => '1',
wmask => "1111");
state <= WAIT_SLOT;
end case;
else
outb_o <= (sel => '0',
hdr_n => 'X',
adr => (others => 'X'),
dat => (others => 'X'),
we => 'X',
wmask => "XXXX");
end if;
when READY =>
-- Make the slot ready.
outb_o <= (sel => '1',
hdr_n => '0',
adr => c_mqueue_addr_command(12 downto 0),
dat => (c_mqueue_command_ready => '1',
others => '0'),
we => '1',
wmask => "1111");
n_state <= (state => WAIT_SLOT,
addr => (others => 'X'));
end case;
end if;
end process;
p_fsm_reg: process (clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
state <= (state => WAIT_SLOT,
addr => (others => 'X'));
else
state <= n_state;
end if;
end if;
end process;
......
hdl/rtl/mqueue/mt_rmq_tx.vhd
View file @ 80379d02
......@@ -79,7 +79,7 @@ architecture rtl of mt_rmq_tx is
begin
header_last <= f_to_std_logic
(state.addr(5 downto 2) = to_unsigned(2**g_CONFIG.header_bits, 4));
(state.addr(5 downto 2) = to_unsigned(2**g_CONFIG.header_bits - 1, 4));
payload_last <= f_to_std_logic (state.addr = state.pkt_last_addr);
p_fsm: process (state, src_i, inb_i, inb_stat_i, header_last, payload_last)
......
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