hdl:cpu: upgraded to uRV hw multiply & divide, simulation fixes

Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>

hdl:cpu: upgraded to uRV hw multiply & divide, simulation fixes
Signed-off-by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
c1d9ea53 · Tomasz Wlostowski · Federico Vaga · 1bf24126 · c1d9ea53
Commit c1d9ea53 authored Jun 05, 2018 by Tomasz Wlostowski Committed by Federico Vaga Jun 06, 2018
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mt_urv_wrapper.vhd hdl/rtl/cpu/mt_urv_wrapper.vhd +9 -4

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--- a/hdl/rtl/cpu/mt_urv_wrapper.vhd
+++ b/hdl/rtl/cpu/mt_urv_wrapper.vhd
@@ -53,10 +53,10 @@ architecture arch of mt_urv_wrapper is
  begin
 -- synthesis translate_off
    for i in 0 to x'length-1 loop
-      if x(i + x'LEFT) = 'X' or x(i + x'LEFT) = 'U' then
-        tmp(i) := '0';
+      if x(i) = '1' or x(i) = 'H' then
+        tmp(i) := '1';
      else
-        tmp(i) := x(i + x'LEFT);
+        tmp(i) := '0';
      end if;
    end loop;
    return tmp;
@@ -108,6 +108,11 @@ begin
  dwb_o <= dwb_out;

  U_cpu_core : entity work.urv_cpu
+    generic map (
+      g_with_hw_debug => 1,
+      g_with_hw_mulh => 1,
+      g_with_hw_div => 1
+    )
    port map (
      clk_i            => clk_sys_i,
      rst_i            => cpu_rst,
@@ -246,7 +251,7 @@ begin

          if dwb_i.ack = '1' or bus_timeout_cnt = 100 then
            if dm_wb_write = '0' then
-              dm_wb_rdata  <= dwb_i.dat;
+              dm_wb_rdata  <= dwb_i.dat; --f_x_to_zero(dwb_i.dat);
              dm_select_wb <= '1';
              dm_load_done <= '1';
            else