Skip to content

M
Mock Turtle
Commit e174eeb1 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files
Options

ci: build hdl sim firmware

parent 62dd78e4
Hide whitespace changes
Inline Side-by-side
Showing with 29 additions and 8 deletions
.gitlab-ci.yml
View file @ e174eeb1
......@@ -26,6 +26,18 @@ software_build:
variables:
EDL_CI_SW_PATHS: software
sim_fw_build:
extends: .build_urv_fw
variables:
EXTRA2_CFLAGS: -DSIMULATION
script:
- make -C tests/firmware
- make -C demos firmware
artifacts:
paths:
- tests/firmware/**/*.bin
- demos/**/*.bin
test_fw_build:
extends: .build_urv_fw
variables:
......
demos/Makefile
View file @ e174eeb1
......@@ -13,11 +13,12 @@ DIRS += fmc-spec-carrier/software
TRTL ?= ..
TRTL_SW = $(TRTL)/software
all clean cleanall modules install modules_install: $(DIRS)
all clean cleanall modules install modules_install firmware: $(DIRS)
clean: TARGET = clean
cleanall: TARGET = cleanall
modules: TARGET = modules
firmware: TARGET = firmware
install: TARGET = install
modules_install: TARGET = modules_install
......
hdl/testbench/.gitlab-ci.yml
View file @ e174eeb1
......@@ -4,9 +4,9 @@
hdl_simulation:
interruptible: true
stage: build
stage: validate
when: manual
needs: []
needs: [sim_fw_build]
tags:
- questasim
- "10.5c"
......
hdl/testbench/hmq_async_recv/Manifest.py
View file @ e174eeb1
......@@ -27,7 +27,8 @@ include_dirs = [
fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
]
sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../tests/firmware/hmq-async-recv defconfig all"
# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
#sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../tests/firmware/hmq-async-recv defconfig all"
files = [
"main.sv",
......
hdl/testbench/mock_turtle_core/Manifest.py
View file @ e174eeb1
......@@ -25,7 +25,8 @@ include_dirs = [
fetchto + "/general-cores/sim/",
]
sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../tests/firmware/sim-verif defconfig all"
# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
#sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../tests/firmware/sim-verif defconfig all"
files = [
"main.sv",
......
hdl/testbench/mt_eth_ep/Manifest.py
View file @ e174eeb1
......@@ -18,7 +18,8 @@ include_dirs = [
fetchto + "/general-cores/sim/",
]
sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../tests/firmware/rmq-udp-send defconfig all"
# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
#sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../tests/firmware/rmq-udp-send defconfig all"
files = [
"main.sv",
......
hdl/testbench/spec_mt_demo/Manifest.py
View file @ e174eeb1
......@@ -27,7 +27,8 @@ include_dirs = [
fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
]
sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../demos/hello_world/firmware/fw-01 defconfig all"
# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
#sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../demos/hello_world/firmware/fw-01 defconfig all"
files = [
"main.sv",
......
hdl/testbench/svec_mt_demo/Manifest.py
View file @ e174eeb1
......@@ -27,7 +27,8 @@ include_dirs = [
fetchto + "/vme64x-core/hdl/sim/vme64x_bfm/",
]
sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../demos/hello_world/firmware/fw-01 defconfig all"
# Now done via CI, otherwise it must be done manually using a RISC-V cross-compiler
#sim_pre_cmd = "EXTRA2_CFLAGS='-DSIMULATION' make -C ../../../demos/hello_world/firmware/fw-01 defconfig all"
files = [
"main.sv",
......
software/firmware/Makefile
View file @ e174eeb1
......@@ -81,6 +81,9 @@ CFLAGS += -I$(TRTL_FW)/framework
CFLAGS += -I$(TRTL_SW)/include
CFLAGS += -DGIT_VERSION=$(RT_GIT_VERSION)
EXTRA2_CFLAGS += # To be set by user on make line
EXTRA_CFLAGS += $(EXTRA2_CFLAGS)
# used for firmware by trtl-project-creator
CFLAGS += $(EXTRA_CFLAGS)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment