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Mock Turtle
Commits
e3fd6f0e
Commit
e3fd6f0e
authored
Jun 18, 2015
by
Federico Vaga
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wrtd: reduce code duplication by using application/common
Signed-off-by:
Federico Vaga
<
federico.vaga@cern.ch
>
parent
cec1caf0
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mqueue.h
applications/wrtd/include/hw/mqueue.h
+0
-131
wrn_cpu_csr.h
applications/wrtd/include/hw/wrn_cpu_csr.h
+0
-126
wrn_cpu_lr.h
applications/wrtd/include/hw/wrn_cpu_lr.h
+0
-95
pp-printf.h
applications/wrtd/include/pp-printf.h
+0
-31
rt-common.h
applications/wrtd/include/rt-common.h
+0
-70
rt-message.h
applications/wrtd/include/rt-message.h
+0
-73
rt-mqueue.h
applications/wrtd/include/rt-mqueue.h
+0
-93
rt-smem.h
applications/wrtd/include/rt-smem.h
+0
-37
rt.h
applications/wrtd/include/rt.h
+0
-31
printf.c
applications/wrtd/rt/common/printf.c
+0
-43
rt-common.c
applications/wrtd/rt/common/rt-common.c
+0
-39
vsprintf-xint.c
applications/wrtd/rt/common/vsprintf-xint.c
+0
-109
wrn-crt0.S
applications/wrtd/rt/common/wrn-crt0.S
+0
-144
wrnode.ld
applications/wrtd/rt/common/wrnode.ld
+0
-37
wrnode.mk
applications/wrtd/rt/common/wrnode.mk
+0
-27
Makefile
applications/wrtd/rt/fd/Makefile
+6
-2
Makefile
applications/wrtd/rt/tdc/Makefile
+6
-2
No files found.
applications/wrtd/include/hw/mqueue.h
deleted
100644 → 0
View file @
cec1caf0
/*
* This work is part of the White Rabbit Node Core project.
*
* Copyright (C) 2013-2014 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
/*.
* White Rabbit Node Core
*
* mqueue.h: MQ register definitions (Host side)
*/
#ifndef __MQUEUE_H
#define __MQUEUE_H
// Nax number of supported incoming/outgoing slots
#define MAX_MQUEUE_SLOTS 16
// HMQ base address (wrs to the base addr of the WR Node Core)
#define BASE_HMQ 0x00000
// Global Control Registers base address, relative to BASE_HMQ (SLOT_COUNT, SLOT_STATUS, interrupt control, etc).
// Common for all incoming/outgoing slots in the queue
#define MQUEUE_BASE_GCR (0x0)
// Incoming slot base address, relative to BASE_HMQ
#define MQUEUE_BASE_IN(slot) (0x4000 + (slot) * 0x400)
// Outgoung slot base address, relative to BASE_HMQ
#define MQUEUE_BASE_OUT(slot) (0x8000 + (slot) * 0x400)
// MQ slot registers, relative to the base address of each slot: MQUEUE_BASE_IN(slot_no) or MQUEUE_BASE_OUT(slot_no)
#define MQUEUE_SLOT_COMMAND 0
// Status register
#define MQUEUE_SLOT_STATUS 4
// Start of data block
#define MQUEUE_SLOT_DATA_START 8
// Layout of MQUEUE_SLOT_COMMAND register:
// Claim: prepares a slot to send a message (w/o)
#define MQUEUE_CMD_CLAIM (1<<24)
// Purge: erases all messages from a slot (w/o)
#define MQUEUE_CMD_PURGE (1<<25)
// Ready: pushes the message to the queue. (w/o)
#define MQUEUE_CMD_READY (1<<26)
// Discard: removes last message from the queue, advancing to the next one (w/o)
#define MQUEUE_CMD_DISCARD (1<<27)
// Size of the message to be sent, in words (w/o). Must be written together with the
// READY command, e.g.:
// writel (MQUEUE_CMD_READY | 10, MQUEUE_SLOT_COMMAND);
#define MQUEUE_CMD_MSG_SIZE_MASK 0xff
#define MQUEUE_CMD_MSG_SIZE_SHIFT 0
// Layout of MQUEUE_SLOT_STATUS register:
// [0] Slot is full
#define MQUEUE_SLOT_STATUS_FULL (1<<0)
// [1] Slot is empty
#define MQUEUE_SLOT_STATUS_EMPTY (1<<1)
// [15:8] Number of occupied entries
#define MQUEUE_SLOT_STATUS_OCCUPIED_SHIFT 8
#define MQUEUE_SLOT_STATUS_OCCUPIED_MASK 0xff00
// [23:16] Number of transferred words in the message currently on top of the slot
#define MQUEUE_SLOT_STATUS_MSG_SIZE_SHIFT 16
#define MQUEUE_SLOT_STATUS_MSG_SIZE_MASK 0xff0000
// [31:28] log2(number of words in the slot).
#define MQUEUE_SLOT_STATUS_LOG2_WIDTH_SHIFT 28
#define MQUEUE_SLOT_STATUS_LOG2_WIDTH_MASK 0xf0000000
// [7:2] log2(number of entries in the slot).
#define MQUEUE_SLOT_STATUS_LOG2_ENTRIES_SHIFT 2
#define MQUEUE_SLOT_STATUS_LOG2_ENTRIES_MASK 0xfc
//
// MQ Global Control Registers.Adresses relative to MQUEUE_BASE_GCR:
//
#define MQUEUE_GCR_INCOMING_STATUS_MASK (0x0000ffff)
// Number of slots in this implementation of HMQ
#define MQUEUE_GCR_SLOT_COUNT 0
// EMPTY bits of all slots in a single register (for polling/IRQ status)
#define MQUEUE_GCR_SLOT_STATUS 4
// Interrupt mask (Outgoing: EMPTY, Incoming: not EMPTY)
#define MQUEUE_GCR_IRQ_MASK 8
// IRQ Coalescing register (reserved for future use)
#define MQUEUE_GCR_IRQ_COALESCE 12
// Layout of SLOT_COUNT register
// [7:0] Number of Incoming slots
#define MQUEUE_GCR_SLOT_COUNT_N_IN_SHIFT 0
#define MQUEUE_GCR_SLOT_COUNT_N_IN_MASK 0xff
// [15:8] Number of Outgoing slots
#define MQUEUE_GCR_SLOT_COUNT_N_OUT_SHIFT 8
#define MQUEUE_GCR_SLOT_COUNT_N_OUT_MASK 0xff00
// Layout of SLOT_STATUS register
// [15:0] Outgoing slots status. Each bit indicates a NOT EMPTY status of the corresponding outgoing slot
#define MQUEUE_GCR_SLOT_STATUS_OUT_SHIFT 0
#define MQUEUE_GCR_SLOT_STATUS_OUT_MASK 0xffff
// [31:16] Incoming slots status. Each bit indicates an EMPTY status of the corresponding incoming slot
#define MQUEUE_GCR_SLOT_STATUS_IN_SHIFT 16
#define MQUEUE_GCR_SLOT_STATUS_IN_MASK 0xffff0000
// Layout of IRQ_MASK register
// [15:0] Outgoing slots status interrupt mask. Each bit enables generation of interrupt on NOT EMPTY status of the corresponding outgoing slot.
#define MQUEUE_GCR_IRQ_MASK_OUT_SHIFT 0
#define MQUEUE_GCR_IRQ_MASK_OUT_MASK 0xffff
// [31:16] Incoming slots status interrupt mask. Each bit enables generation of interrupt on EMPTY status of the corresponding incoming slot.
#define MQUEUE_GCR_IRQ_MASK_IN_SHIFT 16
#define MQUEUE_GCR_IRQ_MASK_IN_MASK 0xffff0000
// Layout of IRQ_COALSESCE register
// The register is left for future IRQ coalescing support (if ever needed)
#endif
applications/wrtd/include/hw/wrn_cpu_csr.h
deleted
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cec1caf0
/*
Register definitions for slave core: WR Node CPU Control/Status registers block
* File : wrn_cpu_csr.h
* Author : auto-generated by wbgen2 from wrn_cpu_csr.wb
* Created : Mon Dec 8 15:40:37 2014
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrn_cpu_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRN_CPU_CSR_WB
#define __WBGEN2_REGDEFS_WRN_CPU_CSR_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Application ID Register */
/* definitions for register: CPU Reset Register */
/* definitions for register: CPU Enable Register */
/* definitions for register: CPU Upload Address Register */
/* definitions for field: Address in reg: CPU Upload Address Register */
#define WRN_CPU_CSR_UADDR_ADDR_MASK WBGEN2_GEN_MASK(0, 20)
#define WRN_CPU_CSR_UADDR_ADDR_SHIFT 0
#define WRN_CPU_CSR_UADDR_ADDR_W(value) WBGEN2_GEN_WRITE(value, 0, 20)
#define WRN_CPU_CSR_UADDR_ADDR_R(reg) WBGEN2_GEN_READ(reg, 0, 20)
/* definitions for register: Core Select Register */
/* definitions for register: Core Count Register */
/* definitions for register: Core Memory Size */
/* definitions for register: CPU Upload Data Register */
/* definitions for register: CPU Debug Register */
/* definitions for field: JTAG data in reg: CPU Debug Register */
#define WRN_CPU_CSR_DBG_JTAG_JDATA_MASK WBGEN2_GEN_MASK(0, 8)
#define WRN_CPU_CSR_DBG_JTAG_JDATA_SHIFT 0
#define WRN_CPU_CSR_DBG_JTAG_JDATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define WRN_CPU_CSR_DBG_JTAG_JDATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: JTAG address in reg: CPU Debug Register */
#define WRN_CPU_CSR_DBG_JTAG_JADDR_MASK WBGEN2_GEN_MASK(8, 3)
#define WRN_CPU_CSR_DBG_JTAG_JADDR_SHIFT 8
#define WRN_CPU_CSR_DBG_JTAG_JADDR_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define WRN_CPU_CSR_DBG_JTAG_JADDR_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for field: JTAG reset in reg: CPU Debug Register */
#define WRN_CPU_CSR_DBG_JTAG_RSTN WBGEN2_GEN_MASK(16, 1)
/* definitions for field: JTAG TCK in reg: CPU Debug Register */
#define WRN_CPU_CSR_DBG_JTAG_TCK WBGEN2_GEN_MASK(17, 1)
/* definitions for field: JTAG Update in reg: CPU Debug Register */
#define WRN_CPU_CSR_DBG_JTAG_UPDATE WBGEN2_GEN_MASK(18, 1)
/* definitions for register: CPU Debug Message Register */
/* definitions for field: Debug message byte for the selected core in reg: CPU Debug Message Register */
#define WRN_CPU_CSR_DBG_MSG_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define WRN_CPU_CSR_DBG_MSG_DATA_SHIFT 0
#define WRN_CPU_CSR_DBG_MSG_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define WRN_CPU_CSR_DBG_MSG_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: CPU Debug Messge Poll Register */
/* definitions for field: Debug Message data available in reg: CPU Debug Messge Poll Register */
#define WRN_CPU_CSR_DBG_POLL_READY_MASK WBGEN2_GEN_MASK(0, 8)
#define WRN_CPU_CSR_DBG_POLL_READY_SHIFT 0
#define WRN_CPU_CSR_DBG_POLL_READY_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define WRN_CPU_CSR_DBG_POLL_READY_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: CPU Debug Messge Interrupt Mask Register */
/* definitions for field: Per-CPU Debug Message Interrupt Enable in reg: CPU Debug Messge Interrupt Mask Register */
#define WRN_CPU_CSR_DBG_IMSK_ENABLE_MASK WBGEN2_GEN_MASK(0, 8)
#define WRN_CPU_CSR_DBG_IMSK_ENABLE_SHIFT 0
#define WRN_CPU_CSR_DBG_IMSK_ENABLE_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define WRN_CPU_CSR_DBG_IMSK_ENABLE_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* [0x0]: REG Application ID Register */
#define WRN_CPU_CSR_REG_APP_ID 0x00000000
/* [0x4]: REG CPU Reset Register */
#define WRN_CPU_CSR_REG_RESET 0x00000004
/* [0x8]: REG CPU Enable Register */
#define WRN_CPU_CSR_REG_ENABLE 0x00000008
/* [0xc]: REG CPU Upload Address Register */
#define WRN_CPU_CSR_REG_UADDR 0x0000000c
/* [0x10]: REG Core Select Register */
#define WRN_CPU_CSR_REG_CORE_SEL 0x00000010
/* [0x14]: REG Core Count Register */
#define WRN_CPU_CSR_REG_CORE_COUNT 0x00000014
/* [0x18]: REG Core Memory Size */
#define WRN_CPU_CSR_REG_CORE_MEMSIZE 0x00000018
/* [0x1c]: REG CPU Upload Data Register */
#define WRN_CPU_CSR_REG_UDATA 0x0000001c
/* [0x20]: REG CPU Debug Register */
#define WRN_CPU_CSR_REG_DBG_JTAG 0x00000020
/* [0x24]: REG CPU Debug Message Register */
#define WRN_CPU_CSR_REG_DBG_MSG 0x00000024
/* [0x28]: REG CPU Debug Messge Poll Register */
#define WRN_CPU_CSR_REG_DBG_POLL 0x00000028
/* [0x2c]: REG CPU Debug Messge Interrupt Mask Register */
#define WRN_CPU_CSR_REG_DBG_IMSK 0x0000002c
#endif
applications/wrtd/include/hw/wrn_cpu_lr.h
deleted
100644 → 0
View file @
cec1caf0
/*
Register definitions for slave core: WR Node CPU Local Registers
* File : wrn_cpu_lr.h
* Author : auto-generated by wbgen2 from wrn_cpu_lr.wb
* Created : Mon Dec 8 15:40:37 2014
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrn_cpu_lr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRN_CPU_LR_WB
#define __WBGEN2_REGDEFS_WRN_CPU_LR_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: CPU Polling Register */
/* definitions for field: HMQ Slot Status in reg: CPU Polling Register */
#define WRN_CPU_LR_POLL_HMQ_MASK WBGEN2_GEN_MASK(0, 16)
#define WRN_CPU_LR_POLL_HMQ_SHIFT 0
#define WRN_CPU_LR_POLL_HMQ_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define WRN_CPU_LR_POLL_HMQ_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: RMQ Slot Status in reg: CPU Polling Register */
#define WRN_CPU_LR_POLL_RMQ_MASK WBGEN2_GEN_MASK(16, 16)
#define WRN_CPU_LR_POLL_RMQ_SHIFT 16
#define WRN_CPU_LR_POLL_RMQ_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define WRN_CPU_LR_POLL_RMQ_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: CPU Status Register */
/* definitions for field: WR Link Up in reg: CPU Status Register */
#define WRN_CPU_LR_STAT_WR_LINK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: WR Time OK in reg: CPU Status Register */
#define WRN_CPU_LR_STAT_WR_TIME_OK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: WR Aux Clock OK in reg: CPU Status Register */
#define WRN_CPU_LR_STAT_WR_AUX_CLOCK_OK_MASK WBGEN2_GEN_MASK(2, 8)
#define WRN_CPU_LR_STAT_WR_AUX_CLOCK_OK_SHIFT 2
#define WRN_CPU_LR_STAT_WR_AUX_CLOCK_OK_W(value) WBGEN2_GEN_WRITE(value, 2, 8)
#define WRN_CPU_LR_STAT_WR_AUX_CLOCK_OK_R(reg) WBGEN2_GEN_READ(reg, 2, 8)
/* definitions for field: Core ID in reg: CPU Status Register */
#define WRN_CPU_LR_STAT_CORE_ID_MASK WBGEN2_GEN_MASK(28, 4)
#define WRN_CPU_LR_STAT_CORE_ID_SHIFT 28
#define WRN_CPU_LR_STAT_CORE_ID_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define WRN_CPU_LR_STAT_CORE_ID_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: TAI Cycles */
/* definitions for register: TAI Seconds */
/* definitions for register: GPIO Input */
/* definitions for register: GPIO Set */
/* definitions for register: GPIO Clear */
/* definitions for register: Debug Message Output */
/* [0x0]: REG CPU Polling Register */
#define WRN_CPU_LR_REG_POLL 0x00000000
/* [0x4]: REG CPU Status Register */
#define WRN_CPU_LR_REG_STAT 0x00000004
/* [0x8]: REG TAI Cycles */
#define WRN_CPU_LR_REG_TAI_CYCLES 0x00000008
/* [0xc]: REG TAI Seconds */
#define WRN_CPU_LR_REG_TAI_SEC 0x0000000c
/* [0x10]: REG GPIO Input */
#define WRN_CPU_LR_REG_GPIO_IN 0x00000010
/* [0x14]: REG GPIO Set */
#define WRN_CPU_LR_REG_GPIO_SET 0x00000014
/* [0x18]: REG GPIO Clear */
#define WRN_CPU_LR_REG_GPIO_CLEAR 0x00000018
/* [0x1c]: REG Debug Message Output */
#define WRN_CPU_LR_REG_DBG_CHR 0x0000001c
#endif
applications/wrtd/include/pp-printf.h
deleted
100644 → 0
View file @
cec1caf0
/*
* This work is part of the White Rabbit Node Core project.
*
* Copyright (C) 2013-2014 CERN (www.cern.ch)
* Author: Alessandro Rubini <rubini@gnudd.com>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#ifndef __PP_PRINTF_H
#define __PP_PRINTF_H
#include <stdarg.h>
#define CONFIG_PRINT_BUFSIZE 128
extern
int
pp_printf
(
const
char
*
fmt
,
...)
__attribute__
((
format
(
printf
,
1
,
2
)));
extern
int
pp_sprintf
(
char
*
s
,
const
char
*
fmt
,
...)
__attribute__
((
format
(
printf
,
2
,
3
)));
extern
int
pp_vprintf
(
const
char
*
fmt
,
va_list
args
);
extern
int
pp_vsprintf
(
char
*
buf
,
const
char
*
,
va_list
)
__attribute__
((
format
(
printf
,
2
,
0
)));
/* This is what we rely on for output */
extern
int
puts
(
const
char
*
s
);
#endif
applications/wrtd/include/rt-common.h
deleted
100644 → 0
View file @
cec1caf0
/*
* This work is part of the White Rabbit Node Core project.
*
* Copyright (C) 2013-2014 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
/*.
* White Rabbit Node Core
*
* rt-common.h: common WRN CPU definitions and routines
*/
#ifndef __RT_COMMON_H
#define __RT_COMMON_H
#include <stdint.h>
#include <stdio.h>
#include "hw/wrn_cpu_lr.h"
/* Dedicated Peripheral base */
#define CPU_DP_BASE 0x200000
/* CPU Local Registers base */
#define CPU_LR_BASE 0x100000
void
rt_set_debug_slot
(
int
slot
);
static
inline
uint32_t
dp_readl
(
uint32_t
reg
)
{
return
*
(
volatile
uint32_t
*
)
(
reg
+
CPU_DP_BASE
);
}
static
inline
void
dp_writel
(
uint32_t
value
,
uint32_t
reg
)
{
*
(
volatile
uint32_t
*
)
(
reg
+
CPU_DP_BASE
)
=
value
;
}
static
inline
uint32_t
lr_readl
(
uint32_t
reg
)
{
return
*
(
volatile
uint32_t
*
)
(
reg
+
CPU_LR_BASE
);
}
static
inline
uint32_t
lr_writel
(
uint32_t
value
,
uint32_t
reg
)
{
*
(
volatile
uint32_t
*
)
(
reg
+
CPU_LR_BASE
)
=
value
;
}
static
inline
void
gpio_set
(
int
pin
)
{
lr_writel
(
(
1
<<
pin
),
WRN_CPU_LR_REG_GPIO_SET
);
}
static
inline
void
gpio_clear
(
int
pin
)
{
lr_writel
(
(
1
<<
pin
),
WRN_CPU_LR_REG_GPIO_CLEAR
);
}
/* fixme: use Timing Unit */
static
inline
void
delay
(
int
n
)
{
int
i
;
for
(
i
=
0
;
i
<
n
;
i
++
)
asm
volatile
(
"nop"
);
}
#endif
applications/wrtd/include/rt-message.h
deleted
100644 → 0
View file @
cec1caf0
/*
* This work is part of the White Rabbit Node Core project.
*
* Copyright (C) 2013-2014 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
/*.
* White Rabbit Node Core
*
* rt-message.h: Message assembling helper functions
*/
#ifndef __RT_MESSAGE_H
#define __RT_MESSAGE_H
#ifdef WRNODE_RT
#include "wrtd-common.h"
enum
wrnc_msg_direction
{
WRNC_MSG_DIR_SEND
=
0
,
WRNC_MSG_DIR_RECEIVE
=
1
};
struct
wrnc_msg
{
uint32_t
datalen
;
/**< payload length*/
volatile
uint32_t
*
data
;
/**< payload */
uint32_t
max_size
;
/**< maximum message size for chosen slot */
uint32_t
offset
;
/**< serialization/deserialization offset */
enum
wrnc_msg_direction
direction
;
/**< serialization direction (used by wrnc_msg_x functions) */
int
error
;
/** serialization error status */
int
slot
;
/** concerned slot */
};
static
inline
struct
wrnc_msg
hmq_msg_claim_out
(
int
slot
,
int
max_size
)
{
struct
wrnc_msg
b
;
mq_claim
(
0
,
slot
);
b
.
data
=
mq_map_out_buffer
(
0
,
slot
);
b
.
direction
=
WRNC_MSG_DIR_SEND
;
b
.
max_size
=
max_size
;
b
.
offset
=
0
;
b
.
datalen
=
0
;
b
.
slot
=
slot
;
return
b
;
}
static
inline
struct
wrnc_msg
hmq_msg_claim_in
(
int
slot
,
int
max_size
)
{
struct
wrnc_msg
b
;
b
.
data
=
mq_map_in_buffer
(
0
,
slot
);
b
.
direction
=
WRNC_MSG_DIR_RECEIVE
;
b
.
max_size
=
max_size
;
b
.
datalen
=
max_size
;
b
.
offset
=
0
;
b
.
slot
=
slot
;
return
b
;
}
static
inline
void
hmq_msg_send
(
struct
wrnc_msg
*
buf
)
{
mq_send
(
0
,
buf
->
slot
,
buf
->
datalen
);
}
#endif
#endif
applications/wrtd/include/rt-mqueue.h
deleted
100644 → 0
View file @
cec1caf0
/*
* This work is part of the White Rabbit Node Core project.
*
* Copyright (C) 2013-2014 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
/*.
* White Rabbit Node Core
*
* rt-mqueue.h: Message Queues definitions and functions
*/
#ifndef __RT_MQUEUE_H
#define __RT_MQUEUE_H
#define REG_LR_POLL 0x100000
/* MQ Base addresses */
#define HMQ_BASE 0x40010000
#define RMQ_BASE 0x40020000
/* MQ Slot offsets */
#define MQ_GCR (0x0)
#define MQ_IN(slot) (0x4000 + (slot) * 0x400)
#define MQ_OUT(slot) (0x8000 + (slot) * 0x400)
/* MQ Commands */
#define MQ_CMD_CLAIM (1 << 24)
#define MQ_CMD_PURGE (1 << 25)
#define MQ_CMD_READY (1 << 26)
#define MQ_CMD_DISCARD (1 << 27)
/* MQ Registers */
#define MQ_SLOT_COMMAND 0
#define MQ_SLOT_STATUS 4
#define MQ_SLOT_DATA_START 8
struct
rmq_message_addr
{
uint32_t
target_ip
;
uint32_t
target_port
;
uint32_t
target_offset
;
};
static
inline
void
mq_writel
(
int
remote
,
uint32_t
val
,
uint32_t
reg
)
{
if
(
remote
)
*
(
volatile
uint32_t
*
)
(
RMQ_BASE
+
reg
)
=
val
;
else
*
(
volatile
uint32_t
*
)
(
HMQ_BASE
+
reg
)
=
val
;
}
static
inline
void
mq_claim
(
int
remote
,
int
slot
)
{
mq_writel
(
remote
,
MQ_CMD_CLAIM
,
MQ_OUT
(
slot
)
+
MQ_SLOT_COMMAND
);
}
static
inline
void
mq_send
(
int
remote
,
int
slot
,
int
count
)
{
mq_writel
(
remote
,
MQ_CMD_READY
|
count
,
MQ_OUT
(
slot
)
+
MQ_SLOT_COMMAND
);
}
static
inline
void
mq_discard
(
int
remote
,
int
slot
)
{
mq_writel
(
remote
,
MQ_CMD_DISCARD
,
MQ_IN
(
slot
)
);
}
static
void
*
mq_map_out_buffer
(
int
remote
,
int
slot
)
{
uint32_t
base
=
remote
?
RMQ_BASE
:
HMQ_BASE
;
return
(
void
*
)
(
base
+
MQ_OUT
(
slot
)
+
MQ_SLOT_DATA_START
);
}
static
void
*
mq_map_in_buffer
(
int
remote
,
int
slot
)
{
uint32_t
base
=
remote
?
RMQ_BASE
:
HMQ_BASE
;
return
(
void
*
)
(
base
+
MQ_IN
(
slot
)
+
MQ_SLOT_DATA_START
);
}
static
inline
uint32_t
mq_poll
()
{
return
*
(
volatile
uint32_t
*
)
(
REG_LR_POLL
);
}
static
inline
uint32_t
rmq_poll
(
int
slot
)
{
return
*
(
volatile
uint32_t
*
)
(
REG_LR_POLL
)
&
(
1
<<
(
16
+
slot
));
}
#endif
applications/wrtd/include/rt-smem.h
deleted
100644 → 0
View file @
cec1caf0
/*
* This work is part of the White Rabbit Node Core project.
*
* Copyright (C) 2013-2014 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
/*.
* White Rabbit Node Core
*
* rt-smem.h: Shared Memory definitions & API
*/
#ifndef __WRNODE_SMEM_H
#define __WRNODE_SMEM_H
#define SMEM_RANGE_ADD 0x2000
#define SMEM_RANGE_SUB 0x4000
#define SMEM_RANGE_SET 0x6000
#define SMEM_RANGE_CLEAR 0x8000
#define SMEM_RANGE_FLIP 0xa000
#define SMEM __attribute__((section(".smem")))
static
inline
void
smem_atomic_add
(
int
*
p
,
int
x
)
{
*
(
volatile
int
*
)(
p
+
(
SMEM_RANGE_ADD
>>
2
))
=
x
;
}
static
inline
void
smem_atomic_sub
(
int
*
p
,
int
x
)
{
*
(
volatile
int
*
)(
p
+
(
SMEM_RANGE_SUB
>>
2
))
=
x
;
}
#endif
applications/wrtd/include/rt.h
deleted
100644 → 0
View file @
cec1caf0
/*
* This work is part of the White Rabbit Node Core project.
*
* Copyright (C) 2013-2014 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
/*.
* White Rabbit Node Core
*
* rt.h: all common stuff in a single header
*/
#ifndef __WRN_RT_H
#define __WRN_RT_H
#include <stdint.h>
#include "rt-mqueue.h"
#include "rt-common.h"
#include "rt-smem.h"
#include "pp-printf.h"
#endif
applications/wrtd/rt/common/printf.c
deleted
100644 → 0
View file @
cec1caf0
/*
* Basic printf based on vprintf based on vsprintf
*
* Alessandro Rubini for CERN, 2011 -- public domain
* (please note that the vsprintf is not public domain but GPL)
*/
#include <stdarg.h>
#include <pp-printf.h>
static
char
print_buf
[
CONFIG_PRINT_BUFSIZE
];
int
pp_vprintf
(
const
char
*
fmt
,
va_list
args
)
{
int
ret
;
ret
=
pp_vsprintf
(
print_buf
,
fmt
,
args
);
puts
(
print_buf
);
return
ret
;
}
int
pp_sprintf
(
char
*
s
,
const
char
*
fmt
,
...)
{
va_list
args
;
int
ret
;
va_start
(
args
,
fmt
);
ret
=
pp_vsprintf
(
s
,
fmt
,
args
);
va_end
(
args
);
return
ret
;
}
int
pp_printf
(
const
char
*
fmt
,
...)
{
va_list
args
;
int
ret
;
va_start
(
args
,
fmt
);
ret
=
pp_vprintf
(
fmt
,
args
);
va_end
(
args
);
return
ret
;
}
applications/wrtd/rt/common/rt-common.c
deleted
100644 → 0
View file @
cec1caf0
/*
* This work is part of the White Rabbit Node Core project.
*
* Copyright (C) 2013-2014 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
/*.
* White Rabbit Node Core
*
* rt-common.c: common RT CPU functions
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include "rt-mqueue.h"
#include "rt-common.h"
int
puts
(
const
char
*
p
)
{
char
c
;
int
i
=
0
;
while
(
c
=
*
(
p
++
))
{
lr_writel
(
c
,
WRN_CPU_LR_REG_DBG_CHR
);
++
i
;
}
/* Provide a string terminator */
lr_writel
(
'\0'
,
WRN_CPU_LR_REG_DBG_CHR
);
return
i
;
}
applications/wrtd/rt/common/vsprintf-xint.c
deleted
100644 → 0
View file @
cec1caf0
/*
* vsprintf-xint: a possible free-software replacement for mprintf
*
* public domain
*/
#include <stdarg.h>
#include <stdint.h>
static
const
char
hex
[]
=
"0123456789abcdef"
;
static
int
number
(
char
*
out
,
unsigned
value
,
int
base
,
int
lead
,
int
wid
)
{
char
tmp
[
16
];
int
i
=
16
,
ret
,
negative
=
0
;
/* No error checking at all: it is as ugly as possible */
if
((
signed
)
value
<
0
&&
base
==
10
)
{
negative
=
1
;
value
=
-
value
;
}
while
(
value
&&
i
)
{
tmp
[
--
i
]
=
hex
[
value
%
base
];
value
/=
base
;
}
if
(
i
==
16
)
tmp
[
--
i
]
=
'0'
;
if
(
negative
&&
lead
==
' '
)
{
tmp
[
--
i
]
=
'-'
;
negative
=
0
;
}
while
(
i
>
16
-
wid
+
negative
)
tmp
[
--
i
]
=
lead
;
if
(
negative
)
tmp
[
--
i
]
=
'-'
;
ret
=
16
-
i
;
while
(
i
<
16
)
*
(
out
++
)
=
tmp
[
i
++
];
return
ret
;
}
int
pp_vsprintf
(
char
*
buf
,
const
char
*
fmt
,
va_list
args
)
{
char
*
s
,
*
str
=
buf
;
int
base
,
lead
,
wid
;
for
(;
*
fmt
;
++
fmt
)
{
if
(
*
fmt
!=
'%'
)
{
*
str
++
=
*
fmt
;
continue
;
}
base
=
10
;
lead
=
' '
;
wid
=
1
;
repeat:
fmt
++
;
/* Skip '%' initially, other stuff later */
switch
(
*
fmt
)
{
case
'\0'
:
goto
ret
;
case
'0'
:
lead
=
'0'
;
goto
repeat
;
case
'*'
:
/* should be precision, just eat it */
base
=
va_arg
(
args
,
int
);
/* fall through: discard unknown stuff */
default:
if
(
*
fmt
>=
'1'
&&
*
fmt
<=
'9'
)
wid
=
*
fmt
-
'0'
;
goto
repeat
;
/* Special cases for conversions */
case
'c'
:
/* char: supported */
*
str
++
=
(
unsigned
char
)
va_arg
(
args
,
int
);
break
;
case
's'
:
/* string: supported */
s
=
va_arg
(
args
,
char
*
);
while
(
*
s
)
*
str
++
=
*
s
++
;
break
;
case
'n'
:
/* number-thus-far: not supported */
break
;
case
'%'
:
/* supported */
*
str
++
=
'%'
;
break
;
/* integers are more or less printed */
case
'p'
:
case
'x'
:
case
'X'
:
base
=
16
;
case
'o'
:
if
(
base
==
10
)
/* yet unchaged */
base
=
8
;
case
'd'
:
case
'i'
:
case
'u'
:
str
+=
number
(
str
,
va_arg
(
args
,
int
),
base
,
lead
,
wid
);
break
;
}
}
ret:
*
str
=
'\0'
;
return
str
-
buf
;
}
applications/wrtd/rt/common/wrn-crt0.S
deleted
100644 → 0
View file @
cec1caf0
/****************************************************************************
**
** Name: crt0ram.S
**
** Description:
** Implements boot-code that calls LatticeDDInit (that calls main())
** Implements exception handlers (actually, redirectors)
**
** $Revision: $
**
** Disclaimer:
**
** This source code is intended as a design reference which
** illustrates how these types of functions can be implemented. It
** is the user's responsibility to verify their design for
** consistency and functionality through the use of formal
** verification methods. Lattice Semiconductor provides no warranty
** regarding the use or functionality of this code.
**
** --------------------------------------------------------------------
**
** Lattice Semiconductor Corporation
** 5555 NE Moore Court
** Hillsboro, OR 97214
** U.S.A
**
** TEL: 1-800-Lattice (USA and Canada)
** (503)268-8001 (other locations)
**
** web: http://www.latticesemi.com
** email: techsupport@latticesemi.com
**
** --------------------------------------------------------------------------
**
** Change History (Latest changes on top)
**
** Ver Date Description
** --------------------------------------------------------------------------
** 3.8 Apr-15-2011 Added __MICO_USER_<handler>_HANDLER__ preprocessor to
** allow customers to implement their own handlers for:
** DATA_ABORT, INST_ABORT
**
** 3.1 Jun-18-2008 Added __MICO_NO_INTERRUPTS__ preprocessor
** option to exclude invoking MicoISRHandler
** to reduce code-size in apps that don't use
** interrupts
**
** 3.0 Mar-25-2008 Added Header
**
**---------------------------------------------------------------------------
*****************************************************************************/
/*
* LatticeMico32 C startup code.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* From include/sys/signal.h */
#define SIGINT 2 /* interrupt */
#define SIGTRAP 5 /* trace trap */
#define SIGFPE 8 /* arithmetic exception */
#define SIGSEGV 11 /* segmentation violation */
//#define MICO32_FULL_CONTEXT_SAVE_RESTORE
/* Exception handlers - Must be 32 bytes long. */
.section .boot, "ax", @progbits
.global _start
_start:
.global _reset_handler
.type _reset_handler, @function
_reset_handler:
xor r0, r0, r0
wcsr IE, r0
wcsr IM, r0
mvhi r1, hi(_reset_handler)
ori r1, r1, lo(_reset_handler)
wcsr EBA, r1
calli _crt0
nop
.size _reset_handler, .-_reset_handler
.extern _irq_entry
.org 0xc0
.global _interrupt_handler
.type _interrupt_handler, @function
_interrupt_handler:
nop
.org 0x100
.global _crt0
.type _crt0, @function
_crt0:
/* Clear r0 */
xor r0, r0, r0
xor r1, r1, r1
xor r2, r2, r2
xor r3, r3, r3
/* Setup stack and global pointer */
mvhi sp, hi(_fstack)
ori sp, sp, lo(_fstack)
mvhi gp, hi(_gp)
ori gp, gp, lo(_gp)
mvhi r1, hi(_fbss)
ori r1, r1, lo(_fbss)
mvi r2, 0
mvhi r3, hi(_ebss)
ori r3, r3, lo(_ebss)
sub r3, r3, r1
/* calli memset */
mvi r1, 0
mvi r2, 0
mvi r3, 0
calli main
loopf:
bi loopf
applications/wrtd/rt/common/wrnode.ld
deleted
100644 → 0
View file @
cec1caf0
OUTPUT_FORMAT("elf32-lm32")
ENTRY(_start)
MEMORY
{
ram :
ORIGIN = 0x00000000,
LENGTH = 32768 - 2048
stack :
ORIGIN = 32768 - 2048,
LENGTH = 2048
smem :
ORIGIN = 0x40000000,
LENGTH = 8192
}
SECTIONS
{
.boot : { *(.boot) } > ram
.text : { *(.text .text.*) } > ram =0
.rodata : { *(.rodata .rodata.*) } > ram
.data : {
*(.data .data.*)
_gp = ALIGN(16) + 0x7ff0;
} > ram
.bss : {
_fbss = .;
*(.bss .bss.*)
*(COMMON)
_ebss = .;
} > ram
.smem : { *(.smem) } > smem
PROVIDE(_endram = ORIGIN(stack));
PROVIDE(_fstack = ORIGIN(stack) + LENGTH(stack) - 4);
}
PROVIDE(mprintf = pp_printf);
applications/wrtd/rt/common/wrnode.mk
deleted
100644 → 0
View file @
cec1caf0
# and don't touch the rest unless you know what you're doing.
CROSS_COMPILE_TARGET ?= lm32-elf-
INSTALL_PREFIX ?= .
CC = $(CROSS_COMPILE_TARGET)gcc
LD = $(CROSS_COMPILE_TARGET)ld
OBJDUMP = $(CROSS_COMPILE_TARGET)objdump
OBJCOPY = $(CROSS_COMPILE_TARGET)objcopy
SIZE = $(CROSS_COMPILE_TARGET)size
CFLAGS = -DWRNODE_RT -g -O3 -I. -I../common -I../../include -mmultiply-enabled -mbarrel-shift-enabled
OBJS += ../common/wrn-crt0.o ../common/vsprintf-xint.o ../common/printf.o ../common/rt-common.o ../common/loop-queue.o
LDSCRIPT = ../common/wrnode.ld
all: $(OUTPUT)
$(OUTPUT): $(LDSCRIPT) $(OBJS)
${CC} -o $(OUTPUT).elf -nostartfiles $(OBJS) -T $(LDSCRIPT) -lgcc -lc
${OBJCOPY} --remove-section .smem -O binary $(OUTPUT).elf $(OUTPUT).bin
${OBJDUMP} -S $(OUTPUT).elf > disasm.S
$(SIZE) $(OUTPUT).elf
clean:
rm -f $(OBJS) $(OUTPUT).bin
install:
cp $(OUTPUT).bin $(INSTALL_PREFIX)
applications/wrtd/rt/fd/Makefile
View file @
e3fd6f0e
OBJS
=
rt-fd.o
OBJS
:=
rt-fd.o
OBJS
+=
../common/loop-queue.o
OUTPUT
=
rt-fd
PATH_COMMON
=
../../../common/
EXTRA_CFLAGS
+=
-I
../../include
EXTRA_CFLAGS
+=
-I
../common
include
../common/wrnode.mk
include
$(PATH_COMMON)/rt/Makefile
applications/wrtd/rt/tdc/Makefile
View file @
e3fd6f0e
OBJS
=
rt-tdc.o
OBJS
:=
rt-tdc.o
OBJS
+=
../common/loop-queue.o
OUTPUT
=
rt-tdc
PATH_COMMON
=
../../../common/
EXTRA_CFLAGS
+=
-I
../../include
EXTRA_CFLAGS
+=
-I
../common
include
../common/wrnode.mk
include
$(PATH_COMMON)/rt/Makefile
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