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Mock Turtle
Commit f8575c46 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: update SPEC demo to use xwb_gn4124_core (with VHDL records for wishbone)

parent 27404fc9
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Showing with 38 additions and 64 deletions
hdl/syn/spec_mt_demo/spec_mt_demo.ucf
View file @ f8575c46
......@@ -149,6 +149,11 @@ NET "brd_button_i[0]" IOSTANDARD = "LVCMOS18";
NET "brd_button_i[1]" LOC = D21;
NET "brd_button_i[1]" IOSTANDARD = "LVCMOS18";
#----------------------------------------
# IOBs
#----------------------------------------
INST "cmp_gn4124_core/cmp_wrapped_gn4124/cmp_sync_l2p_rdy/sync0" IOB = FALSE;
#===============================================================================
# Timing constraints and exceptions
......@@ -168,7 +173,7 @@ TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
# GN4124
NET "gn_rst_n_i" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/rst_*" TIG;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
......@@ -183,8 +188,8 @@ NET "clk_125m_pllref" TNM_NET = clk_125m_pllref;
TIMEGRP "sys_clk" = "sys_clk_62_5" "clk_125m_pllref";
NET "cmp_gn4124_core/sys_clk" TNM_NET = pci_sys_clk;
NET "cmp_gn4124_core/io_clk" TNM_NET = pci_io_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_sys_clk;
NET "cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_io_clk;
TIMEGRP "pci_clk" = "pci_sys_clk" "pci_io_clk";
......
hdl/top/spec_mt_demo/spec_mt_demo.vhd
View file @ f8575c46
......@@ -129,8 +129,6 @@ architecture arch of spec_mt_demo is
signal rstlogic_arst : std_logic;
signal gn_rst_n_p : std_logic;
signal gn_wbadr : std_logic_vector(31 downto 0);
signal pllout_clk_sys : std_logic;
signal pllout_clk_fb_pllref : std_logic;
......@@ -241,70 +239,41 @@ begin -- architecture arch
irqs_i(3) => mt_notify_irq,
irq_master_o => vic_master_irq);
cmp_gn4124_core : gn4124_core
cmp_gn4124_core : xwb_gn4124_core
port map (
rst_n_a_i => gn_rst_n_i,
status_o => open,
p2l_clk_p_i => gn_p2l_clk_p_i,
p2l_clk_n_i => gn_p2l_clk_n_i,
p2l_data_i => gn_p2l_data_i,
p2l_dframe_i => gn_p2l_dframe_i,
p2l_valid_i => gn_p2l_valid_i,
p2l_rdy_o => gn_p2l_rdy_o,
p_wr_req_i => gn_p_wr_req_i,
p_wr_rdy_o => gn_p_wr_rdy_o,
rx_error_o => gn_rx_error_o,
vc_rdy_i => gn_vc_rdy_i,
l2p_clk_p_o => gn_l2p_clkp_o,
l2p_clk_n_o => gn_l2p_clkn_o,
l2p_data_o => gn_l2p_data_o,
l2p_dframe_o => gn_l2p_dframe_o,
l2p_valid_o => gn_l2p_valid_o,
l2p_edb_o => gn_l2p_edb_o,
l2p_rdy_i => gn_l2p_rdy_i,
l_wr_rdy_i => gn_l_wr_rdy_i,
p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
tx_error_i => gn_tx_error_i,
dma_irq_o => open,
irq_p_i => vic_master_irq,
irq_p_o => gn_gpio_b(1),
dma_reg_rst_n_i => rst_sys_n,
dma_reg_clk_i => clk_sys,
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_we_i => '0',
dma_reg_cyc_i => '0',
csr_rst_n_i => rst_sys_n,
csr_clk_i => clk_sys,
csr_adr_o => gn_wbadr,
csr_dat_o => cnx_master_out(c_MASTER_PCIE).dat,
csr_sel_o => cnx_master_out(c_MASTER_PCIE).sel,
csr_stb_o => cnx_master_out(c_MASTER_PCIE).stb,
csr_we_o => cnx_master_out(c_MASTER_PCIE).we,
csr_cyc_o => cnx_master_out(c_MASTER_PCIE).cyc,
csr_dat_i => cnx_master_in(c_MASTER_PCIE).dat,
csr_ack_i => cnx_master_in(c_MASTER_PCIE).ack,
csr_stall_i => cnx_master_in(c_MASTER_PCIE).stall,
csr_err_i => cnx_master_in(c_MASTER_PCIE).err,
csr_rty_i => cnx_master_in(c_MASTER_PCIE).rty,
dma_rst_n_i => rst_sys_n,
dma_clk_i => clk_sys,
dma_dat_i => (others => '0'),
dma_ack_i => '1',
dma_stall_i => '0',
dma_err_i => '0',
dma_rty_i => '0');
rst_n_a_i => gn_rst_n_i,
status_o => open,
p2l_clk_p_i => gn_p2l_clk_p_i,
p2l_clk_n_i => gn_p2l_clk_n_i,
p2l_data_i => gn_p2l_data_i,
p2l_dframe_i => gn_p2l_dframe_i,
p2l_valid_i => gn_p2l_valid_i,
p2l_rdy_o => gn_p2l_rdy_o,
p_wr_req_i => gn_p_wr_req_i,
p_wr_rdy_o => gn_p_wr_rdy_o,
rx_error_o => gn_rx_error_o,
vc_rdy_i => gn_vc_rdy_i,
l2p_clk_p_o => gn_l2p_clkp_o,
l2p_clk_n_o => gn_l2p_clkn_o,
l2p_data_o => gn_l2p_data_o,
l2p_dframe_o => gn_l2p_dframe_o,
l2p_valid_o => gn_l2p_valid_o,
l2p_edb_o => gn_l2p_edb_o,
l2p_rdy_i => gn_l2p_rdy_i,
l_wr_rdy_i => gn_l_wr_rdy_i,
p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
tx_error_i => gn_tx_error_i,
dma_irq_o => open,
irq_p_i => vic_master_irq,
irq_p_o => gn_gpio_b(1),
wb_master_clk_i => clk_sys,
wb_master_rst_n_i => rst_sys_n,
wb_master_i => cnx_master_in(c_MASTER_PCIE),
wb_master_o => cnx_master_out(c_MASTER_PCIE));
-- drive unused GN GPIO output
gn_gpio_b(0) <= '0';
-- "translating" word addressing of Gennum module into byte addressing
cnx_master_out(c_MASTER_PCIE).adr(1 downto 0) <= (others => '0');
cnx_master_out(c_MASTER_PCIE).adr(18 downto 2) <= gn_wbadr(16 downto 0);
cnx_master_out(c_MASTER_PCIE).adr(31 downto 19) <= (others => '0');
U_Mock_Turtle : mock_turtle_core
generic map (
g_CONFIG => c_MT_CONFIG,
......
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