1st version evas; major changes in units: wf_rx_osc and wf_rx

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@56 7f0067c9-7624-46c7-bd39-3fb5400c0213

1st version evas; major changes in units: wf_rx_osc and wf_rx
git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@56 7f0067c9-7624-46c7-bd39-3fb5400c0213
02c4dba5 · egousiou · 3f7da556 · 02c4dba5 · 02c4dba5 · 02c4dba5
Commit 02c4dba5 authored Aug 03, 2010 by egousiou
14 changed files
--- a/DualClkRAM.vhd
+++ b/DualClkRAM.vhd
--- a/deglitcher.vhd
+++ b/deglitcher.vhd
@@ -65,23 +65,30 @@ use IEEE.NUMERIC_STD.all;    --! conversion functions
 entity deglitcher is
    Generic (C_ACULENGTH : integer := 10);
    Port ( uclk_i : in  STD_LOGIC;
-           d_i : in  STD_LOGIC;
+           rx_data_i : in  STD_LOGIC;
-           d_o : out  STD_LOGIC;
+           clk_bit_180_p_i : in std_logic;
+           rx_data_filtered_o : out  STD_LOGIC;
           carrier_p_i : in  STD_LOGIC;
-           d_ready_p_o : out  STD_LOGIC);
+           sample_manch_bit_p_o : out  STD_LOGIC;
+           sample_bit_p_o : out  STD_LOGIC
+         );
 end deglitcher;
 architecture Behavioral of deglitcher is
 signal s_onesc : signed(C_ACULENGTH - 1 downto 0);
+signal s_rx_data_filtered_o: STD_LOGIC;
+signal s_d_d: std_logic_vector(2 downto 0);
+signal s_rx_data_filtered_d : std_logic;
 begin
 process(uclk_i)
 begin
 if rising_edge(uclk_i) then
-	if carrier_p_i = '1' then
+	if carrier_p_i = '1' then -- 4 clock ticks after a transition of manchestered input
 		s_onesc <= to_signed(0,s_onesc'length);
-	elsif  d_i = '1' then
+	elsif  rx_data_i = '1' then
 		s_onesc <= s_onesc - 1;
 	else
 		s_onesc <= s_onesc + 1;
@@ -89,14 +96,68 @@ if rising_edge(uclk_i) then
 end if;
 end process;
 process(uclk_i)
-begin if rising_edge(uclk_i) then
+  begin
-	if carrier_p_i = '1' then 		
+    if rising_edge(uclk_i) then
-	   d_o <= s_onesc(s_onesc'left);
+	  if carrier_p_i = '1' then 		
-	end if;
+	    s_rx_data_filtered_o <= s_onesc(s_onesc'left);
-	d_ready_p_o <= carrier_p_i;
+      end if;
-	end if;
+      s_rx_data_filtered_d <= s_rx_data_filtered_o; 
+  end if;
 end process;
+      sample_manch_bit_p_o <= carrier_p_i;  
+      sample_bit_p_o <= clk_bit_180_p_i;
+--process(carrier_p_i)
+  --begin
+    --if rising_edge(carrier_p_i) then
+	--   s_rx_data_filtered_o <= s_onesc(s_onesc'left);
+   -- elsif falling_edge(carrier_p_i) then
+   --   s_rx_data_filtered_o <= s_onesc(s_onesc'left); 
+   -- end if;
+ -- end process;
+--process(uclk_i)
+  --begin
+    --if rising_edge(uclk_i) then
+     -- sample_manch_bit_p_o <= carrier_p_i;	
+     -- sample_bit_p_o <= clk_bit_180_p_i; ---- delay on clk_bit_180_p_i, so that sample_bit is 1 clock tick before rx_data_filtered_o
+    --  s_rx_data_filtered_o_1 <= s_rx_data_filtered_o_0;
+    --  s_rx_data_filtered_o_0 <= s_rx_data_filtered_o; 
+ -- end if;
+--end process;
+ rx_data_filtered_o <= s_rx_data_filtered_d;
 end Behavioral;
--- a/dpblockram_clka_rd_clkb_wr_syn.vhd
+++ b/dpblockram_clka_rd_clkb_wr_syn.vhd
-------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------- 
 --! @file dpblockram.vhd
-------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------- 
 --! Standard library
 library IEEE;
 --! Standard packages
 use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
 use IEEE.NUMERIC_STD.all;    --! conversion functions
+--------------------------------------------------------------------------------------------------- 
----------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------- 
----------------------------------------------------------------------------
 -- --
 -- CERN, BE  --
 -- --
-------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------- 
 --
 -- unit name: dpblockram.vhd
 --
--! @brief The dpblockram implements a template for a true dual port ram clocked on both ports by the same clock.
+--! @brief The unit provides transparently to the outside world the memory triplication and all the
+--! associated actions.
+--!
 --! 
 --! @author <Pablo Alvarez(pablo.alvarez.sanchez@cern.ch)>
 --
 --! @date 24\01\2009
 --
 --! @version 1
--
+--!
--! @details
+--! @details The component DualClkRam is triplicated.
+--! Each incoming byte is written at the same position in the three memories, whereas
+--! each outgoing byte is the outcome of a majority voting system from the three memories.
 --!
 --! <b>Dependencies:</b>\n
--! 
+--! DualClkRAM.vhd \n
 --!
 --! <b>References:</b>\n
--! <reference one> \n
--! <reference two>
 --!
 --! <b>Modified by:</b>\n
 --! Author: Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
-------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------- 
--! \n\n<b>Last changes:</b>\n
+--! @todo 
--! 24\01\2009 paas header included\n
--! <extended description>
-------------------------------------------------------------------------------
--! @todo Adapt vhdl sintax to ohr standard\n
--! <another thing to do> \n
 --
-------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------- 
 entity dpblockram_clka_rd_clkb_wr is
-  generic (c_dl : integer := 8; 		-- Length of the data word 
+  generic (c_data_length : integer := 8; 		-- 8: length of data word 
-           c_al : integer := 9);        -- Number of words
+           c_addr_length : integer := 9);       -- 2^9: memory depth
-                                        -- 'nw' has to be coherent with 'c_al'
  port (
-        clka_i  : in std_logic; 			-- Global Clock
+        clk_A_i  :     in std_logic;
-        aa_i : in std_logic_vector(c_al - 1 downto 0);
+        addr_A_i :     in std_logic_vector(c_addr_length - 1 downto 0);
-        da_o : out std_logic_vector(c_dl -1 downto 0);
-        clkb_i : in std_logic;
+        clk_B_i :      in std_logic;
-        ab_i : in std_logic_vector(c_al - 1 downto 0);
+        addr_B_i :     in std_logic_vector(c_addr_length - 1 downto 0);
-        db_i : in std_logic_vector(c_dl - 1 downto 0);
+        data_B_i :     in std_logic_vector(c_data_length - 1 downto 0);
-        web_i : in std_logic);
+        write_en_B_i : in std_logic;
+       data_A_o :      out std_logic_vector(c_data_length -1 downto 0)
+);
 end dpblockram_clka_rd_clkb_wr; 
--library synplify;
--use synplify.attributes.all;
 architecture syn of dpblockram_clka_rd_clkb_wr is 
-component DualClkRam is 
+---------------------------------------------------------------------------------------------------
-    port( DINA : in std_logic_vector(7 downto 0); DOUTA : out 
+--!@brief: component DualClkRam declaration
-        std_logic_vector(7 downto 0); DINB : in std_logic_vector(
+  component DualClkRam is 
-        7 downto 0); DOUTB : out std_logic_vector(7 downto 0); 
+    port(
-        ADDRA : in std_logic_vector(8 downto 0); ADDRB : in 
+    DINA :   in std_logic_vector(7 downto 0);  
-        std_logic_vector(8 downto 0);RWA, RWB, BLKA, BLKB, CLKA, 
+    ADDRA :  in std_logic_vector(8 downto 0);
-        CLKB, RESET : in std_logic) ;
+    RWA :    in std_logic;                   
-end component DualClkRam;
+    CLKA :   in std_logic;                 
+    DINB :   in std_logic_vector(7 downto 0);  
+    ADDRB :  in std_logic_vector(8 downto 0); 
+    RWB :    in std_logic;                   
+    CLKB :   in std_logic;                   
+    RESETn : in std_logic;                  
+    DOUTA :  out std_logic_vector(7 downto 0); 
+    DOUTB :  out std_logic_vector(7 downto 0)  
+    );
+  end component DualClkRam;
+---------------------------------------------------------------------------------------------------
-signal s_zeros_da : std_logic_vector(7 downto 0);
 signal zero : std_logic;
 signal one : std_logic;
-signal s_rw : std_logic;
+signal s_rwB : std_logic;
-type t_da_o_array is array (natural range <>) of std_logic_vector(7 downto 0);
+signal s_zeros : std_logic_vector(7 downto 0);
-signal da_o_array : t_da_o_array(0 to 2);
+type t_data_o_A_array is array (natural range <>) of std_logic_vector(7 downto 0);
+signal data_o_A_array : t_data_o_A_array(0 to 2); --will keep the DOUTA of each one of the memories
+--------------------------------------------------------------------------------------------------- 
 begin 
-s_zeros_da <= (others => '0');
 zero <= '0';
 one <= '1';
-s_rw <= not web_i;
+s_zeros <= (others => '0');
+s_rwB <= not write_en_B_i;
+--------------------------------------------------------------------------------------------------- 
+--!@brief: memory triplication
+--! The component DualClkRam is generated three times.
+--! Port A is used for reading, port B for writing.
+--! The input DINB is written in the same position in the 3 memories.
+--! The output DOUTA from each memory is kept in the array data_o_A_array.
+memory_triplication: for I in 0 to 2 generate 
-G: for I in 0 to 2 generate 
 UDualClkRam : DualClkRam  
-    port map ( DINA => s_zeros_da,
+   port map ( DINA   => s_zeros,
-     DOUTA => da_o_array(I),
+               ADDRA  => addr_A_i,
-     DINB => db_i,
+                RWA    => one, 
-     DOUTB  => open,
+               CLKA   => clk_A_i, 
-     ADDRA  => aa_i,
-     ADDRB  => ab_i, 
+               DINB   => data_B_i,
-     RWA  => one, 
+               ADDRB  => addr_B_i, 
-     RWB  => s_rw, 
+               RWB    => s_rwB, 
-     BLKA  => zero, 
+               CLKB   => clk_B_i, 
-     BLKB  => zero, 
-     CLKA  => clka_i, 
+               RESETn => one,
-     CLKB  => clkb_i, 
-     RESET  => one) ;
+               DOUTA  => data_o_A_array(I),
+               DOUTB  => open) ;
 end generate;
-process(da_o_array)
+--UDualClkRam : DualClkRam  
-   begin
+--    port map ( DINA   => s_zeros,
-         da_o <= (da_o_array(0) and da_o_array(1)) or (da_o_array(1) and da_o_array(2)) or (da_o_array(2) and da_o_array(0));
+--               ADDRA  => addr_A_i,
-end process;
+--               RWA    => one, 
+--               CLKA   => clk_A_i, 
+--
+--               DINB   => data_B_i,
+--               ADDRB  => addr_B_i, 
+--               RWB    => s_rwB, 
+--               CLKB   => clk_B_i, 
+--
+--               RESETn => one,
+--
+--               DOUTA  => data_A_o,
+--               DOUTB  => open) ;
+--------------------------------------------------------------------------------------------------- 
+--!@brief: majority voter after a memory reading
+--! when a reading is done from the memory, the process majority_voter considers internally the
+--! outputs of the three memories and defines as final output, the majority of the three.
+majority_voter: process (data_o_A_array)
+  begin
+    data_A_o <= (data_o_A_array(0) and data_o_A_array(1)) or
+               (data_o_A_array(1) and data_o_A_array(2)) or
+               (data_o_A_array(2) and data_o_A_array(0));
+end process;
 end syn;
\ No newline at end of file
--- a/nanofip.vhd
+++ b/nanofip.vhd
--- a/reset_logic.vhd
+++ b/reset_logic.vhd
@@ -93,7 +93,7 @@ begin
 process(s_rstin_d,var_i)
 begin
-if (var_i = c_var_array(c_var_reset_pos).var) then 
+if (var_i = c_var_array(c_reset_var_pos).var) then 
 s_reload_rst_c <= '1';
 else
 s_reload_rst_c <=   s_rstin_d(s_rstin_d'left);

--- a/wf_consumed_vars.vhd
+++ b/wf_consumed_vars.vhd
--- a/wf_crc.vhd
+++ b/wf_crc.vhd
@@ -59,11 +59,9 @@ generic(
 port (
   uclk_i    : in std_logic; --! User Clock
   rst_i     : in std_logic;
+    start_p_i : in std_logic;
-   start_p_i : in std_logic;
-	d_i       : in std_logic;
 	d_rdy_p_i     : in std_logic;
-	data_fcs_sel_n : in std_logic;
+	d_i       : in std_logic;
 	crc_o     : out  std_logic_vector(c_poly_length - 1 downto 0);
 	crc_rdy_p_o : out std_logic;
 	crc_ok_p : out std_logic
@@ -88,17 +86,17 @@ constant c_poly :  std_logic_vector(c_poly_length - 1 downto 0)      := "0001110
 constant c_check_mask : std_logic_vector(c_poly_length - 1 downto 0) := "0001110001101011";
 signal s_q, s_q_nx  : std_logic_vector(c_poly_length - 1 downto 0);
 signal s_crc_rdy_p : std_logic;
 signal s_d : std_logic;
 begin
 s_d <= d_i;
 G: for I in 0 to c_poly'left generate
   G0: if I = 0 generate
-      s_q_nx(I) <= data_fcs_sel_n and (( s_d) xor s_q(s_q'left));
+      s_q_nx(I) <= (( s_d) xor s_q(s_q'left));
   end generate;
   G1: if I > 0 generate
-      s_q_nx(I) <= s_q(I-1) xor (c_poly(I) and data_fcs_sel_n and (s_d xor s_q(s_q'left)));
+      s_q_nx(I) <= s_q(I-1) xor (c_poly(I) and (s_d xor s_q(s_q'left)));      
   end generate;
 end generate;

--- a/wf_engine_control.vhd
+++ b/wf_engine_control.vhd
--- a/wf_package.vhd
+++ b/wf_package.vhd
--- a/wf_produced_vars.vhd
+++ b/wf_produced_vars.vhd
--- a/wf_rx.vhd
+++ b/wf_rx.vhd
--- a/wf_rx_osc.vhd
+++ b/wf_rx_osc.vhd
--- a/wf_tx.vhd
+++ b/wf_tx.vhd
--- a/wf_tx_rx.vhd
+++ b/wf_tx_rx.vhd
@@ -70,15 +70,14 @@ entity wf_tx_rx is
    uclk_i    : in std_logic; --! User Clock
    rst_i     : in std_logic;
-    start_send_p_i  : in std_logic;
+    start_produce_p_i  : in std_logic;
    request_byte_p_o : out std_logic;
    byte_ready_p_i : in std_logic;
    byte_i : in std_logic_vector(7 downto 0);
    last_byte_p_i : in std_logic;
--   clk_fixed_carrier_p_o : out std_logic;
+    tx_data_o : out std_logic;
-    d_o : out std_logic;
+    tx_enable_o : out std_logic;
-    d_e_o : out std_logic;
    d_clk_o : out std_logic;
    d_a_i : in std_logic;
@@ -90,7 +89,7 @@ entity wf_tx_rx is
    last_byte_p_o : out std_logic;
    fss_decoded_p_o : out std_logic;
    code_violation_p_o : out std_logic;
-    crc_bad_p_o : out std_logic;
+    crc_wrong_p_o : out std_logic;
    crc_ok_p_o : out std_logic
    );
@@ -113,9 +112,9 @@ architecture rtl of wf_tx_rx is
  signal s_clk_fixed_carrier_p : std_logic;
  signal s_d_filtered : std_logic;
  signal s_d_ready_p : std_logic;
-  signal s_load_phase : std_logic;   
+  signal s_first_fe : std_logic;   
  signal s_clk_carrier_p : std_logic;
-  signal s_clk_bit_180_p  : std_logic;
+  signal s_clk_bit_180_p, s_sample_bit_p, s_sample_manch_bit_p  : std_logic;
  signal s_edge_window, edge_180_window : std_logic;
  signal s_d_edge : std_logic;   
  signal s_clk_fixed_carrier_p_d : std_logic_vector(C_CLKFCDLENTGTH - 1 downto 0); 
@@ -140,15 +139,15 @@ begin
    PORT MAP(
      uclk_i => uclk_i,
      rst_i => rst_i,
-      start_send_p_i => start_send_p_i,
+      start_produce_p_i => start_produce_p_i,
      request_byte_p_o => request_byte_p_o,
      byte_ready_p_i => byte_ready_p_i,
      byte_i => byte_i,
      last_byte_p_i => last_byte_p_i,
 --      clk_fixed_carrier_p_i => s_clk_fixed_carrier_p,
-      clk_fixed_carrier_p_d_i => s_clk_fixed_carrier_p_d,
+      tx_clk_p_buff_i => s_clk_fixed_carrier_p_d,
-      d_o => d_o,
+      tx_data_o => tx_data_o,
-      d_e_o => d_e_o
+      tx_enable_o => tx_enable_o
      );
@@ -162,16 +161,16 @@ begin
      fss_decoded_p_o => fss_decoded_p_o,
      crc_ok_p_o => crc_ok_p_o,
-      d_fe_i => s_d_fe,
+      rx_data_f_edge_i => s_d_fe,
-      d_re_i => s_d_re,
+      rx_data_r_edge_i => s_d_re,
-      d_filtered_i => s_d_filtered,
+      rx_data_filtered_i => s_d_filtered,
-      s_d_ready_p_i => s_d_ready_p,
+      sample_manch_bit_p_i => s_sample_manch_bit_p,
-      load_phase_o => s_load_phase,
+      wait_d_first_f_edge_o=> s_first_fe,
-      clk_bit_180_p_i => s_clk_bit_180_p,
+      sample_bit_p_i => s_sample_bit_p,
-      edge_window_i => s_edge_window,
+      signif_edge_window_i => s_edge_window,
-      edge_180_window_i => edge_180_window
+      adjac_bits_window_i => edge_180_window
      );
@@ -179,16 +178,17 @@ begin
  uwf_rx_osc :wf_rx_osc
-    generic map(C_OSC_LENGTH => 20,
+    generic map(C_COUNTER_LENGTH => 7,
-                C_QUARTZ_PERIOD => 25.0,
+                C_QUARTZ_PERIOD => 24.8,
                C_CLKFCDLENTGTH => C_CLKFCDLENTGTH)
    port map(
      uclk_i   => uclk_i, --! User Clock
      rst_i   => rst_i, 
-      d_edge_i   => s_d_fe,
+      d_edge_i => s_d_edge,      
-      load_phase_i   => s_load_phase, 
+      rx_data_f_edge_i   => s_d_fe,
+      wait_d_first_f_edge_i   => s_first_fe, 
      --! Bit rate         \n
@@ -198,31 +198,27 @@ begin
      --! 11: reserved, do not use
      rate_i   => rate_i,  --! Bit rate
-      clk_fixed_carrier_p_o     => s_clk_fixed_carrier_p,
+      tx_clk_p_buff_o   => s_clk_fixed_carrier_p_d,
-      clk_fixed_carrier_p_d_o   => s_clk_fixed_carrier_p_d,
+      tx_clk_o   => d_clk_o,
-      clk_fixed_carrier_o   => d_clk_o,
-      clk_carrier_p_o     => s_clk_carrier_p,
+      rx_manch_clk_p_o     => s_clk_carrier_p,
-      clk_carrier_180_p_o => open,
-      clk_bit_p_o      => open,
+      rx_bit_clk_p_o  => s_clk_bit_180_p, 
-      clk_bit_90_p_o   => open, 
-      clk_bit_180_p_o  => s_clk_bit_180_p, 
-      clk_bit_270_p_o  => open, 
-      edge_window_o  => s_edge_window,
+      rx_signif_edge_window_o  => s_edge_window,
-      edge_180_window_o => edge_180_window,
+      rx_adjac_bits_window_o => edge_180_window
-      phase_o  => open
      );
  Udeglitcher : deglitcher 
    generic map (C_ACULENGTH => 10)
    Port map( uclk_i => uclk_i,
-              d_i => s_d_d(2),
+              rx_data_i => s_d_d(2),
-              d_o => s_d_filtered,
+              rx_data_filtered_o => s_d_filtered,
+              clk_bit_180_p_i => s_clk_bit_180_p,
              carrier_p_i  => s_clk_carrier_p,
-              d_ready_p_o => s_d_ready_p);
+              sample_manch_bit_p_o => s_sample_manch_bit_p,
+              sample_bit_p_o => s_sample_bit_p
+              );
 end architecture rtl;