manch code violations checked at reception (wf_manch_code_viol_check removed)

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@194 7f0067c9-7624-46c7-bd39-3fb5400c0213

manch code violations checked at reception (wf_manch_code_viol_check removed)
git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@194 7f0067c9-7624-46c7-bd39-3fb5400c0213
101d142c · egousiou · e1bd8403 · 101d142c · e1bd8403 · 101d142c
Commit 101d142c authored Mar 21, 2011 by egousiou
29 changed files
--- a/DualClkRAM.vhd
+++ b/DualClkRAM.vhd
@@ -180,7 +180,7 @@ architecture RAM4K9 of DualClkRAM is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/NanoFip.pdc
+++ b/NanoFip.pdc
--- a/nanofip.vhd
+++ b/nanofip.vhd
@@ -276,6 +276,12 @@ entity nanofip is
  var3_rdy_o : out std_logic;                    --! Signals that the var 3 can safely be written
+------------------------------************************----------------------------
+TP16 : out std_logic;
+TP15 : out std_logic;
+TP14 : out std_logic;
+------------------------------************************----------------------------
  --  User Interface, WISHBONE Slave
  dat_o      : out std_logic_vector(15 downto 0);--! dat_o(7 downto 0) : WISHBONE data out, memory mode
@@ -294,6 +300,20 @@ end entity nanofip;
 architecture struc of nanofip is
+---------------------------------------------------------------------------------------------------
+--                                    Triple Module Redundancy                                   --
+---------------------------------------------------------------------------------------------------
+ --attribute syn_radhardlevel          : string;                                                   --
+ --attribute syn_radhardlevel of struc : architecture is "tmr";                                    --
+---------------------------------------------------------------------------------------------------
  -- WF_reset_unit iutputs
  signal s_nfip_intern_rst, s_wb_rst                                                   : std_logic;
  -- WF_consumption outputs
@@ -309,7 +329,7 @@ architecture struc of nanofip is
  signal s_tx_last_byte_p                                                              : std_logic;
  -- WF_engine_control outputs
  signal s_tx_start_p, s_tx_request_byte_p, s_byte_request_accepted_p                  : std_logic;
-  signal s_rx_rst_p                                                                    : std_logic;
+  signal s_rx_rst                                                                      : std_logic;
  signal s_var                                                                         : t_var;
  signal s_prod_data_lgth, s_prod_cons_byte_index                  : std_logic_vector (7 downto 0);
  -- WF_model_constr_dec outputs
@@ -319,11 +339,18 @@ architecture struc of nanofip is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin
+------------------------------************************----------------------------
+TP16 <= '1' when s_var = var_1 else '0';
+TP15 <= s_assert_RSTON_p;
+TP14 <= s_rx_fss_crc_fes_manch_ok_p;
+------------------------------************************----------------------------
 ---------------------------------------------------------------------------------------------------
 --                                         WF_reset_unit                                         --
 ---------------------------------------------------------------------------------------------------
@@ -383,7 +410,7 @@ begin
    rate_i                      => rate_i,
    fd_rxd_a_i                  => fd_rxd_i,
    nfip_rst_i                  => s_nfip_intern_rst,
-    rx_rst_p_i                  => s_rx_rst_p,
+    rx_rst_i                    => s_rx_rst,
  -------------------------------------------------------------
    rx_byte_o                   => s_rx_byte,
    rx_byte_ready_p_o           => s_rx_byte_ready_p,
@@ -481,7 +508,7 @@ begin
    tx_last_byte_p_o            => s_tx_last_byte_p,
    prod_cons_byte_index_o      => s_prod_cons_byte_index,
    prod_data_lgth_o            => s_prod_data_lgth,
-    rx_rst_p_o                  => s_rx_rst_p);
+    rx_rst_o                    => s_rx_rst);
  -------------------------------------------------------------
    var1_rdy_o <= s_var1_rdy;

--- a/wf_DualClkRAM_clka_rd_clkb_wr.vhd
+++ b/wf_DualClkRAM_clka_rd_clkb_wr.vhd
@@ -100,14 +100,14 @@ end WF_DualClkRAM_clka_rd_clkb_wr;
 --=================================================================================================
 architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
-  type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
+--  type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
-  signal s_data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
+--  signal s_data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
  signal s_one, s_rwB     : std_logic;
  signal s_zeros          : std_logic_vector (7 downto 0);
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin
@@ -122,7 +122,7 @@ begin
 --! The input DINB is written in the same position in the 3 memories.
 --! The output DOUTA from each memory is kept in the array s_data_o_A_array.
-  G_memory_triplication: for I in 0 to 2 generate
+--  G_memory_triplication: for I in 0 to 2 generate
    UDualClkRam : DualClkRam
    port map (
@@ -138,18 +138,18 @@ begin
      RESETn => s_one,
-      DOUTA  => s_data_o_A_array(I),
+      DOUTA  => data_porta_o, --s_data_o_A_array(I),
      DOUTB  => open);
-  end generate;
+--  end generate;
 ---------------------------------------------------------------------------------------------------
 --!@brief Combinatorial Majority_Voter
-Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
+--Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
-                                (s_data_o_A_array(1) and s_data_o_A_array(2)) or
+--                                (s_data_o_A_array(1) and s_data_o_A_array(2)) or
-                                (s_data_o_A_array(2) and s_data_o_A_array(0));
+--                                (s_data_o_A_array(2) and s_data_o_A_array(0));
 end syn;
 --=================================================================================================

--- a/wf_bits_to_txd.vhd
+++ b/wf_bits_to_txd.vhd
@@ -115,7 +115,7 @@ architecture rtl of WF_bits_to_txd is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_cons_bytes_processor.vhd
+++ b/wf_cons_bytes_processor.vhd
@@ -163,7 +163,7 @@ architecture rtl of WF_cons_bytes_processor is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_cons_outcome.vhd
+++ b/wf_cons_outcome.vhd
@@ -43,6 +43,9 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --!              o rst_nFIP_and_FD_p and assert_RSTON_p, that are inputs to the WF_reset_unit.
 --!
 --!
+--!            Note: The Length byte is considered "correct" if it is coherent with the actual
+--!                  number of bytes received in the frame.
+--!
 --!            Reminder:
 --!
 --!            Consumed RP_DAT frame structure :
@@ -86,6 +89,7 @@ use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
 --!     -> 02/2010  v0.05  EG  Added here functionality of wf_cons_frame_validator
 --!                            Bug on var1_rdy, var2_rdy generation corrected (the s_varX_received
 --!                            was always set to 1!)
+--!                            Added check of Ctrl byte for rtler
 --
 ---------------------------------------------------------------------------------------------------
 --
@@ -158,12 +162,12 @@ end entity WF_cons_outcome;
 --=================================================================================================
 architecture rtl of WF_cons_outcome is
-  signal s_cons_frame_ok_p                 : std_logic;
+  signal s_cons_frame_ok_p, s_var1_received, s_var2_received                 : std_logic;
  signal s_rst_nfip_and_fd, s_assert_rston : std_logic;
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin
@@ -181,7 +185,8 @@ begin
 --! Length, the 2 CRC and the FES bytes (and counting starts from 0!).
 -- --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- -- --
 --! The same process is also used for the generation of the of the nanoFIP status byte, bit 4, that
--! indicates a received PDU_TYPE or Length byte error in a consumed RP_DAT frame.
+--! indicates a received Control or PDU_TYPE byte error or a Length byte incoherency in a consumed 
+--! RP_DAT frame.
 --! Note: The end of a frame is marked by either the signal rx_fss_crc_fes_manch_ok_p_i or by the
 --! rx_crc_or_manch_wrong_p_i.
@@ -189,25 +194,28 @@ begin
  begin
    if rising_edge (uclk_i) then
      if nfip_rst_i = '1' then
-        s_cons_frame_ok_p <= '0';
+        s_cons_frame_ok_p          <= '0';
+        nfip_status_r_tler_p_o     <= '0';
      else
        if (var_i = var_1) or (var_i = var_2) or (var_i = var_rst) then -- only consumed RP_DATs
-          --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --  --  --
+          --  --  --  --  --  --  --  --  -- --  --  -- --  --  --  --  --  --  --  --  --  --  --
          if (rx_fss_crc_fes_manch_ok_p_i = '1')            and         -- FSS CRC FES Manch. check
             (cons_ctrl_byte_i = c_RP_DAT_CTRL_BYTE)        and         -- CTRL byte check
             (cons_pdu_byte_i  = c_PROD_CONS_PDU_TYPE_BYTE) and         -- PDU_TYPE byte check
             (unsigned(rx_byte_index_i ) = (unsigned(cons_lgth_byte_i) + 5)) then --LGTH byte check
-            s_cons_frame_ok_p <= '1';
+            s_cons_frame_ok_p      <= '1';
          else
-            s_cons_frame_ok_p <= '0';
+            s_cons_frame_ok_p      <= '0';
          end if;
-          --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --  --  --
+          --  --  --  --  --  --  --  --  -- --  --  -- --  --  --  --  --  --  --  --  --  --  --
-          if ((rx_fss_crc_fes_manch_ok_p_i = '1') or (rx_crc_or_manch_wrong_p_i = '1')) and -- end of frame
+          if ((rx_fss_crc_fes_manch_ok_p_i = '1') or (rx_crc_or_manch_wrong_p_i = '1')) and-- end of frame
-              ((cons_pdu_byte_i /= c_PROD_CONS_PDU_TYPE_BYTE)                           or  -- PDU_TYPE byte check
+              ((cons_ctrl_byte_i = c_RP_DAT_CTRL_BYTE)                                  or -- CTRL byte check
-              (unsigned(rx_byte_index_i ) /= (unsigned(cons_lgth_byte_i) + 5))) then        -- LGTH byte check
+              ((cons_pdu_byte_i /= c_PROD_CONS_PDU_TYPE_BYTE)                           or -- PDU_TYPE byte check
+              (unsigned(rx_byte_index_i ) /= (unsigned(cons_lgth_byte_i) + 5)))) then      -- LGTH byte check
            nfip_status_r_tler_p_o <= '1';
          else
@@ -249,18 +257,22 @@ begin
  --! VAR2_RDY (for broadcast consumed vars): stays always deasserted.
--! Note: A correct consumed RP_DAT frame is signaled by the s_cons_frame_ok_p, whereas a correct
+--! Note: A correct consumed RP_DAT frame is signaled by the s_cons_frame_ok_p, which arrives upon
--! ID_DAT frame along with the variable it contained is signaled by the var_i.
+--! FES detection. A correct ID_DAT frame along with the variable it contained is signaled by the
--! For consumed variables, var_i gets its value (var_1, var_2, var_rst) after the reception of a
+--! var_i. The signal var_i gets its value (var_1, var_2, var_rst) after the reception of a correct
--! correct ID_DAT frame and of a correct FSS of the corresponding RP_DAT frame and it retains it
+--! ID_DAT and of a correct RP_DAT FSS; var_i retains its value until the FES detectionon of the
--! until the end of the reception.
+--! RP_DAT frame.
+--!
+--! frames          : ______[ID_DAT,var_1]____[......RP_DAT......]________________[ID_DAT,var_1]___
+--! cons_frame_ok_p : ___________________________________________|-|_______________________________
+--! var_i           :       var_whatever      > <      var_1       > <       var_whatever                                                   
  VAR_RDY_Generation: process (uclk_i)
  begin
    if rising_edge (uclk_i) then
      if nfip_rst_i = '1' then
-        var1_rdy_o          <= '0';
+        var1_rdy_o   <= '0';
-        var2_rdy_o          <= '0';
+        var2_rdy_o   <= '0';
      else
@@ -297,8 +309,6 @@ begin
    end if;
  end process;
 ---------------------------------------------------------------------------------------------------
 --!@ brief: Generation of the signals rst_nfip_and_fd : signals that the 1st byte of a consumed
 --!                                                     reset var contains the station address

--- a/wf_consumption.vhd
+++ b/wf_consumption.vhd
@@ -202,7 +202,7 @@ architecture struc of WF_consumption is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_crc.vhd
+++ b/wf_crc.vhd
@@ -110,7 +110,7 @@ architecture rtl of WF_crc is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_decr_counter.vhd
+++ b/wf_decr_counter.vhd
@@ -90,11 +90,12 @@ end entity WF_decr_counter;
 --=================================================================================================
 architecture rtl of WF_decr_counter is
-  signal s_counter : unsigned (g_counter_lgth-1 downto 0);
+  signal s_counter_is_zero : std_logic;
+  signal s_counter         : unsigned (g_counter_lgth-1 downto 0);
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin
@@ -116,16 +117,19 @@ begin
          s_counter <= s_counter - 1;
        end if;
+        counter_is_zero_o <= s_counter_is_zero; -- for slack reasons, especially for the
+                                                -- 21 bits "session_timeout" counters
      end if;
    end if;
  end process;
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  -- Concurrent assignments for the output signals
+  -- Concurrent assignments 
  counter_o         <= s_counter;
-  counter_is_zero_o <= '1' when s_counter = to_unsigned(0,s_counter'length) else '0';
+  s_counter_is_zero <= '1' when s_counter = to_unsigned(0,s_counter'length) else '0';
 end architecture rtl;

--- a/wf_engine_control.vhd
+++ b/wf_engine_control.vhd
@@ -97,12 +97,11 @@ use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
 --!                         rx_byte_ready_p_o removed cleaning-up+commenting
 --!     02/2011  v0.05  EG  Independant timeout counter added; time counter 18 digits instead of 15
 --!                         id_dat_frame_ok: corrected mistake if rx_fss_crc_fes_manch_ok_p not
--!                         activated
+--!                         activated; rx reset during production (rx_rst_o)
 --
 ---------------------------------------------------------------------------------------------------
 --
--! @todo  -> could add an extra time counter (on top of the more complicated bytes counters) that
+--! @todo
--!           after 134*8 transmission periods can reset tx and rx
 --!
 ---------------------------------------------------------------------------------------------------
@@ -172,10 +171,9 @@ entity WF_engine_control is
    -- Signals to the WF_consumption
    -- Signal to the WF_rx_deserializer
-    rx_rst_p_o                 : out std_logic;--!if a FES hasn't arrived after 8 bytes of an ID_DAT
+    rx_rst_o                   : out std_logic; --! reset during production or
-                                               --!or after 134 bytes of a RP_DAT, the state machine
+                                                --! reset pulse when consumption is lasting more than
-                                               --!of the WF_rx_deserializer returns to idle state
+                                                --! expected (ID_DAT > 8 bytes, RP_DAT > 134 bytes)
    --  --  --  --  --  --  --  --  --  --  --  --  --  --  -- --  --  --  --  --  --  --  --  --
    -- Signals to the WF_production & WF_consumption
@@ -224,7 +222,7 @@ architecture rtl of WF_engine_control is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin
@@ -624,7 +622,7 @@ begin
    incr_counter_i    => s_inc_prod_bytes_counter,
    -------------------------------------------------------
    counter_o         => s_prod_bytes_c,
-    counter_is_full_o => open );
+    counter_is_full_o => open);
    -------------------------------------------------------
  --  --  --  --  --  --  --  --  --  --  --
@@ -942,24 +940,26 @@ begin
 --                                 Concurrent Signal Assignments                                 --
 ---------------------------------------------------------------------------------------------------
 -- variable received by a valid ID_DAT frame that concerns this station
-  var_o                  <= s_var;
+  var_o                      <= s_var;
 -- number of bytes of the Control & Data fields of a produced RP_DAT frame
-  prod_data_lgth_o       <= s_prod_data_lgth;
+  prod_data_lgth_o           <= s_prod_data_lgth;
 -- response to WF_tx_serializer request for a byte
-  tx_byte_request_accept_p_o      <= s_tx_byte_request_accept_p_d2;
+  tx_byte_request_accept_p_o <= s_tx_byte_request_accept_p_d2;
 -- Index of the byte being consumed or produced
-  prod_cons_byte_index_o <= s_tx_byte_index when s_producing = '1' else s_rx_byte_index;
+  prod_cons_byte_index_o     <= s_tx_byte_index when s_producing = '1' else s_rx_byte_index;
 -- If the WF_rx_deserializer continues receiving bytes when the engine_control is idle, it has to
 -- be reset. This happens when the number of bytes that have arrived exceed the expected (ID_DAT >8
-- bytes and consumed RP_DAT > 130 bytes)
+-- bytes and consumed RP_DAT > 134 bytes).
-  rx_rst_p_o             <= s_idle_state and rx_byte_ready_p_i;
+--! The WF_rx_deserializer is also reset during a production session.
+  rx_rst_o                   <= (s_idle_state and rx_byte_ready_p_i) or
+                                (s_prod_wait_turnar_time or s_producing);
 -- Production starts after the expiration of the turnaround time
-  tx_start_p_o           <= s_tx_start_prod_p;
+  tx_start_p_o               <= s_tx_start_prod_p;
 ---------------------------------------------------------------------------------------------------

--- a/wf_fd_receiver.vhd
+++ b/wf_fd_receiver.vhd
@@ -117,9 +117,9 @@ entity WF_fd_receiver is
    nfip_rst_i                  : in std_logic; --! nanoFIP internal reset
    -- Signal from the WF_engine_control unit
-    rx_rst_p_i                  : in std_logic; --! receiver timeout
+    rx_rst_i                    : in std_logic; --! reset during production or
-                                                --! in cases when reception is lasting more than
+                                                --! reset pulse when consumption is lasting more than
-                                                --! received (ID_DAT > 8 bytes, RP_DAT > 130 bytes)
+                                                --! expected (ID_DAT > 8 bytes, RP_DAT > 134 bytes)
  -- OUTPUTS
@@ -147,12 +147,12 @@ end entity WF_fd_receiver;
 architecture struc of WF_fd_receiver is
  signal s_rx_osc_rst, s_adjac_bits_window, s_signif_edge_window                 : std_logic;
-  signal s_sample_bit_p, s_sample_manch_bit_p, s_rxd_filtered                    : std_logic;
+  signal s_sample_bit_p, s_sample_manch_bit_p, s_rxd_filtered, s_rx_code_viol_p  : std_logic;
  signal s_rxd_filtered_edge_p, s_rxd_filtered_f_edge_p, s_rxd_filtered_r_edge_p : std_logic;
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin
@@ -195,6 +195,7 @@ begin
   ------------------------------------------------------
    rx_manch_clk_p_o        => s_sample_manch_bit_p,
    rx_bit_clk_p_o          => s_sample_bit_p,
+    rx_manch_code_viol_p_o  => s_rx_code_viol_p, 
    rx_signif_edge_window_o => s_signif_edge_window,
    rx_adjac_bits_window_o  => s_adjac_bits_window);
   -----------------------------------------------------
@@ -211,7 +212,8 @@ begin
  port map (
    uclk_i                   => uclk_i,
    nfip_rst_i               => nfip_rst_i,
-    rx_rst_p_i               => rx_rst_p_i,
+    rx_rst_i                 => rx_rst_i,
+    manch_code_viol_p_i      => s_rx_code_viol_p,
    sample_bit_p_i           => s_sample_bit_p,
    sample_manch_bit_p_i     => s_sample_manch_bit_p,
    signif_edge_window_i     => s_signif_edge_window,

--- a/wf_fd_transmitter.vhd
+++ b/wf_fd_transmitter.vhd
@@ -149,7 +149,7 @@ architecture struc of WF_fd_transmitter is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_incr_counter.vhd
+++ b/wf_incr_counter.vhd
@@ -91,7 +91,7 @@ constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1'
 signal   s_counter      : unsigned (g_counter_lgth-1 downto 0);
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_manch_code_viol_check.vhd
+++ b/wf_manch_code_viol_check.vhd
--_________________________________________________________________________________________________
--                                                                                                |
--                                        |The nanoFIP|                                           |
--                                                                                                |
--                                        CERN,BE/CO-HT                                           |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_rx_manch_code_check.vhd                                                              |
---------------------------------------------------------------------------------------------------
--! standard library
-library IEEE;
--! standard packages
-use IEEE.STD_LOGIC_1164.all;  --! std_logic definitions
-use IEEE.NUMERIC_STD.all;     --! conversion functions
--! specific packages
-use work.WF_PACKAGE.all;      --! definitions of types, constants, entities
---------------------------------------------------------------------------------------------------
--                                                                                               --
--                                     WF_rx_manch_code_check                                    --
--                                                                                               --
---------------------------------------------------------------------------------------------------
--
--
--! @brief     The unit follows the incoming deglitched serial signal and outputs a pulse if a
--!            Manchester 2 (manch.) code violation is detected.
--!            It is assumed that a violation happens if after a half-bit-clock period (plus 2 uclk
--!            periods), the incoming signal has not had a transition.
--!
--!            Remark: We refer to
--!              o a significant edge                : for the edge of a manch. encoded bit
--!                (bit 0: __|--, bit 1: --|__)
--!
--!              o the sampling of a manch. bit      : for the moments when a manch. encoded bit
--!                should be sampled, before and after a significant edge. The period of this
--!                sampling is that of the half-bit-clock.
--!
--!              o the sampling of a bit             : for the sampling of only the 1st part,
--!                before the transition (the period is the double of the manch. sampling)
--!
--!                Example:
--!                  bits               :   0     1
--!                  manch. encoded     : __|-- --|__
--!                  significant edge   :  ^     ^
--!                  sample_manch_bit_p :  ^ ^   ^ ^
--!                  sample_bit_p       :  ^     ^   (this sampling will give the 0 and the 1)
--
--
--! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--!            Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)
--
--
--! @date      06/2010
--
--
--! @version   v0.02
--
--
--! @details \n
--
--!   \n<b>Dependencies:</b>    \n
--!            WF_reset_unit    \n
--!            WF_rx_deglitcher \n
--
--
--!   \n<b>Modified by:</b>\n
--!            Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--!   \n\n<b>Last changes:</b>\n
--!     -> 12/12/2010  v0.02  EG  cleaning-up+commenting
--
---------------------------------------------------------------------------------------------------
--
--! @todo
--!   ->
--
---------------------------------------------------------------------------------------------------
--=================================================================================================
--!                           Entity declaration for WF_rx_manch_code_check
--=================================================================================================
-entity WF_rx_manch_code_check is
-  port (
-  -- INPUTS
-    -- nanoFIP User Interface general signal
-    uclk_i                : in std_logic; --! 40 MHz clock
-    -- Signal from the WF_reset_unit
-    nfip_rst_i            : in std_logic; --! nanoFIP internal reset
-    -- Signals from the WF_rx_deglitcher unit
-    sample_bit_p_i        : in std_logic; --! pulse for the sampling of a new bit
-    sample_manch_bit_p_i  : in std_logic; --! pulse for the sampling of a new manch. bit
-    serial_input_signal_i : in std_logic; --! input signal
-  -- OUTPUTS
-    -- Signal to the WF_rx_deserializer unit
-    manch_code_viol_p_o  : out std_logic  --! pulse indicating a code violation
-      );
-end entity WF_rx_manch_code_check;
--=================================================================================================
--!                                    architecture declaration
--=================================================================================================
-architecture rtl of WF_rx_manch_code_check is
-signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_signal_d : std_logic;
--=================================================================================================
--                                        architecture begin
--=================================================================================================
-begin
---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Check_Code_Violations: in order to check for code violations, the
--! input signal is delayed for 1 half-bit-clock period.
--! The signal check_code_viol_p is a pulse occurring 2 uclk periods after a manch. edge is expected.
--! A violation exists if the signal and its delayed version are identical on the
--! check_code_viol_p moments.
--                                     0    V-    1
--   rxd_filtered          :         __|--|____|--|__
--   serial_input_signal_d :           __|--|____|--|__
--   check_code_viol       :             ^    ^    ^
-  Check_code_violations: process (uclk_i)
-  begin
-    if rising_edge (uclk_i) then
-       if nfip_rst_i = '1' then
-         s_check_code_viol_p       <= '0';
-         s_sample_bit_p_d1         <= '0';
-         s_sample_bit_p_d2         <= '0';
-         s_serial_input_signal_d   <= '0';
-       else
-         if sample_manch_bit_p_i = '1' then
-           s_serial_input_signal_d <= serial_input_signal_i;
-         end if;
-          s_check_code_viol_p      <= s_sample_bit_p_d2; -- 2 uclk ticks delay
-          s_sample_bit_p_d2        <= s_sample_bit_p_d1;
-          s_sample_bit_p_d1        <= sample_bit_p_i;
-       end if;
-    end if;
-  end process;
- --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  -- Concurrent signal assignment
-  manch_code_viol_p_o                <= s_check_code_viol_p and
-                                        (not (serial_input_signal_i xor s_serial_input_signal_d));
-end architecture rtl;
--=================================================================================================
--                                        architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
--                                      E N D   O F   F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
--- a/wf_model_constr_decoder.vhd
+++ b/wf_model_constr_decoder.vhd
@@ -118,7 +118,7 @@ architecture rtl of WF_model_constr_decoder is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_package.vhd
+++ b/wf_package.vhd
@@ -93,10 +93,10 @@ package WF_package is
  constant c_ONE  : std_logic_vector (1 downto 0) := "10";
  constant c_ZERO : std_logic_vector (1 downto 0) := "01";
-  constant c_PRE  : std_logic_vector (15 downto 0) :=  c_ONE & c_ZERO & c_ONE & c_ZERO & c_ONE & c_ZERO & c_ONE & c_ZERO;
+  constant c_PRE  : std_logic_vector (15 downto 0) := c_ONE & c_ZERO & c_ONE & c_ZERO & c_ONE & c_ZERO & c_ONE & c_ZERO;
-  constant c_FSD  : std_logic_vector (15 downto 0) :=  c_ONE & c_VP & c_VN & c_ONE & c_ZERO & c_VN & c_VP & c_ZERO;
+  constant c_FSD  : std_logic_vector (15 downto 0) := c_ONE & c_VP & c_VN & c_ONE & c_ZERO & c_VN & c_VP & c_ZERO;
-  constant c_FES  : std_logic_vector (15 downto 0) :=  c_ONE & c_VP & c_VN & c_VP & c_VN & c_ONE & c_ZERO & c_ONE;
+  constant c_FES  : std_logic_vector (15 downto 0) := c_ONE & c_VP & c_VN & c_VP & c_VN & c_ONE & c_ZERO & c_ONE;
-  constant c_FSS  : std_logic_vector (31 downto 0) :=  c_PRE & c_FSD;
+  constant c_FSS  : std_logic_vector (31 downto 0) := c_PRE & c_FSD;
@@ -359,7 +359,8 @@ package WF_package is
  port (
    uclk_i                   : in std_logic;
    nfip_rst_i               : in std_logic;
-    rx_rst_p_i               : in std_logic;
+    rx_rst_i                 : in std_logic;
+    manch_code_viol_p_i      : in std_logic; 
    signif_edge_window_i     : in std_logic;
    adjac_bits_window_i      : in std_logic;
    fd_rxd_r_edge_p_i        : in std_logic;
@@ -458,7 +459,7 @@ package WF_package is
    rate_i                      : in std_logic_vector (1 downto 0);
    fd_rxd_a_i                  : in std_logic;
    nfip_rst_i                  : in std_logic;
-    rx_rst_p_i                  : in std_logic;
+    rx_rst_i                    : in std_logic;
  -----------------------------------------------------------------
    rx_byte_o                   : out std_logic_vector (7 downto 0);
    rx_byte_ready_p_o           : out std_logic;
@@ -481,6 +482,7 @@ package WF_package is
  -----------------------------------------------------------------
    rx_manch_clk_p_o        : out std_logic;
    rx_bit_clk_p_o          : out std_logic;
+    rx_manch_code_viol_p_o  : out std_logic;
    rx_signif_edge_window_o : out std_logic;
    rx_adjac_bits_window_o  : out std_logic );
  -----------------------------------------------------------------
@@ -613,7 +615,7 @@ end component WF_rx_osc;
    tx_start_p_o                : out std_logic;
    prod_cons_byte_index_o      : out std_logic_vector (7 downto 0);
    prod_data_lgth_o            : out std_logic_vector (7 downto 0);
-    rx_rst_p_o                  : out std_logic;
+    rx_rst_o                    : out std_logic;
    var_o                       : out t_var);
  -----------------------------------------------------------------
  end component WF_engine_control;
@@ -707,21 +709,6 @@ end component WF_rx_osc;
---------------------------------------------------------------------------------------------------
-  component WF_rx_manch_code_check is
-  port (
-    uclk_i                : in std_logic;
-    nfip_rst_i            : in std_logic;
-    serial_input_signal_i : in std_logic;
-    sample_bit_p_i        : in std_logic;
-    sample_manch_bit_p_i  : in std_logic;
-  -----------------------------------------------------------------
-    manch_code_viol_p_o   : out std_logic);
-  -----------------------------------------------------------------
-  end component WF_rx_manch_code_check;
 ---------------------------------------------------------------------------------------------------
  component WF_rx_deglitcher
  port (

--- a/wf_prod_bytes_retriever.vhd
+++ b/wf_prod_bytes_retriever.vhd
@@ -202,7 +202,7 @@ architecture rtl of WF_prod_bytes_retriever is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_prod_data_lgth_calc.vhd
+++ b/wf_prod_data_lgth_calc.vhd
@@ -122,7 +122,7 @@ architecture behavior of WF_prod_data_lgth_calc is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_prod_permit.vhd
+++ b/wf_prod_permit.vhd
@@ -96,7 +96,7 @@ architecture rtl of WF_prod_permit is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_production.vhd
+++ b/wf_production.vhd
@@ -232,7 +232,7 @@ architecture struc of WF_production is
  signal s_stat, s_mps                    : std_logic_vector (7 downto 0);
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_reset_unit.vhd
+++ b/wf_reset_unit.vhd
@@ -145,6 +145,7 @@ use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
 --!     01/2011  v0.03  EG  PoR added; signals assert_RSTON_p_i & rst_nFIP_and_FD_p_i are inputs
 --!                         treated in the wf_cons_outcome; 2 state machines created; clean-up
 --!                         PoR also for internal WISHBONE resets
+--!     02/2011  v0.031  EG state nfip_off_fd_off added
 --
 ---------------------------------------------------------------------------------------------------
 --
@@ -203,7 +204,7 @@ end entity WF_reset_unit;
 --=================================================================================================
 architecture rtl of WF_reset_unit is
-  type rstin_st_t   is (idle, rstin_eval, nfip_on_fd_on, nfip_off_fd_on);
+  type rstin_st_t   is (idle, rstin_eval, nfip_on_fd_on, nfip_off_fd_on, nfip_off_fd_off);
  type var_rst_st_t is (var_rst_idle, var_rst_rston_on, var_rst_nfip_on_fd_on_rston_on,
                        var_rst_nfip_off_fd_on_rston_on, var_rst_nfip_on_fd_on,
                        var_rst_nfip_off_fd_on_rston_off);
@@ -222,7 +223,7 @@ architecture rtl of WF_reset_unit is
 --=================================================================================================
--                                        architecture begin
+--!                                      architecture begin
 --=================================================================================================
 begin
@@ -273,7 +274,7 @@ begin
 ---------------------------------------------------------------------------------------------------
--                                            RSTIN                                              --
+--                                             RSTIN                                             --
 ---------------------------------------------------------------------------------------------------
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
@@ -361,13 +362,22 @@ begin
    when nfip_off_fd_on =>
                                                          -- nanoFIP internal reset deactivated
                        if s_counter_is_full = '1' then   -- FIELDRIVE reset continues being active
-                           nx_rstin_st <= idle;           -- unitl 4 FD_TXCK cycles have passed
+                           nx_rstin_st <= nfip_off_fd_off;-- unitl 4 FD_TXCK cycles have passed
                        else
                           nx_rstin_st <= nfip_off_fd_on;
                        end if;
+    when nfip_off_fd_off =>
+                        if s_rsti_synch(2) = '1' then     -- RSTIN still active
+                          nx_rstin_st   <= nfip_off_fd_off;
+                        else
+                           nx_rstin_st <= idle;
+                        end if;
    when others =>
                        nx_rstin_st <= idle;
  end case;
@@ -416,6 +426,13 @@ begin
                 -------------------------------------
+    when nfip_off_fd_off =>
+                  s_reinit_counter <= '1';    -- no counting
+                  s_rstin_nfip_rst <= '0';
+                  s_rstin_fd_rst   <= '0';
    when others =>
                  s_reinit_counter <= '1';    -- no counting
@@ -449,7 +466,7 @@ RSTIN_free_counter: WF_incr_counter
 ---------------------------------------------------------------------------------------------------
--                                              var_rst                                          --
+--                                            var_rst                                            --
 ---------------------------------------------------------------------------------------------------
 --!@brief Resets_after_a_var_rst FSM: the state machine is divided in three parts (a clocked process
 --! to store the current state, a combinatorial process to manage state transitions and finally a
@@ -663,7 +680,7 @@ free_counter: WF_incr_counter
  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  s_var_rst_counter_is_eight <= '1' when s_var_rst_c= to_unsigned(8, s_var_rst_c'length)  else '0';
-  s_var_rst_counter_is_two   <= '1' when s_var_rst_c= to_unsigned(10, s_var_rst_c'length) else '0';
+  s_var_rst_counter_is_two   <= '1' when s_var_rst_c= to_unsigned(2, s_var_rst_c'length) else '0';
  s_var_rst_counter_is_full  <= '1' when s_var_rst_c= s_txck_four_periods                 else '0';

--- a/wf_rx_deglitcher.vhd
+++ b/wf_rx_deglitcher.vhd
@@ -108,13 +108,13 @@ architecture Behavioral of WF_rx_deglitcher is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin
 --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -
 --!@brief Synchronous process FD_RXD_synchronizer: Synchronization of the nanoFIP FIELDRIVE input
--!  FD_RXD to the uclk, using a set of 2 registers.
+--! FD_RXD to the uclk, using a set of 2 registers.
  FD_RXD_synchronizer: process (uclk_i)
  begin
@@ -140,7 +140,7 @@ begin
      if nfip_rst_i = '1' then
        s_deglitch_c       <= to_unsigned (c_DEGLITCH_THRESHOLD, s_deglitch_c'length) srl 1;-- middle value
        s_rxd_filtered     <= '0';
+        s_rxd_filtered_d1  <= '0';
      else
        --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
        if s_fd_rxd_synch(1) = '0' then         -- arrival of a '0'
@@ -163,7 +163,7 @@ begin
          end if;                               -- if counter = c_DEGLITCH_THRESHOLD
        end if;
-        s_rxd_filtered_d1  <= s_rxd_filtered;
+        s_rxd_filtered_d1  <= s_rxd_filtered;   -- used for the edges detection
      end if;
    end if;
  end process;

--- a/wf_rx_deserializer.vhd
+++ b/wf_rx_deserializer.vhd
--- a/wf_rx_osc.vhd
+++ b/wf_rx_osc.vhd
@@ -111,6 +111,8 @@ entity WF_rx_osc is
                                              --!  o between adjacent bits
                                              --!  __________|-|_________
+    rx_manch_code_viol_p_o  : out std_logic;  --! pulse upon manch. code violation detection
    rx_signif_edge_window_o : out std_logic;  --! time window where a significant edge is expected
    rx_adjac_bits_window_o  : out std_logic   --! time window where a transition between adjacent
@@ -134,18 +136,16 @@ architecture rtl of WF_rx_osc is
  signal s_bit_clk, s_bit_clk_d1, s_manch_clk, s_manch_clk_d1                          : std_logic;
- --=================================================================================================
+--=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin
-                     -- # uclock ticks for a bit period, defined by the WorldFIP bit rate
+                   --  # uclock ticks for a bit period, defined by the WorldFIP bit rate
-  s_period           <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));
+  s_period      <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));
+  s_half_period <= s_period srl 1; -- 1/2 s_period
+  s_margin      <= s_period srl 3; -- margin for jitter defined
-  s_counter_is_full  <= '1' when s_period_c = s_period -1 else '0'; -- counter full indicator
-  s_half_period      <= s_period srl 1;                             -- 1/2 s_period
-  s_margin           <= s_period srl 3;                             -- margin for jitter defined
-                                                                    -- as 1/8 s_period
 ---------------------------------------------------------------------------------------------------
@@ -171,6 +171,8 @@ begin
    counter_o         => s_period_c);
    ------------------------------------------
+    s_counter_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full indicator
    --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
    -- counter reinitialized : if nfip_rst_i is active                       or
    --                         if the rx_osc_rst_i is active                 or
@@ -204,13 +206,13 @@ begin
  begin
    if rising_edge (uclk_i) then
      if (nfip_rst_i = '1') then
-        s_manch_clk                 <='0';
+        s_manch_clk                <= '0';
-        s_bit_clk                   <='0';
+        s_bit_clk                  <= '0';
-        s_bit_clk_d1                <='0';
+        s_bit_clk_d1               <= '0';
-        s_manch_clk_d1              <='0';
+        s_manch_clk_d1             <= '0';
-        s_signif_edge_found         <='0';
+        s_signif_edge_found        <= '0';
-        s_adjac_bits_edge_found     <='0';
+        s_adjac_bits_edge_found    <= '0';
+        rx_manch_code_viol_p_o     <= '0';
      else
        --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -
@@ -219,17 +221,19 @@ begin
        -- looking for a significant edge inside the corresponding window
        if (s_signif_edge_window='1') and (fd_rxd_edge_p_i='1') and (s_signif_edge_found='0') then
-            s_manch_clk             <= not s_manch_clk; -- inversion of rx_manch_clk
+          s_manch_clk             <= not s_manch_clk; -- inversion of rx_manch_clk
-            s_signif_edge_found     <= '1';             -- indication that the edge was found
+          s_signif_edge_found     <= '1';             -- indication that the edge was found
-            s_adjac_bits_edge_found <= '0';
+          s_adjac_bits_edge_found <= '0';
+          rx_manch_code_viol_p_o  <= '0';
        -- if a significant edge is not found where expected (code violation), the rx_manch_clk
        -- is inverted right after the end of the signif_edge_window.
        elsif (s_signif_edge_found = '0') and (s_period_c = s_margin) then
-          s_manch_clk               <= not s_manch_clk;
+          s_manch_clk             <= not s_manch_clk;
-          s_adjac_bits_edge_found   <= '0';             -- re-initialization before the
+          s_adjac_bits_edge_found <= '0';             -- re-initialization before the
                                                        -- next cycle
+          rx_manch_code_viol_p_o  <= '1';
        --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -
@@ -238,30 +242,37 @@ begin
        -- looking for an edge inside the corresponding window
        elsif (s_adjac_bits_window = '1') and (fd_rxd_edge_p_i = '1') then
-           s_manch_clk              <= not s_manch_clk; -- inversion of rx_manch_clk
+          s_manch_clk             <= not s_manch_clk; -- inversion of rx_manch_clk
-           s_bit_clk                <= not s_bit_clk;   -- inversion of rx_bit_clk
+          s_bit_clk               <= not s_bit_clk;   -- inversion of rx_bit_clk
-           s_adjac_bits_edge_found  <= '1';             -- indication that an edge was found
+          s_adjac_bits_edge_found <= '1';             -- indication that an edge was found
+          s_signif_edge_found     <= '0';             -- re-initialization before next cycle
-           s_signif_edge_found      <= '0';             -- re-initialization before next cycle
+          rx_manch_code_viol_p_o  <= '0';
        -- if no edge is detected inside the adjac_bits_edge_window, both clks are inverted right
        -- after the end of it
        elsif (s_adjac_bits_edge_found = '0') and (s_period_c = s_half_period + s_margin) then
-          s_manch_clk               <= not s_manch_clk;
+          s_manch_clk             <= not s_manch_clk;
-          s_bit_clk                 <= not s_bit_clk;
+          s_bit_clk               <= not s_bit_clk;
+          s_signif_edge_found     <= '0';             -- re-initialization before next cycle
+          rx_manch_code_viol_p_o  <= '0';
+        else
+          rx_manch_code_viol_p_o  <= '0';
-          s_signif_edge_found       <= '0';             -- re-initialization before next cycle
        end if;
      --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-      s_manch_clk_d1                <= s_manch_clk;
+      s_manch_clk_d1              <= s_manch_clk;
                                                -- s_manch_clk:      ____|-----|_____|-----|____
                                                -- s_manch_clk_d1:   ______|-----|_____|-----|__
                                                -- rx_manch_clk_p_o: ____|-|___|-|___|-|___|-|__
-      s_bit_clk_d1                  <= s_bit_clk;
+      s_bit_clk_d1                <= s_bit_clk;
                                                -- s_bit_clk:        ____|-----------|___________
                                                -- s_bit_clk_d1:     ______|-----------|_________
                                                -- rx_bit_clk_p_o:   ____|-|_________|-|_________

--- a/wf_status_bytes_gen.vhd
+++ b/wf_status_bytes_gen.vhd
@@ -197,7 +197,7 @@ architecture rtl of WF_status_bytes_gen is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_tx_osc.vhd
+++ b/wf_tx_osc.vhd
@@ -118,7 +118,7 @@ architecture rtl of WF_tx_osc is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_tx_serializer.vhd
+++ b/wf_tx_serializer.vhd
@@ -157,7 +157,7 @@ architecture rtl of WF_tx_serializer is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin

--- a/wf_wb_controller.vhd
+++ b/wf_wb_controller.vhd
@@ -106,7 +106,7 @@ architecture rtl of WF_wb_controller is
 --=================================================================================================
--                                        architecture begin
+--!                                    architecture declaration
 --=================================================================================================
 begin