Commit 209907b4 authored by Tristan Gingold's avatar Tristan Gingold

Add outputs for testpoints

parent e51c789c
......@@ -131,6 +131,11 @@ entity wf_rx_deserializer is port(
-- Signal to the wf_engine_control unit
fss_received_p_o : out std_logic; -- pulse upon reception of a correct FSS (ID/RP)
-- Debug signal: when the first falling edge has been detected
dbg_frame_start_p_o : out std_logic;
-- Debug: error detected in the fsd
dbg_fsd_err_p_o : out std_logic;
-- Signal to the wf_rx_osc unit
rx_osc_rst_o : out std_logic);-- resets the clk recovery procedure
......@@ -197,6 +202,22 @@ begin
end process;
process (uclk_i)
begin
if rising_edge(uclk_i) then
if rx_st = PRE_FIELD_FIRST_F_EDGE then
dbg_frame_start_p_o <= '1';
else
dbg_frame_start_p_o <= '0';
end if;
if rx_st = FSD_FIELD then
dbg_fsd_err_p_o <= s_fsd_wrong_bit;
else
dbg_fsd_err_p_o <= '0';
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Deserializer_FSM_Comb_State_Transitions: Definition of the state
-- transitions of the FSM.
......
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