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Commit 297713da authored by egousiou's avatar egousiou
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wf_engine_control: mistake when id_dat with wrong crc arrives corrected 

aesthetics: trailing whitespaces deleted from all the units

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@173 7f0067c9-7624-46c7-bd39-3fb5400c0213
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DualClkRAM.vhd
View file @ 297713da
...@@ -32,10 +32,10 @@ use PROASIC3.all; ...@@ -32,10 +32,10 @@ use PROASIC3.all;
-- --
-- --
--! @brief Instantiation of a template ProAsic3 RAM4K9 memory component with --! @brief Instantiation of a template ProAsic3 RAM4K9 memory component with
--! o word width : 8 bits and --! o word width : 8 bits and
--! o depth : 512 bytes. --! o depth : 512 bytes.
-- --
-- --
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
-- --
...@@ -50,23 +50,23 @@ use PROASIC3.all; ...@@ -50,23 +50,23 @@ use PROASIC3.all;
-- --
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
--! ProASIC3 lib \n --! ProASIC3 lib \n
-- --
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! \n\n<b>Last changes: </b>\n --! \n\n<b>Last changes: </b>\n
--! -> 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the --! -> 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the
--! address is given (otherwise it was 2 clock cycles later) slack --! address is given (otherwise it was 2 clock cycles later) slack
--! checked and is ok! code cleaned-up and commented \n --! checked and is ok! code cleaned-up and commented \n
--! ->15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up --! ->15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo --! @todo
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
...@@ -75,12 +75,12 @@ use PROASIC3.all; ...@@ -75,12 +75,12 @@ use PROASIC3.all;
entity DualClkRAM is entity DualClkRAM is
port( port(
-- INPUTS -- INPUTS
-- Inputs concerning port A -- Inputs concerning port A
CLKA : in std_logic; --! clock A for synchronous read/ write operations CLKA : in std_logic; --! clock A for synchronous read/ write operations
ADDRA : in std_logic_vector (8 downto 0); --! address A ADDRA : in std_logic_vector (8 downto 0); --! address A
DINA : in std_logic_vector (7 downto 0); --! data in A DINA : in std_logic_vector (7 downto 0); --! data in A
RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
-- Inputs concerning port B -- Inputs concerning port B
CLKB : in std_logic; --! clock B for synchronous read/ write operations CLKB : in std_logic; --! clock B for synchronous read/ write operations
...@@ -93,10 +93,10 @@ entity DualClkRAM is ...@@ -93,10 +93,10 @@ entity DualClkRAM is
-- OUTPUTS -- OUTPUTS
-- Output concerning port A -- Output concerning port A
DOUTA : out std_logic_vector (7 downto 0); --! data out A DOUTA : out std_logic_vector (7 downto 0); --! data out A
-- Output concerning port B -- Output concerning port B
DOUTB : out std_logic_vector (7 downto 0) --! data out B DOUTB : out std_logic_vector (7 downto 0) --! data out B
); );
end DualClkRAM; end DualClkRAM;
...@@ -107,7 +107,7 @@ end DualClkRAM; ...@@ -107,7 +107,7 @@ end DualClkRAM;
--================================================================================================= --=================================================================================================
architecture RAM4K9 of DualClkRAM is architecture RAM4K9 of DualClkRAM is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- !@brief component RAM4K9 : -- !@brief component RAM4K9 :
--! General information concerning RAM4K9: a fully synchronous, true dual-port RAM with an optional --! General information concerning RAM4K9: a fully synchronous, true dual-port RAM with an optional
--! pipeline stage. It provides variable aspect ratios of 4096 x 1, 2048 x 2, 1024 x 4 and 512 x 9. --! pipeline stage. It provides variable aspect ratios of 4096 x 1, 2048 x 2, 1024 x 4 and 512 x 9.
...@@ -122,7 +122,7 @@ architecture RAM4K9 of DualClkRAM is ...@@ -122,7 +122,7 @@ architecture RAM4K9 of DualClkRAM is
--! Switching between Read and Write modes for the respective ports. --! Switching between Read and Write modes for the respective ports.
--! A Low indicates Write operation and a High indicates a Read. --! A Low indicates Write operation and a High indicates a Read.
--! BLKA, BLKB : --! BLKA, BLKB :
--! Active low enable for the respective ports. --! Active low enable for the respective ports.
--! PIPEA, PIPEB : --! PIPEA, PIPEB :
...@@ -133,7 +133,7 @@ architecture RAM4K9 of DualClkRAM is ...@@ -133,7 +133,7 @@ architecture RAM4K9 of DualClkRAM is
--! WMODEA, WMODEB : --! WMODEA, WMODEB :
--! Configuration of the behavior of the output when the RAM is in the Write mode. --! Configuration of the behavior of the output when the RAM is in the Write mode.
--! A Low on this signal makes the output retain data from the previous Read. A High indicates a --! A Low on this signal makes the output retain data from the previous Read. A High indicates a
--! pass-through behavior where the data being written will appear on the output immediately. --! pass-through behavior where the data being written will appear on the output immediately.
component RAM4K9 component RAM4K9
...@@ -160,14 +160,14 @@ architecture RAM4K9 of DualClkRAM is ...@@ -160,14 +160,14 @@ architecture RAM4K9 of DualClkRAM is
); );
end component; end component;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the component VCC --!@brief Instantiation of the component VCC
component VCC component VCC
port (Y : out std_logic); port (Y : out std_logic);
end component; end component;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the component GND --!@brief Instantiation of the component GND
component GND component GND
...@@ -187,9 +187,9 @@ begin ...@@ -187,9 +187,9 @@ begin
power_supply_signal : VCC port map (Y => POWER); power_supply_signal : VCC port map (Y => POWER);
ground_signal : GND port map (Y => GROUND); ground_signal : GND port map (Y => GROUND);
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief: Instantiation of the component RAM4K9. --!@brief: Instantiation of the component RAM4K9.
--! The following configuration has been applied: --! The following configuration has been applied:
--! o aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCC) --! o aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCC)
--! o word width : 8 bits (DINA8, DINB8: GND, DOUTA8, DOUTB8 : open) --! o word width : 8 bits (DINA8, DINB8: GND, DOUTA8, DOUTB8 : open)
--! o memory depth : 512 bytes(ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9 : GND) --! o memory depth : 512 bytes(ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9 : GND)
...@@ -199,10 +199,10 @@ begin ...@@ -199,10 +199,10 @@ begin
A9D8DualClkRAM_R0C0 : RAM4K9 A9D8DualClkRAM_R0C0 : RAM4K9
port map ( port map (
-- INPUTS -- INPUTS
-- inputs concerning port A -- inputs concerning port A
-- data in A (1 byte, (7 downto 0)) -- data in A (1 byte, (7 downto 0))
DINA8 => GROUND, DINA8 => GROUND,
DINA7 => DINA(7), DINA7 => DINA(7),
DINA6 => DINA(6), DINA6 => DINA(6),
...@@ -236,7 +236,7 @@ begin ...@@ -236,7 +236,7 @@ begin
PIPEA => GROUND, PIPEA => GROUND,
WMODEA => GROUND, WMODEA => GROUND,
-- inputs concerning port B -- inputs concerning port B
-- data in B (1 byte, (7 downto 0)) -- data in B (1 byte, (7 downto 0))
DINB8 => GROUND, DINB8 => GROUND,
DINB7 => DINB(7), DINB7 => DINB(7),
...@@ -275,7 +275,7 @@ begin ...@@ -275,7 +275,7 @@ begin
------------------------------- -------------------------------
-- OUTPUTS -- OUTPUTS
-- output concerning port A -- output concerning port A
-- data out A (1 byte) -- data out A (1 byte)
DOUTA8 => open, DOUTA8 => open,
DOUTA7 => DOUTA(7), DOUTA7 => DOUTA(7),
DOUTA6 => DOUTA(6), DOUTA6 => DOUTA(6),
...@@ -287,7 +287,7 @@ begin ...@@ -287,7 +287,7 @@ begin
DOUTA0 => DOUTA(0), DOUTA0 => DOUTA(0),
-- output concerning port B -- output concerning port B
-- data out B (1 byte) -- data out B (1 byte)
DOUTB8 => open, DOUTB8 => open,
DOUTB7 => DOUTB(7), DOUTB7 => DOUTB(7),
DOUTB6 => DOUTB(6), DOUTB6 => DOUTB(6),
......
nanofip.vhd
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wf_DualClkRAM_clka_rd_clkb_wr.vhd
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...@@ -6,9 +6,9 @@ ...@@ -6,9 +6,9 @@
--________________________________________________________________________________________________| --________________________________________________________________________________________________|
--________________________________________________________________________________________________| --________________________________________________________________________________________________|
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! @file WF_DualClkRAM_clka_rd_clkb_wr.vhd | --! @file WF_DualClkRAM_clka_rd_clkb_wr.vhd |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! Standard library --! Standard library
library IEEE; library IEEE;
...@@ -28,14 +28,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -28,14 +28,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
-- --
--! @brief The unit provides the memory triplication, transparently to the outside world. --! @brief The unit provides the memory triplication, transparently to the outside world.
--! The component DualClkRam (512 bytes) is triplicated: each incoming byte is written --! The component DualClkRam (512 bytes) is triplicated: each incoming byte is written
--! at the same position in the three memories, whereas each outgoing byte is the --! at the same position in the three memories, whereas each outgoing byte is the
--! outcome of a majority voter. --! outcome of a majority voter.
--! The memory is dual port; port A is used for reading only, port B for writing only. --! The memory is dual port; port A is used for reading only, port B for writing only.
--! --!
--! Remark: MajorityVoter(A,B,C) = (A and B) OR (A and C) OR (B and C) --! Remark: MajorityVoter(A,B,C) = (A and B) OR (A and C) OR (B and C)
-- --
-- --
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
-- --
...@@ -48,23 +48,23 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -48,23 +48,23 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
--! @details\n --! @details\n
-- --
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
--! DualClkRAM.vhd \n --! DualClkRAM.vhd \n
-- --
-- --
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! \n\n<b>Last changes: </b>\n --! \n\n<b>Last changes: </b>\n
--! -> 12/2010 v0.02 EG code cleaned-up+commented \n --! -> 12/2010 v0.02 EG code cleaned-up+commented \n
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo --! @todo
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -76,29 +76,29 @@ entity WF_DualClkRAM_clka_rd_clkb_wr is ...@@ -76,29 +76,29 @@ entity WF_DualClkRAM_clka_rd_clkb_wr is
generic (g_ram_data_lgth : integer; -- length of data word generic (g_ram_data_lgth : integer; -- length of data word
g_ram_addr_lgth : integer); -- memory depth g_ram_addr_lgth : integer); -- memory depth
port ( port (
-- INPUTS -- INPUTS
-- Inputs concerning port A -- Inputs concerning port A
clk_porta_i : in std_logic; clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0); addr_porta_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
-- Inputs concerning port B -- Inputs concerning port B
clk_portb_i : in std_logic; clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0); addr_portb_i : in std_logic_vector (g_ram_addr_lgth - 1 downto 0);
data_portb_i : in std_logic_vector (g_ram_data_lgth - 1 downto 0); data_portb_i : in std_logic_vector (g_ram_data_lgth - 1 downto 0);
write_en_portb_i : in std_logic; write_en_portb_i : in std_logic;
-- OUTPUT -- OUTPUT
-- Output concerning port A -- Output concerning port A
data_porta_o : out std_logic_vector (g_ram_data_lgth -1 downto 0) data_porta_o : out std_logic_vector (g_ram_data_lgth -1 downto 0)
); );
end WF_DualClkRAM_clka_rd_clkb_wr; end WF_DualClkRAM_clka_rd_clkb_wr;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0); type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
signal s_data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories signal s_data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
...@@ -109,32 +109,32 @@ architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is ...@@ -109,32 +109,32 @@ architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
--================================================================================================= --=================================================================================================
begin begin
s_one <= '1'; s_one <= '1';
s_zeros <= (others => '0'); s_zeros <= (others => '0');
s_rwB <= not write_en_portb_i; s_rwB <= not write_en_portb_i;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief: memory triplication --!@brief: memory triplication
--! The component DualClkRam is generated three times. --! The component DualClkRam is generated three times.
--! Port A is used for reading only, port B for writing only. --! Port A is used for reading only, port B for writing only.
--! The input DINB is written in the same position in the 3 memories. --! The input DINB is written in the same position in the 3 memories.
--! The output DOUTA from each memory is kept in the array s_data_o_A_array. --! The output DOUTA from each memory is kept in the array s_data_o_A_array.
G_memory_triplication: for I in 0 to 2 generate G_memory_triplication: for I in 0 to 2 generate
UDualClkRam : DualClkRam UDualClkRam : DualClkRam
port map ( port map (
DINA => s_zeros, DINA => s_zeros,
ADDRA => addr_porta_i, ADDRA => addr_porta_i,
RWA => s_one, RWA => s_one,
CLKA => clk_porta_i, CLKA => clk_porta_i,
DINB => data_portb_i, DINB => data_portb_i,
ADDRB => addr_portb_i, ADDRB => addr_portb_i,
RWB => s_rwB, RWB => s_rwB,
CLKB => clk_portb_i, CLKB => clk_portb_i,
RESETn => s_one, RESETn => s_one,
...@@ -144,7 +144,7 @@ begin ...@@ -144,7 +144,7 @@ begin
end generate; end generate;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Combinatorial Majority_Voter --!@brief Combinatorial Majority_Voter
Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
......
wf_bits_to_txd.vhd
View file @ 297713da
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
--! standard packages --! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
...@@ -43,7 +43,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -43,7 +43,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.03 --! @version v0.03
-- --
-- --
--! @details \n --! @details \n
-- --
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n --! WF_reset_unit \n
...@@ -54,21 +54,21 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -54,21 +54,21 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! -> 8/2010 v0.02 EG tx_enable has to be synched with txd! sending_fss not enough; --! -> 8/2010 v0.02 EG tx_enable has to be synched with txd! sending_fss not enough;
--! need for tx_clk_p_buff signal --! need for tx_clk_p_buff signal
--! -> 7/1/2011 v0.03 EG tx_enable now starts 1 uclk tick earlier, at the same moment as txd --! -> 7/1/2011 v0.03 EG tx_enable now starts 1 uclk tick earlier, at the same moment as txd
--! becomes 1 for the 1st bit of preamble --! becomes 1 for the 1st bit of preamble
--! signals s_tx_enable & s_start_tx_enable removed for simplification --! signals s_tx_enable & s_start_tx_enable removed for simplification
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo --! @todo
--! -> --! ->
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -78,7 +78,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -78,7 +78,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_bits_to_txd is entity WF_bits_to_txd is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface, General signals -- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
...@@ -94,12 +94,12 @@ entity WF_bits_to_txd is ...@@ -94,12 +94,12 @@ entity WF_bits_to_txd is
sending_fes_i : in std_logic; --! -------"----"-----"-------- sending_fes_i : in std_logic; --! -------"----"-----"--------
stop_transmission_i : in std_logic; --! -------"----"-----"-------- stop_transmission_i : in std_logic; --! -------"----"-----"--------
txd_bit_index_i : in unsigned(4 downto 0); --! index of a bit inside a byte txd_bit_index_i : in unsigned(4 downto 0); --! index of a bit inside a byte
-- Signals from the WF_tx_osc unit -- Signals from the WF_tx_osc unit
tx_clk_p_i : in std_logic; --!clk for transmission synchronization tx_clk_p_i : in std_logic; --!clk for transmission synchronization
-- OUTPUTS -- OUTPUTS
-- nanoFIP FIELDRIVE outputs -- nanoFIP FIELDRIVE outputs
txd_o : out std_logic; --! FD_TXD txd_o : out std_logic; --! FD_TXD
...@@ -116,7 +116,7 @@ architecture rtl of WF_bits_to_txd is ...@@ -116,7 +116,7 @@ architecture rtl of WF_bits_to_txd is
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
--================================================================================================= --=================================================================================================
begin begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -133,7 +133,7 @@ begin ...@@ -133,7 +133,7 @@ begin
else else
if tx_clk_p_i = '1' then if tx_clk_p_i = '1' then
if sending_fss_i = '1' then if sending_fss_i = '1' then
txd_o <= c_FSS (to_integer (txd_bit_index_i)); -- FSS: 2 bytes long (no need to resize) txd_o <= c_FSS (to_integer (txd_bit_index_i)); -- FSS: 2 bytes long (no need to resize)
...@@ -148,7 +148,7 @@ begin ...@@ -148,7 +148,7 @@ begin
txd_o <= c_FES(to_integer (resize(txd_bit_index_i,4))); -- FES: 1 byte txd_o <= c_FES(to_integer (resize(txd_bit_index_i,4))); -- FES: 1 byte
else else
txd_o <= '0'; txd_o <= '0';
end if; end if;
end if; end if;
...@@ -162,7 +162,7 @@ begin ...@@ -162,7 +162,7 @@ begin
--!@brief Synchronous process FD_TXENA_Generator: The nanoFIP output FD_TXENA is activated at the --!@brief Synchronous process FD_TXENA_Generator: The nanoFIP output FD_TXENA is activated at the
--! same moment as the first bit of the PRE starts being delivered and stays asserted until the --! same moment as the first bit of the PRE starts being delivered and stays asserted until the
--! end of the delivery of the last FES bit. --! end of the delivery of the last FES bit.
FD_TXENA_Generator: process (uclk_i) FD_TXENA_Generator: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
...@@ -174,7 +174,7 @@ begin ...@@ -174,7 +174,7 @@ begin
if ((sending_fss_i = '1') or (sending_data_i = '1') or -- tx sending bits if ((sending_fss_i = '1') or (sending_data_i = '1') or -- tx sending bits
(sending_crc_i = '1') or (sending_fes_i = '1') or (stop_transmission_i = '1')) then (sending_crc_i = '1') or (sending_fes_i = '1') or (stop_transmission_i = '1')) then
if tx_clk_p_i = '1' then -- in order to synchronise the if tx_clk_p_i = '1' then -- in order to synchronise the
tx_enable_o <= '1'; -- activation of tx_enable with the tx_enable_o <= '1'; -- activation of tx_enable with the
end if; -- the delivery of the 1st FSS bit end if; -- the delivery of the 1st FSS bit
-- FD_TXD (FSS) :________|-----|___________|-------- -- FD_TXD (FSS) :________|-----|___________|--------
...@@ -183,7 +183,7 @@ begin ...@@ -183,7 +183,7 @@ begin
-- FD_TXENA :________|-------------------------- -- FD_TXENA :________|--------------------------
else else
tx_enable_o <= '0'; tx_enable_o <= '0';
end if; end if;
end if; end if;
end if; end if;
......
wf_cons_bytes_processor.vhd
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wf_cons_outcome.vhd
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wf_consumption.vhd
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wf_crc.vhd
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...@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.04 --! @version v0.04
-- --
-- --
--! @details \n --! @details \n
-- --
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
--! WF_reset_unit \n --! WF_reset_unit \n
...@@ -77,11 +77,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -77,11 +77,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--================================================================================================= --=================================================================================================
entity WF_crc is entity WF_crc is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface, General signals -- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_rx_deserializer/ WF_tx_serializer units -- Signals from the WF_rx_deserializer/ WF_tx_serializer units
...@@ -89,14 +89,14 @@ entity WF_crc is ...@@ -89,14 +89,14 @@ entity WF_crc is
data_bit_ready_p_i : in std_logic; --! indicates the sampling moment of data_bit_i data_bit_ready_p_i : in std_logic; --! indicates the sampling moment of data_bit_i
start_crc_p_i : in std_logic; --! beginning of the CRC calculation start_crc_p_i : in std_logic; --! beginning of the CRC calculation
-- OUTPUTS -- OUTPUTS
-- Signal to the WF_rx_deserializer unit -- Signal to the WF_rx_deserializer unit
crc_ok_p_o : out std_logic; --! signals a correct received CRC syndrome crc_ok_p_o : out std_logic; --! signals a correct received CRC syndrome
-- Signal to the WF_tx_serializer unit -- Signal to the WF_tx_serializer unit
crc_o : out std_logic_vector (c_CRC_GENER_POLY_LGTH-1 downto 0)--!calculated CRC crc_o : out std_logic_vector (c_CRC_POLY_LGTH-1 downto 0)--!calculated CRC
); );
end entity WF_crc; end entity WF_crc;
...@@ -106,7 +106,7 @@ end entity WF_crc; ...@@ -106,7 +106,7 @@ end entity WF_crc;
--================================================================================================= --=================================================================================================
architecture rtl of WF_crc is architecture rtl of WF_crc is
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_CRC_GENER_POLY_LGTH - 1 downto 0); signal s_q, s_q_nx : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0);
--================================================================================================= --=================================================================================================
...@@ -115,7 +115,7 @@ architecture rtl of WF_crc is ...@@ -115,7 +115,7 @@ architecture rtl of WF_crc is
begin begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1 --!@brief The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1
--! of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which --! of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which
--! are interconnected as a linear feedback shift register. --! are interconnected as a linear feedback shift register.
...@@ -124,7 +124,7 @@ begin ...@@ -124,7 +124,7 @@ begin
s_q_nx(0) <= data_bit_i xor s_q(s_q'left); s_q_nx(0) <= data_bit_i xor s_q(s_q'left);
G: for I in 1 to c_CRC_GENER_POLY'left generate G: for I in 1 to c_CRC_GENER_POLY'left generate
s_q_nx(I) <= s_q(I-1) xor (c_CRC_GENER_POLY(I) and (data_bit_i xor s_q(s_q'left))); s_q_nx(I) <= s_q(I-1) xor (c_CRC_GENER_POLY(I) and (data_bit_i xor s_q(s_q'left)));
end generate; end generate;
...@@ -139,7 +139,7 @@ begin ...@@ -139,7 +139,7 @@ begin
if nfip_rst_i = '1' then if nfip_rst_i = '1' then
s_q <= (others => '0'); s_q <= (others => '0');
else else
if start_crc_p_i = '1' then if start_crc_p_i = '1' then
...@@ -154,21 +154,21 @@ begin ...@@ -154,21 +154,21 @@ begin
end if; end if;
end process; end process;
-- -- -- -- -- -- -- -- -- --
crc_o <= not s_q; crc_o <= not s_q;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Syndrome_Verification: On the reception, the CRC is being --!@brief Combinatorial process Syndrome_Verification: On the reception, the CRC is being
--! calculated as data is arriving (same as in the transmission) and it is being compared to the --! calculated as data is arriving (same as in the transmission) and it is being compared to the
--! predefined c_CRC_VERIFIC_MASK. When the CRC calculated from the received data matches the --! predefined c_CRC_VERIF_POLY. When the CRC calculated from the received data matches the
--! c_CRC_VERIFIC_MASK, it is implied that a correct CRC word has been received for the preceded --! c_CRC_VERIF_POLY, it is implied that a correct CRC word has been received for the preceded
--! data and the signal crc_ok_p_o gives a 1 uclk-wide pulse. --! data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.
Syndrome_Verification: process (s_q, data_bit_ready_p_i) Syndrome_Verification: process (s_q, data_bit_ready_p_i)
begin begin
if s_q = not c_CRC_VERIFIC_MASK then if s_q = not c_CRC_VERIF_POLY then
crc_ok_p_o <= data_bit_ready_p_i; crc_ok_p_o <= data_bit_ready_p_i;
......
wf_decr_counter.vhd
View file @ 297713da
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
--! standard packages --! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
...@@ -37,23 +37,23 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -37,23 +37,23 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @version v0.01 --! @version v0.01
-- --
-- --
--! @details \n --! @details \n
-- --
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
-- --
-- --
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo --! @todo
--! -> --! ->
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -64,7 +64,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -64,7 +64,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
entity WF_decr_counter is entity WF_decr_counter is
generic (g_counter_lgth : natural := 4); --! default length generic (g_counter_lgth : natural := 4); --! default length
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface general signal -- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
...@@ -75,11 +75,11 @@ entity WF_decr_counter is ...@@ -75,11 +75,11 @@ entity WF_decr_counter is
counter_decr_p_i : in std_logic; --! decrement enable counter_decr_p_i : in std_logic; --! decrement enable
counter_load_i : in std_logic; --! load enable counter_load_i : in std_logic; --! load enable
counter_top : in unsigned (g_counter_lgth-1 downto 0); --! load value counter_top : in unsigned (g_counter_lgth-1 downto 0); --! load value
-- OUTPUTS -- OUTPUTS
-- Signal to any unit -- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); --! counter counter_o : out unsigned (g_counter_lgth-1 downto 0); --! counter
counter_is_zero_o : out std_logic --! empty counter indication counter_is_zero_o : out std_logic --! empty counter indication
); );
end entity WF_decr_counter; end entity WF_decr_counter;
...@@ -95,7 +95,7 @@ architecture rtl of WF_decr_counter is ...@@ -95,7 +95,7 @@ architecture rtl of WF_decr_counter is
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
--================================================================================================= --=================================================================================================
begin begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -121,12 +121,12 @@ begin ...@@ -121,12 +121,12 @@ begin
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments for the output signals -- Concurrent assignments for the output signals
counter_o <= s_counter; counter_o <= s_counter;
counter_is_zero_o <= '1' when s_counter = to_unsigned(0,s_counter'length) else '0'; counter_is_zero_o <= '1' when s_counter = to_unsigned(0,s_counter'length) else '0';
end architecture rtl; end architecture rtl;
--================================================================================================= --=================================================================================================
......
wf_engine_control.vhd
View file @ 297713da
This diff is collapsed.
wf_fd_receiver.vhd
View file @ 297713da
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
--! standard packages --! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
...@@ -37,7 +37,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -37,7 +37,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o WF_rx_osc : for the clock recovery --! o WF_rx_osc : for the clock recovery
--! --!
--! o WF_rx_deglitcher : for the filtering of the input FD_RXD --! o WF_rx_deglitcher : for the filtering of the input FD_RXD
--! --!
--! --!
--! _________________________ _________________________ --! _________________________ _________________________
--! | | | | --! | | | |
...@@ -61,7 +61,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -61,7 +61,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! |___________________________________________________________| --! |___________________________________________________________|
--! \/ --! \/
--! ___________________________________________________________________ --! ___________________________________________________________________
--! 0_____________________________FIELDBUS______________________________O --! 0_____________________________FIELDBUS______________________________O
-- --
-- --
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
...@@ -74,7 +74,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -74,7 +74,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.01 --! @version v0.01
-- --
-- --
--! @details \n --! @details \n
-- --
--! \n<b>Dependencies:</b> \n --! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n --! WF_reset_unit \n
...@@ -83,17 +83,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -83,17 +83,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! -> --! ->
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo --! @todo
--! -> --! ->
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -103,11 +103,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -103,11 +103,11 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_fd_receiver is entity WF_fd_receiver is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface, General signals -- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHZ clock uclk_i : in std_logic; --! 40 MHZ clock
-- nanoFIP WorldFIP Settings -- nanoFIP WorldFIP Settings
rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate rate_i : in std_logic_vector (1 downto 0); --! WorldFIP bit rate
-- nanoFIP FIELDRIVE -- nanoFIP FIELDRIVE
...@@ -122,17 +122,17 @@ entity WF_fd_receiver is ...@@ -122,17 +122,17 @@ entity WF_fd_receiver is
--! received (ID_DAT > 8 bytes, RP_DAT > 130 bytes) --! received (ID_DAT > 8 bytes, RP_DAT > 130 bytes)
-- OUTPUTS -- OUTPUTS
-- Signals to the WF_engine_control and WF_consumption -- Signals to the WF_engine_control and WF_consumption
rx_byte_o : out std_logic_vector (7 downto 0); --! retrieved data byte rx_byte_o : out std_logic_vector (7 downto 0); --! retrieved data byte
rx_byte_ready_p_o : out std_logic;--! pulse indicating a new retrieved data byte rx_byte_ready_p_o : out std_logic;--! pulse indicating a new retrieved data byte
rx_fss_crc_fes_manch_ok_p_o : out std_logic;--! indication of a frame (ID_DAT or RP_DAT) with rx_fss_crc_fes_manch_ok_p_o : out std_logic;--! indication of a frame (ID_DAT or RP_DAT) with
--! correct FSS, FES, CRC and manch. encoding --! correct FSS, FES, CRC and manch. encoding
-- Signals to the WF_engine_control -- Signals to the WF_engine_control
rx_fss_received_p_o : out std_logic;--! pulse after the reception of a correct FSS(ID/RP) rx_fss_received_p_o : out std_logic;--! pulse after the reception of a correct FSS(ID/RP)
-- Signal to the WF_engine_control and the WF_production units -- Signal to the WF_engine_control and the WF_production units
rx_crc_or_manch_wrong_p_o : out std_logic --! indication of a wrong CRC or manch. encoding on rx_crc_or_manch_wrong_p_o : out std_logic --! indication of a wrong CRC or manch. encoding on
--!a ID_DAT or RP_DAT;pulse after the FES detection --!a ID_DAT or RP_DAT;pulse after the FES detection
); );
...@@ -153,7 +153,7 @@ architecture struc of WF_fd_receiver is ...@@ -153,7 +153,7 @@ architecture struc of WF_fd_receiver is
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
--================================================================================================= --=================================================================================================
begin begin
...@@ -164,7 +164,7 @@ begin ...@@ -164,7 +164,7 @@ begin
--! @brief Instantiation of the WF_rx_deglitcher unit. --! @brief Instantiation of the WF_rx_deglitcher unit.
FIELDRIVE_Receiver_Deglitcher: WF_rx_deglitcher FIELDRIVE_Receiver_Deglitcher: WF_rx_deglitcher
port map ( port map (
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i, nfip_rst_i => nfip_rst_i,
...@@ -181,7 +181,7 @@ begin ...@@ -181,7 +181,7 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Oscillator -- -- Oscillator --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_rx_osc unit. --! @brief Instantiation of the WF_rx_osc unit.
...@@ -203,11 +203,11 @@ begin ...@@ -203,11 +203,11 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Deserializer -- -- Deserializer --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! @brief Instantiation of the WF_rx_deserializer unit. --! @brief Instantiation of the WF_rx_deserializer unit.
FIELDRIVE_Receiver_Deserializer: WF_rx_deserializer FIELDRIVE_Receiver_Deserializer: WF_rx_deserializer
port map ( port map (
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i, nfip_rst_i => nfip_rst_i,
...@@ -229,7 +229,7 @@ begin ...@@ -229,7 +229,7 @@ begin
------------------------------------------------------ ------------------------------------------------------
end architecture struc; end architecture struc;
--================================================================================================= --=================================================================================================
...@@ -237,4 +237,4 @@ end architecture struc; ...@@ -237,4 +237,4 @@ end architecture struc;
--================================================================================================= --=================================================================================================
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- E N D O F F I L E -- E N D O F F I L E
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_fd_transmitter.vhd
View file @ 297713da
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
--! standard packages --! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
...@@ -33,14 +33,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -33,14 +33,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! o WF_tx_serializer : that receives bytes from the WF_Production, encodes them --! o WF_tx_serializer : that receives bytes from the WF_Production, encodes them
--! (Manchester 2), adds the FSS, FCS & FES fields and puts one --! (Manchester 2), adds the FSS, FCS & FES fields and puts one
--! by one bits to the FIELDRIVE output FD_TXD, following the --! by one bits to the FIELDRIVE output FD_TXD, following the
--! synchronization signals from the WF_tx_osc unit. --! synchronization signals from the WF_tx_osc unit.
--! Also generates the nanoFIP output FD_TXENA. --! Also generates the nanoFIP output FD_TXENA.
--! --!
--! o WF_tx_osc : that generates the nanoFIP FIELDRIVE output FD_TXCK --! o WF_tx_osc : that generates the nanoFIP FIELDRIVE output FD_TXCK
--! and the array of pulses tx_clk_p_buff (used for the --! and the array of pulses tx_clk_p_buff (used for the
--! synchronization of the WF_tx_serializer). --! synchronization of the WF_tx_serializer).
--! ___________________________________________________________ --! ___________________________________________________________
--! | | --! | |
--! | WF_Production | --! | WF_Production |
--! |___________________________________________________________| --! |___________________________________________________________|
--! \/ --! \/
...@@ -60,7 +60,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -60,7 +60,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! |___________________________________________________________| --! |___________________________________________________________|
--! \/ --! \/
--! ___________________________________________________________________ --! ___________________________________________________________________
--! 0_____________________________FIELDBUS______________________________O --! 0_____________________________FIELDBUS______________________________O
--! --!
--! --!
--! --!
...@@ -76,7 +76,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -76,7 +76,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.01 --! @version v0.01
-- --
-- --
--! @details \n --! @details \n
-- --
--! \n<b>Dependencies:</b> \n --! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n --! WF_reset_unit \n
...@@ -89,14 +89,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -89,14 +89,14 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! -> --! ->
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo --! @todo
--! -> --! ->
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -107,7 +107,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -107,7 +107,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_fd_transmitter is entity WF_fd_transmitter is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface, General signal -- nanoFIP User Interface, General signal
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
...@@ -118,10 +118,10 @@ entity WF_fd_transmitter is ...@@ -118,10 +118,10 @@ entity WF_fd_transmitter is
nfip_rst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signals from the WF_production unit -- Signals from the WF_production unit
tx_byte_i : in std_logic_vector (7 downto 0); --! byte to be delivered tx_byte_i : in std_logic_vector (7 downto 0); --! byte to be delivered
-- Signals from the WF_engine_control -- Signals from the WF_engine_control
tx_byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered tx_byte_request_accept_p_i : in std_logic; --! indication that a byte is ready to be delivered
tx_last_byte_p_i : in std_logic; --! indication of the last byte before the CRC bytes tx_last_byte_p_i : in std_logic; --! indication of the last byte before the CRC bytes
tx_start_p_i : in std_logic; --! indication for the start of the production tx_start_p_i : in std_logic; --! indication for the start of the production
...@@ -146,11 +146,11 @@ architecture struc of WF_fd_transmitter is ...@@ -146,11 +146,11 @@ architecture struc of WF_fd_transmitter is
signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0); signal s_tx_clk_p_buff : std_logic_vector (c_TX_CLK_BUFF_LGTH-1 downto 0);
signal s_tx_osc_rst_p : std_logic; signal s_tx_osc_rst_p : std_logic;
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
--================================================================================================= --=================================================================================================
begin begin
...@@ -160,9 +160,9 @@ begin ...@@ -160,9 +160,9 @@ begin
--!@brief Instantiation of the WF_tx_osc unit --!@brief Instantiation of the WF_tx_osc unit
tx_oscillator: WF_tx_osc tx_oscillator: WF_tx_osc
port map ( port map (
uclk_i => uclk_i, uclk_i => uclk_i,
rate_i => rate_i, rate_i => rate_i,
nfip_rst_i => nfip_rst_i, nfip_rst_i => nfip_rst_i,
tx_osc_rst_p_i => s_tx_osc_rst_p, tx_osc_rst_p_i => s_tx_osc_rst_p,
...@@ -175,11 +175,11 @@ begin ...@@ -175,11 +175,11 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Serializer -- -- Serializer --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Instantiation of the WF_tx_serializer unit --!@brief Instantiation of the WF_tx_serializer unit
tx_serializer: WF_tx_serializer tx_serializer: WF_tx_serializer
port map ( port map (
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i, nfip_rst_i => nfip_rst_i,
......
wf_incr_counter.vhd
View file @ 297713da
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
--! standard packages --! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
...@@ -37,24 +37,24 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -37,24 +37,24 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @version v0.01 --! @version v0.01
-- --
-- --
--! @details \n --! @details \n
-- --
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
-- --
-- --
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! -> 01/2011 EG v0.011 counter_full became a constant --! -> 01/2011 EG v0.011 counter_full became a constant
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo --! @todo
--! -> --! ->
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
...@@ -62,22 +62,22 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -62,22 +62,22 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--================================================================================================= --=================================================================================================
entity WF_incr_counter is entity WF_incr_counter is
generic (g_counter_lgth : natural := 4); --! default length generic (g_counter_lgth : natural := 4); --! default length
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface general signal -- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signals from any unit -- Signals from any unit
incr_counter_i : in std_logic; --! increment enable incr_counter_i : in std_logic; --! increment enable
reinit_counter_i : in std_logic; --! reinitializes counter to 0 reinit_counter_i : in std_logic; --! reinitializes counter to 0
-- OUTPUT -- OUTPUT
-- Signal to any unit -- Signal to any unit
counter_o : out unsigned(g_counter_lgth-1 downto 0); --! counter counter_o : out unsigned (g_counter_lgth-1 downto 0); --! counter
counter_is_full_o : out std_logic --! counter full indication counter_is_full_o : out std_logic --! counter full indication
); --! (all bits to '1') ); --! (all bits to '1')
end entity WF_incr_counter; end entity WF_incr_counter;
...@@ -90,14 +90,13 @@ architecture rtl of WF_incr_counter is ...@@ -90,14 +90,13 @@ architecture rtl of WF_incr_counter is
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1'); constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0); signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
--================================================================================================= --=================================================================================================
begin begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Synchronous process Incr_Counter -- Synchronous process Incr_Counter
Incr_Counter: process (uclk_i) Incr_Counter: process (uclk_i)
...@@ -114,7 +113,7 @@ begin ...@@ -114,7 +113,7 @@ begin
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent assignments for output signals -- Concurrent assignments for output signals
counter_o <= s_counter; counter_o <= s_counter;
......
wf_manch_code_viol_check.vhd
View file @ 297713da
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
--! standard packages --! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
...@@ -41,13 +41,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -41,13 +41,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! sampling is that of the half-bit-clock. --! sampling is that of the half-bit-clock.
--! --!
--! o the sampling of a bit : for the sampling of only the 1st part, --! o the sampling of a bit : for the sampling of only the 1st part,
--! before the transition (the period is the double of the manch. sampling) --! before the transition (the period is the double of the manch. sampling)
--! --!
--! Example: --! Example:
--! bits : 0 1 --! bits : 0 1
--! manch. encoded : __|-- --|__ --! manch. encoded : __|-- --|__
--! significant edge : ^ ^ --! significant edge : ^ ^
--! sample_manch_bit_p : ^ ^ ^ ^ --! sample_manch_bit_p : ^ ^ ^ ^
--! sample_bit_p : ^ ^ (this sampling will give the 0 and the 1) --! sample_bit_p : ^ ^ (this sampling will give the 0 and the 1)
-- --
-- --
...@@ -61,7 +61,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -61,7 +61,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.02 --! @version v0.02
-- --
-- --
--! @details \n --! @details \n
-- --
--! \n<b>Dependencies:</b> \n --! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n --! WF_reset_unit \n
...@@ -71,17 +71,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -71,17 +71,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! -> 12/12/2010 v0.02 EG cleaning-up+commenting --! -> 12/12/2010 v0.02 EG cleaning-up+commenting
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo --! @todo
--! -> --! ->
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
...@@ -90,8 +90,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -90,8 +90,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_rx_manch_code_check is entity WF_rx_manch_code_check is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface general signal -- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
...@@ -100,9 +100,9 @@ entity WF_rx_manch_code_check is ...@@ -100,9 +100,9 @@ entity WF_rx_manch_code_check is
-- Signals from the WF_rx_deglitcher unit -- Signals from the WF_rx_deglitcher unit
sample_bit_p_i : in std_logic; --! pulse for the sampling of a new bit sample_bit_p_i : in std_logic; --! pulse for the sampling of a new bit
sample_manch_bit_p_i : in std_logic; --! pulse for the sampling of a new manch. bit sample_manch_bit_p_i : in std_logic; --! pulse for the sampling of a new manch. bit
serial_input_signal_i : in std_logic; --! input signal serial_input_signal_i : in std_logic; --! input signal
-- OUTPUTS -- OUTPUTS
-- Signal to the WF_rx_deserializer unit -- Signal to the WF_rx_deserializer unit
manch_code_viol_p_o : out std_logic --! pulse indicating a code violation manch_code_viol_p_o : out std_logic --! pulse indicating a code violation
...@@ -120,7 +120,7 @@ signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_si ...@@ -120,7 +120,7 @@ signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_si
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
--================================================================================================= --=================================================================================================
begin begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -130,13 +130,13 @@ begin ...@@ -130,13 +130,13 @@ begin
--! A violation exists if the signal and its delayed version are identical on the --! A violation exists if the signal and its delayed version are identical on the
--! check_code_viol_p moments. --! check_code_viol_p moments.
-- 0 V- 1 -- 0 V- 1
-- rxd_filtered : __|--|____|--|__ -- rxd_filtered : __|--|____|--|__
-- serial_input_signal_d : __|--|____|--|__ -- serial_input_signal_d : __|--|____|--|__
-- check_code_viol : ^ ^ ^ -- check_code_viol : ^ ^ ^
Check_code_violations: process (uclk_i) Check_code_violations: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_rst_i = '1' then if nfip_rst_i = '1' then
s_check_code_viol_p <= '0'; s_check_code_viol_p <= '0';
s_sample_bit_p_d1 <= '0'; s_sample_bit_p_d1 <= '0';
...@@ -146,7 +146,7 @@ begin ...@@ -146,7 +146,7 @@ begin
else else
if sample_manch_bit_p_i = '1' then if sample_manch_bit_p_i = '1' then
s_serial_input_signal_d <= serial_input_signal_i; s_serial_input_signal_d <= serial_input_signal_i;
end if; end if;
s_check_code_viol_p <= s_sample_bit_p_d2; -- 2 uclk ticks delay s_check_code_viol_p <= s_sample_bit_p_d2; -- 2 uclk ticks delay
...@@ -154,15 +154,15 @@ begin ...@@ -154,15 +154,15 @@ begin
s_sample_bit_p_d1 <= sample_bit_p_i; s_sample_bit_p_d1 <= sample_bit_p_i;
end if; end if;
end if; end if;
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment -- Concurrent signal assignment
manch_code_viol_p_o <= s_check_code_viol_p and manch_code_viol_p_o <= s_check_code_viol_p and
(not (serial_input_signal_i xor s_serial_input_signal_d)); (not (serial_input_signal_i xor s_serial_input_signal_d));
end architecture rtl; end architecture rtl;
--================================================================================================= --=================================================================================================
......
wf_model_constr_decoder.vhd
View file @ 297713da
...@@ -29,7 +29,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -29,7 +29,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
--! @brief Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID. --! @brief Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID.
--! The output S_ID0 is a clock with period the double of uclk's period and the S_ID1 --! The output S_ID0 is a clock with period the double of uclk's period and the S_ID1
--! is the opposite clock (it is '0' when S_ID0 is '1' and '1' when S_ID0 is '0'). --! is the opposite clock (it is '0' when S_ID0 is '1' and '1' when S_ID0 is '0').
--! Each one of the 4 pins of the M_ID and C_ID can be connected to either Vcc, Gnd, --! Each one of the 4 pins of the M_ID and C_ID can be connected to either Vcc, Gnd,
--! S_ID1 or S_ID0. Like this (after 2 uclk periods) the 8 bits of the Model and --! S_ID1 or S_ID0. Like this (after 2 uclk periods) the 8 bits of the Model and
--! Constructor words take a value, according to the table: Gnd 00 --! Constructor words take a value, according to the table: Gnd 00
...@@ -47,7 +47,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -47,7 +47,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.03 --! @version v0.03
-- --
-- --
--! @details\n --! @details\n
-- --
--! \n<b>Dependencies:</b> \n --! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n --! WF_reset_unit \n
...@@ -62,7 +62,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -62,7 +62,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! -> 11/09/2009 v0.01 PAS First version \n --! -> 11/09/2009 v0.01 PAS First version \n
--! -> 20/08/2010 v0.02 EG S_ID corrected so that S_ID0 is always the opposite of S_ID1 --! -> 20/08/2010 v0.02 EG S_ID corrected so that S_ID0 is always the opposite of S_ID1
--! "for" loop replaced with signals concatenation; --! "for" loop replaced with signals concatenation;
--! Counter is of c_RELOAD_MID_CID bits; Code cleaned-up \n --! Counter is of c_RELOAD_MID_CID bits; Code cleaned-up \n
--! -> 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed; --! -> 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed;
--! counter unit instantiated --! counter unit instantiated
...@@ -70,8 +70,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -70,8 +70,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo --! @todo
--! -> select_id_o not the output of a dff:-s --! -> select_id_o not the output of a dff:-s
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -83,7 +83,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -83,7 +83,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_model_constr_decoder is entity WF_model_constr_decoder is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface general signal -- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 Mhz clock uclk_i : in std_logic; --! 40 Mhz clock
...@@ -114,7 +114,7 @@ architecture rtl of WF_model_constr_decoder is ...@@ -114,7 +114,7 @@ architecture rtl of WF_model_constr_decoder is
signal s_counter_is_full : std_logic; signal s_counter_is_full : std_logic;
signal s_counter : unsigned (1 downto 0); signal s_counter : unsigned (1 downto 0);
signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0); signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0);
signal s_constr_stage2, s_constr_stage1 : std_logic_vector (3 downto 0); signal s_constr_stage2, s_constr_stage1 : std_logic_vector (3 downto 0);
...@@ -144,7 +144,7 @@ begin ...@@ -144,7 +144,7 @@ begin
s_constr_stage2 <= (others => '0'); s_constr_stage2 <= (others => '0');
else else
s_model_stage2 <= s_model_stage1; -- after 2 uclk ticks stage1 keeps the even bits s_model_stage2 <= s_model_stage1; -- after 2 uclk ticks stage1 keeps the even bits
s_model_stage1 <= model_id_i; -- and stage2 the odd ones s_model_stage1 <= model_id_i; -- and stage2 the odd ones
...@@ -154,12 +154,12 @@ begin ...@@ -154,12 +154,12 @@ begin
if s_counter = "10" then if s_counter = "10" then
model_id_dec_o <= s_model_stage2(3) & s_model_stage1(3) & -- putting together model_id_dec_o <= s_model_stage2(3) & s_model_stage1(3) & -- putting together
s_model_stage2(2) & s_model_stage1(2) & -- even and odd bits s_model_stage2(2) & s_model_stage1(2) & -- even and odd bits
s_model_stage2(1) & s_model_stage1(1) & s_model_stage2(1) & s_model_stage1(1) &
s_model_stage2(0) & s_model_stage1(0); s_model_stage2(0) & s_model_stage1(0);
constr_id_dec_o <= s_constr_stage2(3) & s_constr_stage1(3) & constr_id_dec_o <= s_constr_stage2(3) & s_constr_stage1(3) &
s_constr_stage2(2) & s_constr_stage1(2) & s_constr_stage2(2) & s_constr_stage1(2) &
s_constr_stage2(1) & s_constr_stage1(1) & s_constr_stage2(1) & s_constr_stage1(1) &
s_constr_stage2(0) & s_constr_stage1(0); s_constr_stage2(0) & s_constr_stage1(0);
...@@ -183,13 +183,13 @@ begin ...@@ -183,13 +183,13 @@ begin
counter_o => s_counter, counter_o => s_counter,
counter_is_full_o => s_counter_is_full); counter_is_full_o => s_counter_is_full);
----------------------------------------- -----------------------------------------
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Concurrent signal assignment for the output select_id_o --!@brief Concurrent signal assignment for the output select_id_o
select_id_o <= ((not s_counter(0)) & s_counter(0));-- 2 opposite clocks generated using select_id_o <= ((not s_counter(0)) & s_counter(0));-- 2 opposite clocks generated using
-- the LSB of the counter -- the LSB of the counter
-- uclk_i: |-|__|-|__|-|__|-|__|-|__|-|_ -- uclk_i: |-|__|-|__|-|__|-|__|-|__|-|_
-- S_ID0 : |----|____|----|____|----|___ -- S_ID0 : |----|____|----|____|----|___
-- S_ID1 : |____|----|____|----|____|--- -- S_ID1 : |____|----|____|----|____|---
......
wf_package.vhd
View file @ 297713da
This diff is collapsed.
wf_prod_bytes_retriever.vhd
View file @ 297713da
This diff is collapsed.
wf_prod_data_lgth_calc.vhd
View file @ 297713da
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
--! standard packages --! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
...@@ -61,7 +61,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -61,7 +61,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.02 --! @version v0.02
-- --
-- --
--! @details \n --! @details \n
-- --
--! \n<b>Dependencies:</b> \n --! \n<b>Dependencies:</b> \n
--! WF_engine_control \n --! WF_engine_control \n
...@@ -70,19 +70,19 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -70,19 +70,19 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! -> 12/2010 v0.02 EG code cleaned-up+commented --! -> 12/2010 v0.02 EG code cleaned-up+commented
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo --! @todo
--! -> --! ->
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -93,7 +93,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -93,7 +93,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_prod_data_lgth_calc is entity WF_prod_data_lgth_calc is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP WorldFIP Settings -- nanoFIP WorldFIP Settings
p3_lgth_i : in std_logic_vector (2 downto 0); --! produced var user-data length p3_lgth_i : in std_logic_vector (2 downto 0); --! produced var user-data length
...@@ -123,15 +123,15 @@ architecture behavior of WF_prod_data_lgth_calc is ...@@ -123,15 +123,15 @@ architecture behavior of WF_prod_data_lgth_calc is
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
--================================================================================================= --=================================================================================================
begin begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief: Combinatorial process data_length_calcul: calculation of the amount of bytes, after the --!@brief: Combinatorial process data_length_calcul: calculation of the amount of bytes, after the
--! FSS and before the FCS, that have to be transferred when a variable is produced. In the case --! FSS and before the FCS, that have to be transferred when a variable is produced. In the case
--! of the presence and the identification variables, the data length is predefined in the WF_package. --! of the presence and the identification variables, the data length is predefined in the WF_package.
--! In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the calculation. --! In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the calculation.
data_length_calcul: process (var_i, s_p3_lgth_decoded, slone_i, nostat_i, p3_lgth_i) data_length_calcul: process (var_i, s_p3_lgth_decoded, slone_i, nostat_i, p3_lgth_i)
begin begin
...@@ -141,19 +141,19 @@ begin ...@@ -141,19 +141,19 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_presence => when var_presence =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package) -- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_lgth; s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_identif => when var_identif =>
-- data length information retreival from the c_VARS_ARRAY matrix (WF_package) -- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_lgth; s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_lgth;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_3 => when var_3 =>
-- data length calculation according to the operational mode (memory or stand-alone) -- data length calculation according to the operational mode (memory or stand-alone)
-- in slone mode 2 bytes of user-data are produced(independently of P3_LGTH) -- in slone mode 2 bytes of user-data are produced(independently of P3_LGTH)
...@@ -162,21 +162,21 @@ begin ...@@ -162,21 +162,21 @@ begin
-- 1 byte Length -- 1 byte Length
-- 1 byte MPS status -- 1 byte MPS status
-- optionally 1 byte nFIP status -- optionally 1 byte nFIP status
-- in memory mode the signal "s_p3_lgth_decoded" indicates the amount of user-data -- in memory mode the signal "s_p3_lgth_decoded" indicates the amount of user-data
-- to these, there should be added 1 byte Control -- to these, there should be added 1 byte Control
-- 1 byte PDU_TYPE -- 1 byte PDU_TYPE
-- 1 byte Length -- 1 byte Length
-- 1 byte MPS status -- 1 byte MPS status
-- optionally 1 byte nFIP status -- optionally 1 byte nFIP status
if slone_i = '1' then if slone_i = '1' then
if nostat_i = '1' then -- 6 bytes (counting starts from 0) if nostat_i = '1' then -- 6 bytes (counting starts from 0)
s_prod_data_lgth <= to_unsigned(5, s_prod_data_lgth'length); s_prod_data_lgth <= to_unsigned(5, s_prod_data_lgth'length);
else -- 7 bytes else -- 7 bytes
s_prod_data_lgth <= to_unsigned(6, s_prod_data_lgth'length); s_prod_data_lgth <= to_unsigned(6, s_prod_data_lgth'length);
end if; end if;
...@@ -186,21 +186,21 @@ begin ...@@ -186,21 +186,21 @@ begin
else else
s_prod_data_lgth <= s_p3_lgth_decoded + 3; s_prod_data_lgth <= s_p3_lgth_decoded + 3;
end if; end if;
end if; end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when var_1 | var_2 | var_rst => when var_1 | var_2 | var_rst =>
s_prod_data_lgth <= (others => '0'); s_prod_data_lgth <= (others => '0');
when others => when others =>
s_prod_data_lgth <= (others => '0'); s_prod_data_lgth <= (others => '0');
end case; end case;
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment for the output -- Concurrent signal assignment for the output
prod_data_lgth_o <= std_logic_vector (s_prod_data_lgth); prod_data_lgth_o <= std_logic_vector (s_prod_data_lgth);
......
wf_prod_permit.vhd
View file @ 297713da
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
--! standard packages --! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
...@@ -28,7 +28,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -28,7 +28,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
-- --
--! @brief Generation of the "nanoFIP User Interface, NON_WISHBONE" output signal VAR3_RDY, --! @brief Generation of the "nanoFIP User Interface, NON_WISHBONE" output signal VAR3_RDY,
--! according to the variable (var_i) that is being treated. --! according to the variable (var_i) that is being treated.
-- --
-- --
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
...@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.01 --! @version v0.01
-- --
-- --
--! @details \n --! @details \n
-- --
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
--! WF_engine_control \n --! WF_engine_control \n
...@@ -51,16 +51,16 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -51,16 +51,16 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! -> 1/2011 v0.01 EG First version \n --! -> 1/2011 v0.01 EG First version \n
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo --! @todo
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -71,7 +71,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -71,7 +71,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_prod_permit is entity WF_prod_permit is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface, General signals -- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
...@@ -97,11 +97,11 @@ architecture rtl of WF_prod_permit is ...@@ -97,11 +97,11 @@ architecture rtl of WF_prod_permit is
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
--================================================================================================= --=================================================================================================
begin begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Synchronous process VAR3_RDY_Generation: --!@brief Synchronous process VAR3_RDY_Generation:
--! VAR3_RDY (for produced vars): signals that the user can safely write to the produced variable --! VAR3_RDY (for produced vars): signals that the user can safely write to the produced variable
--! memory or access the DAT_I bus. It is deasserted right after the end of the reception of a --! memory or access the DAT_I bus. It is deasserted right after the end of the reception of a
...@@ -115,7 +115,7 @@ begin ...@@ -115,7 +115,7 @@ begin
--! transmission of the corresponding RP_DAT (in detail, until the end of the transmission of the --! transmission of the corresponding RP_DAT (in detail, until the end of the transmission of the
--! RP_DAT.data field;var_i becomes var_whatever during the RP_DAT.FCS and RP_DAT.FES transmission). --! RP_DAT.data field;var_i becomes var_whatever during the RP_DAT.FCS and RP_DAT.FES transmission).
VAR_RDY_Generation: process (uclk_i) VAR_RDY_Generation: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_rst_i = '1' then if nfip_rst_i = '1' then
...@@ -125,17 +125,17 @@ begin ...@@ -125,17 +125,17 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
case var_i is case var_i is
when var_3 => -- nanoFIP is producing when var_3 => -- nanoFIP is producing
--------------------- ---------------------
var3_rdy_o <= '0'; -- while producing, VAR3_RDY is 0 var3_rdy_o <= '0'; -- while producing, VAR3_RDY is 0
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others => when others =>
var3_rdy_o <= '1'; var3_rdy_o <= '1';
end case; end case;
end if; end if;
end if; end if;
end process; end process;
......
wf_production.vhd
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wf_reset_unit.vhd
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wf_rx_deglitcher.vhd
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...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
--! standard packages --! standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
...@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @version v0.03 --! @version v0.03
-- --
-- --
--! @details --! @details
-- --
--! \n<b>Dependencies:</b> \n --! \n<b>Dependencies:</b> \n
--! WF_reset_unit \n --! WF_reset_unit \n
...@@ -49,7 +49,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -49,7 +49,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n --! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
...@@ -61,7 +61,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -61,7 +61,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo --! @todo
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -73,19 +73,19 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -73,19 +73,19 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
entity WF_rx_deglitcher is entity WF_rx_deglitcher is
port( port(
-- INPUTS -- INPUTS
-- nanoFIP User Interface general signal -- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- nanoFIP FIELDRIVE (synchronized with uclk) -- nanoFIP FIELDRIVE (synchronized with uclk)
fd_rxd_a_i : in std_logic; --! receiver data fd_rxd_a_i : in std_logic; --! receiver data
-- OUTPUTS -- OUTPUTS
-- Signals to the WF_rx_deserializer unit -- Signals to the WF_rx_deserializer unit
fd_rxd_filtered_o : out std_logic; --! filtered output signal fd_rxd_filtered_o : out std_logic; --! filtered output signal
fd_rxd_filtered_edge_p_o : out std_logic; --! indicates an edge on the filtered signal fd_rxd_filtered_edge_p_o : out std_logic; --! indicates an edge on the filtered signal
...@@ -125,7 +125,7 @@ begin ...@@ -125,7 +125,7 @@ begin
else else
s_fd_rxd_synch <= s_fd_rxd_synch(0) & fd_rxd_a_i; s_fd_rxd_synch <= s_fd_rxd_synch(0) & fd_rxd_a_i;
end if; end if;
end if; end if;
end process; end process;
...@@ -158,7 +158,7 @@ begin ...@@ -158,7 +158,7 @@ begin
if s_deglitch_c /= c_DEGLITCH_THRESHOLD then if s_deglitch_c /= c_DEGLITCH_THRESHOLD then
s_deglitch_c <= s_deglitch_c + 1; -- counter updated s_deglitch_c <= s_deglitch_c + 1; -- counter updated
else else
s_rxd_filtered <= '1'; -- output updated s_rxd_filtered <= '1'; -- output updated
end if; -- if counter = c_DEGLITCH_THRESHOLD end if; -- if counter = c_DEGLITCH_THRESHOLD
......
wf_rx_deserializer.vhd
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wf_rx_osc.vhd
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wf_status_bytes_gen.vhd
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wf_tx_osc.vhd
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wf_tx_serializer.vhd
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wf_wb_controller.vhd
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