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nanoFIP - Gateware
Commit 4303602e authored by egousiou's avatar egousiou
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- correction on bytes counters (there were errors when 124 data bytes had to be… 

- correction on bytes counters (there were errors when 124 data bytes had to be sent and the vectors of (6 downto 0) were changed to (7 downto 0))

 - correction on nFIP status byte generation

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@69 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 1a34c6d9
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nanofip.vhd
View file @ 4303602e
......@@ -97,9 +97,7 @@ entity nanofip is
port (
-- WorldFIP settings
rate_i : in std_logic_vector (1 downto 0); --! Bit rate
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding.
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
......@@ -189,7 +187,7 @@ architecture struc of nanofip is
end component;
signal s_data_length_from_control : std_logic_vector(6 downto 0);
signal s_data_length_from_control : std_logic_vector(7 downto 0);
signal s_byte_to_tx : std_logic_vector(7 downto 0);
signal s_rst : std_logic;
signal s_start_send_p : std_logic;
......@@ -200,12 +198,11 @@ architecture struc of nanofip is
signal s_byte_from_rx : std_logic_vector(7 downto 0);
signal s_cons_byte_we_from_control : std_logic;
signal s_var_from_control : t_var;
signal s_add_offset_from_control : std_logic_vector(6 downto 0);
signal addr_from_wb : std_logic_vector(9 downto 0);
signal s_add_offset_from_control : std_logic_vector(7 downto 0);
signal s_crc_ok_from_rx : std_logic;
signal fss_decoded_p_from_rx : std_logic;
signal s_stat : std_logic_vector(7 downto 0);
signal s_ack_produced, s_ack_consumed, s_ack_o: std_logic;
signal s_ack_produced, s_ack_consumed, s_ack_o: std_logic;
signal s_reset_status_bytes, s_sending_mps: std_logic;
signal s_code_violation_p : std_logic;
signal s_crc_bad_p : std_logic;
......@@ -213,11 +210,13 @@ architecture struc of nanofip is
signal s_var2_rdy : std_logic;
signal s_var3_rdy : std_logic;
signal s_mps : std_logic_vector(7 downto 0);
signal s_wb_d_d : std_logic_vector(15 downto 0);
signal s_m_id_dec_o, s_c_id_dec_o : std_logic_vector(7 downto 0);
signal s_stb_d, s_we_d, s_cyc_d : std_logic;
signal s_wb_data_d1, s_wb_data_d2, s_data_o : std_logic_vector(15 downto 0);
signal s_m_id_dec_o, s_c_id_dec_o : std_logic_vector(7 downto 0);
--signal s_stb_d, s_we_d, s_cyc_d : std_logic;
signal s_reset_nFIP_and_FD, s_reset_rston : std_logic;
signal s_adr_d : std_logic_vector ( 9 downto 0);
signal s_adr_d1, s_adr_d2 : std_logic_vector (9 downto 0);
signal s_stb_r_edge, s_stb_d1, s_stb_d2, s_stb_d3 : std_logic;
signal s_we_d1, s_we_d2, s_cyc_d1, s_cyc_d2 : std_logic;
begin
--=================================================================================================
......@@ -227,13 +226,13 @@ begin
---------------------------------------------------------------------------------------------------
ureset_logic : reset_logic
port map(
uclk_i => uclk_i,
rstin_i => rstin_i,
uclk_i => uclk_i,
rstin_i => rstin_i,
reset_nFIP_and_FD_i => s_reset_nFIP_and_FD,
reset_RSTON_i => s_reset_rston,
rston_o => rston_o,
nFIP_rst_o => s_rst,
fd_rstn_o => fd_rstn_o
reset_RSTON_i => s_reset_rston,
rston_o => rston_o,
nFIP_rst_o => s_rst,
fd_rstn_o => fd_rstn_o
);
---------------------------------------------------------------------------------------------------
......@@ -241,130 +240,131 @@ begin
generic map( C_QUARTZ_PERIOD => 25.0)
port map(
uclk_i => uclk_i,
nFIP_rst_i => s_rst,
uclk_i => uclk_i,
nFIP_rst_i => s_rst,
start_produce_p_o => s_start_send_p ,
request_byte_p_i => s_request_byte_from_tx_p,
byte_ready_p_o => s_byte_to_tx_ready_p,
last_byte_p_o => s_last_byte_to_tx_p,
fss_decoded_p_i => fss_decoded_p_from_rx,
byte_ready_p_i => s_byte_from_rx_ready_p,
byte_i => s_byte_from_rx,
frame_ok_p_i => s_crc_ok_from_rx,
rate_i => rate_i,
subs_i => subs_i,
p3_lgth_i => p3_lgth_i,
slone_i => slone_i,
nostat_i => nostat_i,
var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy,
var3_rdy_o => s_var3_rdy,
var_o => s_var_from_control,
add_offset_o => s_add_offset_from_control,
data_length_o => s_data_length_from_control,
consume_byte_p_o => s_cons_byte_we_from_control
request_byte_p_i => s_request_byte_from_tx_p,
byte_ready_p_o => s_byte_to_tx_ready_p,
last_byte_p_o => s_last_byte_to_tx_p,
fss_decoded_p_i => fss_decoded_p_from_rx,
byte_ready_p_i => s_byte_from_rx_ready_p,
byte_i => s_byte_from_rx,
frame_ok_p_i => s_crc_ok_from_rx,
rate_i => rate_i,
subs_i => subs_i,
p3_lgth_i => p3_lgth_i,
slone_i => slone_i,
nostat_i => nostat_i,
var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy,
var3_rdy_o => s_var3_rdy,
var_o => s_var_from_control,
add_offset_o => s_add_offset_from_control,
data_length_o => s_data_length_from_control,
consume_byte_p_o => s_cons_byte_we_from_control
);
---------------------------------------------------------------------------------------------------
uwf_tx_rx : wf_tx_rx
port map(
uclk_i => uclk_i,
nFIP_rst_i => s_rst,
start_produce_p_i => s_start_send_p,
request_byte_p_o => s_request_byte_from_tx_p,
byte_ready_p_i => s_byte_to_tx_ready_p,
byte_i => s_byte_to_tx,
last_byte_p_i => s_last_byte_to_tx_p,
tx_data_o => fx_txd_o,
tx_enable_o => fd_txena_o,
d_clk_o => fd_txck_o,
d_a_i => fx_rxd_i,
rate_i => rate_i,
byte_ready_p_o => s_byte_from_rx_ready_p,
byte_o => s_byte_from_rx,
fss_decoded_p_o => fss_decoded_p_from_rx,
last_byte_p_o => s_last_byte_from_rx_p,
uclk_i => uclk_i,
nFIP_rst_i => s_rst,
start_produce_p_i => s_start_send_p,
request_byte_p_o => s_request_byte_from_tx_p,
byte_ready_p_i => s_byte_to_tx_ready_p,
byte_i => s_byte_to_tx,
last_byte_p_i => s_last_byte_to_tx_p,
tx_data_o => fx_txd_o,
tx_enable_o => fd_txena_o,
d_clk_o => fd_txck_o,
d_a_i => fx_rxd_i,
rate_i => rate_i,
byte_ready_p_o => s_byte_from_rx_ready_p,
byte_o => s_byte_from_rx,
fss_decoded_p_o => fss_decoded_p_from_rx,
last_byte_p_o => s_last_byte_from_rx_p,
code_violation_p_o => s_code_violation_p,
crc_wrong_p_o => s_crc_bad_p,
crc_ok_p_o => s_crc_ok_from_rx
crc_wrong_p_o => s_crc_bad_p,
crc_ok_p_o => s_crc_ok_from_rx
);
---------------------------------------------------------------------------------------------------
uwf_consumed_vars : wf_consumed_vars
port map(
uclk_i => uclk_i,
nFIP_rst_i => s_rst,
slone_i => slone_i,
subs_i => subs_i,
byte_ready_p_i => s_cons_byte_we_from_control,
var_i => s_var_from_control,
index_offset_i => s_add_offset_from_control,
byte_i => s_byte_from_rx,
wb_rst_i => rst_i,
wb_clk_i => wclk_i,
wb_data_o => dat_o,
wb_adr_i => s_adr_d,
wb_stb_p_i => s_stb_d,
wb_ack_cons_p_o => s_ack_consumed,
uclk_i => uclk_i,
nFIP_rst_i => s_rst,
slone_i => slone_i,
subs_i => subs_i,
byte_ready_p_i => s_cons_byte_we_from_control,
var_i => s_var_from_control,
index_offset_i => s_add_offset_from_control,
byte_i => s_byte_from_rx,
wb_rst_i => rst_i,
wb_clk_i => wclk_i,
wb_adr_i => s_adr_d2,
wb_stb_r_edge_p_i => s_stb_r_edge,
wb_cyc_i => s_cyc_d2,
wb_ack_cons_p_o => s_ack_consumed,
data_o => dat_o,
reset_nFIP_and_FD_o => s_reset_nFIP_and_FD,
reset_RSTON_o => s_reset_rston
reset_RSTON_o => s_reset_rston
);
---------------------------------------------------------------------------------------------------
uwf_produced_vars : wf_produced_vars
port map(
uclk_i => uclk_i,
nFIP_rst_i => s_rst,
m_id_dec_i => s_m_id_dec_o,
c_id_dec_i => s_c_id_dec_o,
slone_i => slone_i,
nostat_i => nostat_i,
sending_mps_o => s_sending_mps,
uclk_i => uclk_i,
m_id_dec_i => s_m_id_dec_o,
c_id_dec_i => s_c_id_dec_o,
slone_i => slone_i,
nostat_i => nostat_i,
sending_mps_o => s_sending_mps,
nFIP_status_byte_i => s_stat,
mps_byte_i => s_mps,
var_i => s_var_from_control,
index_offset_i => s_add_offset_from_control,
data_length_i => s_data_length_from_control,
byte_o => s_byte_to_tx,
wb_rst_i => rst_i,
data_i => s_wb_d_d,
wb_clk_i => wclk_i,
wb_adr_i => s_adr_d,
wb_stb_p_i => s_stb_d,
wb_cyc_i => s_cyc_d,
wb_ack_prod_p_o => s_ack_produced,
wb_we_p_i => s_we_d
mps_byte_i => s_mps,
var_i => s_var_from_control,
index_offset_i => s_add_offset_from_control,
data_length_i => s_data_length_from_control,
byte_o => s_byte_to_tx,
wb_rst_i => rst_i,
data_i => s_wb_data_d2,
wb_clk_i => wclk_i,
wb_adr_i => s_adr_d2,
wb_stb_r_edge_p_i => s_stb_r_edge,
wb_cyc_i => s_cyc_d2,
wb_ack_prod_p_o => s_ack_produced,
wb_we_p_i => s_we_d2
);
---------------------------------------------------------------------------------------------------
ustatus_gen : status_gen
port map(
uclk_i => uclk_i,
nFIP_rst_i => s_rst,
slone_i => slone_i,
fd_wdgn_i => fd_wdgn_i,
fd_txer_i => fd_txer_i,
code_violation_p_i => s_code_violation_p,
crc_wrong_p_i => s_crc_bad_p,
var1_rdy_i => s_var1_rdy,
var2_rdy_i => s_var2_rdy,
var3_rdy_i => s_var3_rdy,
var1_access_a_i => var1_acc_i,
var2_access_a_i => var2_acc_i,
var3_access_a_i => var3_acc_i,
uclk_i => uclk_i,
nFIP_rst_i => s_rst,
slone_i => slone_i,
fd_wdgn_i => fd_wdgn_i,
fd_txer_i => fd_txer_i,
code_violation_p_i => s_code_violation_p,
crc_wrong_p_i => s_crc_bad_p,
var_i => s_var_from_control,
var1_rdy_i => s_var1_rdy,
var2_rdy_i => s_var2_rdy,
var3_rdy_i => s_var3_rdy,
var1_access_a_i => var1_acc_i,
var2_access_a_i => var2_acc_i,
var3_access_a_i => var3_acc_i,
reset_status_bytes_i => s_reset_status_bytes,
status_byte_o => s_stat,
mps_byte_o => s_mps
status_byte_o => s_stat,
mps_byte_o => s_mps
);
---------------------------------------------------------------------------------------------------
Uwf_dec_m_ids : wf_dec_m_ids
port map(
uclk_i => uclk_i,
nFIP_rst_i => s_rst,
nFIP_rst_i => s_rst,
s_id_o => s_id_o,
m_id_dec_o => s_m_id_dec_o,
c_id_dec_o => s_c_id_dec_o,
......@@ -379,24 +379,45 @@ WISHBONE_input_signals_buffering: process(wclk_i)
begin
if rising_edge(wclk_i) then
if rst_i = '1' then -- reset not buffered to comply with WISHBONE rule 3.15
s_wb_d_d <= (others => '0');
s_stb_d <= '0';
s_we_d <= '0';
s_adr_d <= (others => '0');
s_wb_data_d1 <= (others => '0');
s_wb_data_d2 <= (others => '0');
s_adr_d1 <= (others => '0');
s_adr_d2 <= (others => '0');
s_stb_d1 <= '0';
s_stb_d2 <= '0';
s_stb_d3 <= '0';
s_cyc_d1 <= '0';
s_cyc_d2 <= '0';
s_we_d1 <= '0';
s_we_d2 <= '0';
else
s_wb_d_d <= dat_i;
s_cyc_d <= cyc_i;
s_stb_d <= stb_i;
s_we_d <= we_i;
s_adr_d <= adr_i;
s_wb_data_d2 <= s_wb_data_d1;
s_wb_data_d1 <= dat_i;
s_adr_d2 <= s_adr_d1;
s_adr_d1 <= adr_i;
s_stb_d1 <= stb_i;
s_stb_d2 <= s_stb_d1;
s_stb_d3 <= s_stb_d2;
s_cyc_d1 <= cyc_i;
s_cyc_d2 <= s_cyc_d1;
s_we_d1 <= we_i;
s_we_d2 <= s_we_d1;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
s_stb_r_edge <= (not s_stb_d3) and s_stb_d2;
ack_o <= (s_ack_produced or s_ack_consumed); --and stb_i;
s_ack_o <= s_ack_produced or s_ack_consumed;
s_reset_status_bytes <= s_sending_mps and s_byte_to_tx_ready_p;
s_reset_status_bytes <= s_sending_mps and s_byte_to_tx_ready_p; -- at the end of the transmission
---------------------------------------------------------------------------------------------------
var1_rdy_o <= s_var1_rdy; --! Variable 1 ready
......
status_gen.vhd
View file @ 4303602e
......@@ -90,9 +90,11 @@ port (
crc_wrong_p_i : in std_logic;
-- Signals from the central control unit wf_engine_control
var_i : in t_var; --! variable type
var1_rdy_i : in std_logic; --! Variable 1 ready
var2_rdy_i : in std_logic; --! Variable 2 ready
var3_rdy_i : in std_logic; --! Variable 3 ready
-- Signal from nanofip
reset_status_bytes_i : in std_logic;
......@@ -100,8 +102,8 @@ port (
-- OUTPUTS
-- Output to wf_produced_vars
status_byte_o : out std_logic_vector(7 downto 0); --! status byte
mps_byte_o : out std_logic_vector(7 downto 0) --! mps byte
status_byte_o : out std_logic_vector(7 downto 0); --! status byte
mps_byte_o : out std_logic_vector(7 downto 0) --! mps byte
);
end entity status_gen;
......@@ -127,9 +129,9 @@ begin
begin
if rising_edge (uclk_i) then
if nFIP_rst_i = '1' then
s_var1_access <= (others => '0');
s_var2_access <= (others => '0');
s_var3_access <= (others => '0');
s_var1_access <= (others => '0');
s_var2_access <= (others => '0');
s_var3_access <= (others => '0');
else
s_var1_access(0) <= var1_access_a_i;
s_var2_access(0) <= var2_access_a_i;
......@@ -150,36 +152,43 @@ begin
if rising_edge(uclk_i) then
if ((nFIP_rst_i = '1') or (reset_status_bytes_i = '1')) then
status_byte_o <= (others => '0');
if ((nFIP_rst_i = '1') or (reset_status_bytes_i = '1')) then -- the byte is reinitialized
status_byte_o <= (others => '0'); -- after having been delivered
else
if ((var1_rdy_i = '0' and s_var1_access(1) = '1') or -- the user logic accessed a cosumed
(var2_rdy_i = '0' and s_var2_access(1) = '1')) then -- variable when it was not ready
status_byte_o(c_U_CACER_INDEX) <= '1';
end if;
if ((var3_rdy_i = '0') and (s_var3_access(1) = '1')) then -- the user logic accessed a prod
status_byte_o(c_U_PACER_INDEX) <= '1'; -- variable when it was not ready
end if;
if (code_violation_p_i = '1') then -- a variable arrived for this
status_byte_o(c_R_BNER_INDEX) <= '1'; -- station with a manchester 2
end if; -- violation
if (crc_wrong_p_i = '1') then -- a variable arrived for this station with wrong checksum
status_byte_o(c_R_FCSER_INDEX) <= '1';
end if;
if (fd_wdgn_i = '1') then -- the FIELDRIVE signalled a transmission error
status_byte_o(c_T_TXER_INDEX) <= '1';
end if;
if (fd_txer_i = '1') then -- the FIELDRIVE signalled a watchdog timer problem
status_byte_o(c_T_WDER_INDEX) <= '1';
end if;
if ((var1_rdy_i = '0' and s_var1_access(1) = '1') or -- since the last time the status
(var2_rdy_i = '0' and s_var2_access(1) = '1')) then -- byte was delivered,
status_byte_o(c_U_CACER_INDEX) <= '1'; -- the user logic accessed a cosmd
end if; -- variable when it was not ready
if ((var3_rdy_i = '0') and (s_var3_access(1) = '1')) then -- since the last time the status
status_byte_o(c_U_PACER_INDEX) <= '1'; -- byte was delivered,
end if; -- the user logic accessed a prod
-- variable when it was not ready
if ((var_i = var_1 or var_i = var_2) and (code_violation_p_i = '1')) then
status_byte_o(c_R_BNER_INDEX) <= '1'; -- since the last time the status
-- byte was delivered,
end if; -- a consumed var arrived for
-- this station with a manch code
-- violation (on the rp_dat.Data)
if ((var_i = var_1 or var_i = var_2)and(crc_wrong_p_i = '1')) then
status_byte_o(c_R_FCSER_INDEX) <= '1'; -- since the last time the status
-- byte was delivered,
end if; -- a consumed var with a wrong CRC
-- arrived for this station
if (fd_wdgn_i = '0') then -- since the last time the status
status_byte_o(c_T_TXER_INDEX) <= '1'; -- byte was delivered,
end if; -- there has been a signal for
-- a FIELDRIVE transmission error
if (fd_txer_i = '1') then -- since the last time the status
status_byte_o(c_T_WDER_INDEX) <= '1'; -- byte was delivered,
end if; -- there has been a signal for a
-- FIELDRIVE watchdog timer problem
end if;
end if;
end process;
......@@ -195,7 +204,7 @@ end process;
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' or reset_status_bytes_i = '1' then
s_refreshment <= '0';
s_refreshment <= '0';
else
if (var3_access_a_i = '1') then
......@@ -215,12 +224,12 @@ end process;
begin
if slone_i='1' then
mps_byte_o <= (others => '0');
mps_byte_o (c_REFRESHMENT_INDEX) <= '1';
mps_byte_o (c_REFRESHMENT_INDEX) <= '1';
mps_byte_o (c_SIGNIFICANCE_INDEX) <= '1';
else
mps_byte_o <= (others => '0');
mps_byte_o (c_REFRESHMENT_INDEX) <= s_refreshment;
mps_byte_o (c_REFRESHMENT_INDEX) <= s_refreshment;
mps_byte_o (c_SIGNIFICANCE_INDEX) <= s_refreshment;
end if;
end process;
......
wf_consumed_vars.vhd
View file @ 4303602e
......@@ -87,14 +87,18 @@ port (
-- (buffered once with wb_clk)
-- note: msb allways 0!
wb_stb_p_i : in std_logic; --! wishbone strobe
-- (buffered once with wb_clk)
wb_stb_r_edge_p_i : in std_logic; --! pulse on the rising edge of stb_i
-- the pulse appears 2 wclk ticks after
-- a rising edge on the stb_i
-- note: indication that master
-- is ready to transfer data
wb_cyc_i : in std_logic; --! wishbone cycle
-- indicates a valid cycle in progress
-- Signals for the wf_engine_control
byte_ready_p_i : in std_logic;
index_offset_i : in std_logic_vector(6 downto 0);
index_offset_i : in std_logic_vector(7 downto 0);
var_i : in t_var;
-- Signals for the receiver wf_rx
......@@ -103,7 +107,7 @@ port (
-- OUTPUTS
-- User Interface WISHBONE slave
wb_data_o : out std_logic_vector (15 downto 0); --!
data_o : out std_logic_vector (15 downto 0); --!
wb_ack_cons_p_o : out std_logic; --! Acknowledge
-- OUTPUTS to the wf_reset_logic
......@@ -122,9 +126,8 @@ architecture rtl of wf_consumed_vars is
signal s_addr: std_logic_vector(8 downto 0);
signal s_mem_data_out : std_logic_vector(7 downto 0);
signal s_slone_write_byte_p : std_logic_vector(1 downto 0);
signal s_slone_data_out : std_logic_vector(15 downto 0);
signal s_base_addr : unsigned(8 downto 0);
signal s_write_byte_to_mem_p, wb_ack_cons_p_o_d: std_logic;
signal s_write_byte_to_mem_p : std_logic;
signal s_rp_dat_control_byte_ok : std_logic := '0'; -- for simulation esthetics
--=================================================================================================
......@@ -157,36 +160,16 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Generate_wb_ack_cons_p_o: Generation of the wb_ack_cons_p_o signal
--!@brief Generate_wb_ack_cons_p_o: Generation of the wb_ack_cons_p_o signal
--! (acknowledgement from wishbone slave of the read cycle, as a response to the master's storbe).
--! wb_ack_cons_p_o is asserted two wb_clk cycles after the assertion of the input strobe signal,
--! (reminder: stb_i is buffered once in the input stage), if the wishbone input address
--! corresponds to an address in the Consumed memory block.
Generate_wb_ack_cons_p_o: process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
wb_ack_cons_p_o_d <= '0';
else
if wb_adr_i(9 downto 8) = "00" then -- checking of the 2 first bits of the address,
-- to confirm that the request to write is on
-- the Cosumed or Cosumed broadcast memory block
wb_ack_cons_p_o_d <= wb_stb_p_i; -- slave's indication: valid data available
else
wb_ack_cons_p_o_d <= '0';
end if;
end if;
end if;
end process;
wb_ack_cons_p_o <= wb_stb_p_i;
--! if the wishbone cycle signal is asserted and the wishbone input address corresponds to an
--! address in the Consumed memory block.
Generate_wb_ack_cons_p_o: wb_ack_cons_p_o <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_i(9 downto 8) = "00") and
(wb_cyc_i = '1'))
else '0';
---------------------------------------------------------------------------------------------------
--!@brief combinatorial process Check_rp_dat_control_byte:Verification of wether the rp_dat.Control
......@@ -226,7 +209,8 @@ end process;
--! Note: in stand-alone mode nanoFIP does not handdle the var2 broadcast variable.
Bytes_Consumption: process (var_i, index_offset_i, slone_i, byte_ready_p_i)
Bytes_Consumption: process (s_rp_dat_control_byte_ok, var_i, index_offset_i, slone_i, byte_i,
subs_i, byte_ready_p_i, s_base_addr)
begin
if s_rp_dat_control_byte_ok = '1' then -- only if the rp_dat.control byte is correct the
......@@ -241,16 +225,17 @@ Bytes_Consumption: process (var_i, index_offset_i, slone_i, byte_ready_p_i)
when var_1 =>
reset_RSTON_o <= '0';
reset_nFIP_and_FD_o <= '0';
s_base_addr <= c_VARS_ARRAY(c_VAR_1_INDEX).base_add; -- base addr info from the wf_package
reset_RSTON_o <= '0';
reset_nFIP_and_FD_o <= '0';
s_base_addr <= c_VARS_ARRAY(c_VAR_1_INDEX).base_add; -- base addr info
-- from wf_package
-- -- -- -- -- -- -- -- -- -- -- --
-- in memory mode
if slone_i = '0' then
s_slone_write_byte_p <= (others => '0');
s_write_byte_to_mem_p <= byte_ready_p_i; -- managment of the write enable signal
-- of the Consumed memory
......@@ -260,12 +245,12 @@ Bytes_Consumption: process (var_i, index_offset_i, slone_i, byte_ready_p_i)
s_write_byte_to_mem_p <= '0';
if index_offset_i = c_1st_byte_addr then -- 1st byte to be transferred
s_slone_write_byte_p(0) <= byte_ready_p_i ;
if index_offset_i = c_1st_BYTE_INDEX then -- 1st byte to be transferred
s_slone_write_byte_p(0) <= byte_ready_p_i;
end if;
if index_offset_i = c_2nd_byte_addr then -- 2nd byte to be transferred
s_slone_write_byte_p(1) <= byte_ready_p_i ;
if index_offset_i = c_2nd_BYTE_INDEX then -- 2nd byte to be transferred
s_slone_write_byte_p(1) <= byte_ready_p_i;
end if;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -273,15 +258,16 @@ Bytes_Consumption: process (var_i, index_offset_i, slone_i, byte_ready_p_i)
when var_2 =>
reset_nFIP_and_FD_o <= '0';
reset_RSTON_o <= '0';
s_base_addr <= c_VARS_ARRAY(c_VAR_2_INDEX).base_add;-- base addr info from the wf_package
reset_nFIP_and_FD_o <= '0';
reset_RSTON_o <= '0';
s_base_addr <= c_VARS_ARRAY(c_VAR_2_INDEX).base_add; -- base addr info
-- from wf_package
-- -- -- -- -- -- -- -- -- -- -- --
-- in memory mode
if slone_i = '0' then
s_slone_write_byte_p <= (others => '0');
s_slone_write_byte_p <= (others => '0');
s_write_byte_to_mem_p <= byte_ready_p_i; -- managment of the write enable signal
-- of the Consumed memory(same as in var_1)
......@@ -290,51 +276,52 @@ Bytes_Consumption: process (var_i, index_offset_i, slone_i, byte_ready_p_i)
-- in stand-alone mode
else -- in slone mode nanoFIP is not able to
s_write_byte_to_mem_p <= '0'; -- receive the broadcast variable
s_slone_write_byte_p <= (others => '0');
s_slone_write_byte_p <= (others => '0');
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when reset_var =>
s_write_byte_to_mem_p <= '0';
s_slone_write_byte_p <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_RESET_VAR_INDEX).base_add;-- base addr info from the wf_package
s_write_byte_to_mem_p <= '0';
s_slone_write_byte_p <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_RESET_VAR_INDEX).base_add; -- base addr info
--from wf_package
if ((byte_ready_p_i = '1')and(index_offset_i = c_1st_byte_addr)) then -- 1st byte
if ((byte_ready_p_i = '1')and(index_offset_i = c_1st_BYTE_INDEX)) then -- 1st byte
if byte_i = subs_i then
reset_nFIP_and_FD_o <= '1'; -- reset_nFIP_and_FD_o stays asserted until
end if; -- the end of this rp_dat frame
elsif ((byte_ready_p_i='1')and(index_offset_i=c_2nd_byte_addr)) then -- 2nd byte
elsif ((byte_ready_p_i='1')and(index_offset_i=c_2nd_BYTE_INDEX)) then -- 2nd byte
if byte_i = subs_i then
reset_RSTON_o <= '1'; -- reset_RSTON_o stays asserted until
reset_RSTON_o <= '1'; -- reset_RSTON_o stays asserted until
end if; -- the end of this rp_dat frame
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
reset_RSTON_o <= '0';
reset_nFIP_and_FD_o <= '0';
s_write_byte_to_mem_p <= '0';
s_base_addr <= (others => '0');
s_slone_write_byte_p <= (others => '0');
reset_RSTON_o <= '0';
reset_nFIP_and_FD_o <= '0';
s_write_byte_to_mem_p <= '0';
s_base_addr <= (others => '0');
s_slone_write_byte_p <= (others => '0');
end case;
else -- if the rp_dat.control byte is incorrect,
-- none of the incoming bytes is considered
reset_RSTON_o <= '0';
reset_nFIP_and_FD_o <= '0';
s_write_byte_to_mem_p <= '0';
s_addr <= (others => '0');
s_base_addr <= (others => '0');
s_slone_write_byte_p <= (others => '0');
reset_RSTON_o <= '0';
reset_nFIP_and_FD_o <= '0';
s_write_byte_to_mem_p <= '0';
s_addr <= (others => '0');
s_base_addr <= (others => '0');
s_slone_write_byte_p <= (others => '0');
end if;
......@@ -352,7 +339,7 @@ Data_Transfer_To_Dat_o: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then
wb_data_o <= (others => '0'); -- bus initialization
data_o <= (others => '0'); -- bus initialization
else
......@@ -361,25 +348,27 @@ begin
if slone_i = '1' then -- 2 data bytes have to be transferred
if s_slone_write_byte_p(0) = '1' then -- the 1st byte is written in the lsb of the bus
wb_data_o(7 downto 0) <= byte_i; -- the data stays there until a new byte arrives
data_o(7 downto 0) <= byte_i; -- the data stays there until a new byte arrives
end if;
if s_slone_write_byte_p(1) = '1' then -- the 2nd byte is written in the msb of the bus
wb_data_o(15 downto 8) <= byte_i; -- the data stays there until a new byte arrives
data_o(15 downto 8) <= byte_i; -- the data stays there until a new byte arrives
end if;
-- -- -- -- -- -- -- -- -- -- -- --
-- in memory mode
else
wb_data_o(7 downto 0) <= s_mem_data_out; -- the lsb of the bus receives the byte that is
-- also written in the memory
data_o(7 downto 0) <= s_mem_data_out; -- the lsb of the bus receives the byte that is
-- also written in the memory
end if;
end if;
end if;
end process;
end architecture rtl;
--=================================================================================================
-- architecture end
......
wf_engine_control.vhd
View file @ 4303602e
......@@ -108,8 +108,8 @@ entity wf_engine_control is
last_byte_p_o : out std_logic;
start_produce_p_o : out std_logic;
var_o : out t_var;
add_offset_o : out std_logic_vector(6 downto 0);
data_length_o : out std_logic_vector(6 downto 0);
add_offset_o : out std_logic_vector(7 downto 0);
data_length_o : out std_logic_vector(7 downto 0);
consume_byte_p_o : out std_logic
);
......@@ -136,8 +136,8 @@ architecture rtl of wf_engine_control is
signal s_start_produce_p, s_start_produce_p_d1 : std_logic;
signal s_respon_silen_c_is_zero, s_broadcast_var : std_logic;
signal s_inc_bytes_c, s_reset_bytes_c, s_last_byte_p : std_logic;
signal s_data_length_match, s_byte_ready_p : std_logic;
signal s_p3_length_decoded, s_data_length : unsigned(6 downto 0);
signal s_data_length_match, s_byte_ready_p : std_logic;
signal s_p3_length_decoded, s_data_length : unsigned(7 downto 0);
signal s_bytes_c : unsigned(7 downto 0);
signal s_respon_silen_c, s_counter_top: signed(16 downto 0);
signal s_response_time, s_silence_time : signed(16 downto 0);
......@@ -273,62 +273,62 @@ begin
case control_st is
when idle =>
s_load_temp_var <= '0';
s_counter_reset <= '1';
s_inc_bytes_c <= '0';
s_reset_bytes_c <= '1';
s_load_var <= '0';
s_counter_top <= s_silence_time;
consume_byte_p_o <= '0';
s_load_temp_var <= '0';
s_counter_reset <= '1';
s_inc_bytes_c <= '0';
s_reset_bytes_c <= '1';
s_load_var <= '0';
s_counter_top <= s_silence_time;
consume_byte_p_o <= '0';
s_start_produce_p <= '0';
s_last_byte_p <= '0';
s_reset_id_dat <= '0';
s_byte_ready_p <= '0';
add_offset_o <= (others => '0');
s_last_byte_p <= '0';
s_reset_id_dat <= '0';
s_byte_ready_p <= '0';
add_offset_o <= (others => '0');
when id_dat_control_byte =>
s_load_temp_var <= '0';
s_counter_reset <= '1';
s_inc_bytes_c <= '0';
s_reset_bytes_c <= '1';
s_load_var <= '0';
s_counter_top <= s_silence_time;
consume_byte_p_o <= '0';
s_load_temp_var <= '0';
s_counter_reset <= '1';
s_inc_bytes_c <= '0';
s_reset_bytes_c <= '1';
s_load_var <= '0';
s_counter_top <= s_silence_time;
consume_byte_p_o <= '0';
s_start_produce_p <= '0';
s_last_byte_p <= '0';
s_reset_id_dat <= '0';
s_byte_ready_p <= '0';
add_offset_o <= (others => '0');
s_last_byte_p <= '0';
s_reset_id_dat <= '0';
s_byte_ready_p <= '0';
add_offset_o <= (others => '0');
when id_dat_var_byte =>
s_load_temp_var <= byte_ready_p_i;
s_counter_reset <= '1';
s_inc_bytes_c <= '0';
s_reset_bytes_c <= '1';
s_load_var <= '0';
s_counter_top <= s_silence_time;
consume_byte_p_o <= '0';
s_load_temp_var <= byte_ready_p_i;
s_counter_reset <= '1';
s_inc_bytes_c <= '0';
s_reset_bytes_c <= '1';
s_load_var <= '0';
s_counter_top <= s_silence_time;
consume_byte_p_o <= '0';
s_start_produce_p <= '0';
s_last_byte_p <= '0';
s_reset_id_dat <= '0';
s_byte_ready_p <= '0';
add_offset_o <= (others => '0');
s_last_byte_p <= '0';
s_reset_id_dat <= '0';
s_byte_ready_p <= '0';
add_offset_o <= (others => '0');
when id_dat_subs_byte =>
s_load_temp_var <= '0';
s_counter_reset <= '1';
s_inc_bytes_c <= '0';
s_reset_bytes_c <= '1';
s_load_var <= '0';
s_counter_top <= s_silence_time;
consume_byte_p_o <= '0';
s_load_temp_var <= '0';
s_counter_reset <= '1';
s_inc_bytes_c <= '0';
s_reset_bytes_c <= '1';
s_load_var <= '0';
s_counter_top <= s_silence_time;
consume_byte_p_o <= '0';
s_start_produce_p <= '0';
s_last_byte_p <= '0';
s_reset_id_dat <= '0';
s_byte_ready_p <= '0';
add_offset_o <= (others => '0');
s_last_byte_p <= '0';
s_reset_id_dat <= '0';
s_byte_ready_p <= '0';
add_offset_o <= (others => '0');
......@@ -336,76 +336,76 @@ begin
s_load_var <= '0';
if s_produce_or_consume = "10" then
s_counter_top <= s_response_time;
s_counter_top <= s_response_time;
else
s_counter_top <= s_silence_time;
s_counter_top <= s_silence_time;
end if;
s_counter_reset <= '1';
s_inc_bytes_c <= '0';
s_reset_bytes_c <= '1';
consume_byte_p_o <= '0';
s_counter_reset <= '1';
s_inc_bytes_c <= '0';
s_reset_bytes_c <= '1';
consume_byte_p_o <= '0';
s_start_produce_p <= '0';
s_last_byte_p <= '0';
s_reset_id_dat <= '0';
s_byte_ready_p <= '0';
s_load_temp_var <= '0';
add_offset_o <= (others => '0');
s_last_byte_p <= '0';
s_reset_id_dat <= '0';
s_byte_ready_p <= '0';
s_load_temp_var <= '0';
add_offset_o <= (others => '0');
when produce_wait_respon_time =>
s_start_produce_p <= s_respon_silen_c_is_zero;
s_counter_reset <= '0';
s_inc_bytes_c <= '0';
s_reset_bytes_c <= '1';
s_load_var <= '1';
s_counter_top <= s_silence_time;
consume_byte_p_o <= '0';
s_load_temp_var <= '0';
s_last_byte_p <= '0';
s_reset_id_dat <= '0';
s_byte_ready_p <= '0';
add_offset_o <= (others => '0');
s_counter_reset <= '0';
s_inc_bytes_c <= '0';
s_reset_bytes_c <= '1';
s_load_var <= '1';
s_counter_top <= s_silence_time;
consume_byte_p_o <= '0';
s_load_temp_var <= '0';
s_last_byte_p <= '0';
s_reset_id_dat <= '0';
s_byte_ready_p <= '0';
add_offset_o <= (others => '0');
when consume =>
--if unsigned(s_bytes_c) > 1 then -- 1st byte: control; not to be consumed--should be >0???
consume_byte_p_o <= byte_ready_p_i;
consume_byte_p_o <= byte_ready_p_i;
--else
-- consume_byte_p_o <= '0';
--end if;
s_reset_id_dat <= frame_ok_p_i or s_respon_silen_c_is_zero;
add_offset_o <= std_logic_vector(resize(s_bytes_c,add_offset_o'length));
s_inc_bytes_c <= byte_ready_p_i;
s_reset_id_dat <= frame_ok_p_i or s_respon_silen_c_is_zero;
add_offset_o <= std_logic_vector(resize(s_bytes_c,add_offset_o'length));
s_inc_bytes_c <= byte_ready_p_i;
s_reset_bytes_c <= '0';
s_counter_reset <= '0';
s_load_var <= '1';
s_counter_top <= s_silence_time;
s_reset_bytes_c <= '0';
s_counter_reset <= '0';
s_load_var <= '1';
s_counter_top <= s_silence_time;
s_start_produce_p <= '0';
s_last_byte_p <= '0';
s_load_temp_var <= '0';
s_byte_ready_p <= '0';
s_last_byte_p <= '0';
s_load_temp_var <= '0';
s_byte_ready_p <= '0';
when produce =>
s_last_byte_p <= s_data_length_match and request_byte_p_i;
s_byte_ready_p <= request_byte_p_i or s_start_produce_p_d1;
s_inc_bytes_c <= request_byte_p_i;
s_reset_id_dat <= s_data_length_match and request_byte_p_i;
add_offset_o <= std_logic_vector(resize(s_bytes_c, add_offset_o'length));
s_counter_reset <= '0';
s_reset_bytes_c <= '0';
s_last_byte_p <= s_data_length_match and request_byte_p_i;
s_byte_ready_p <= request_byte_p_i or s_start_produce_p_d1;
s_inc_bytes_c <= request_byte_p_i;
s_reset_id_dat <= s_data_length_match and request_byte_p_i;
add_offset_o <= std_logic_vector(resize(s_bytes_c, add_offset_o'length));
s_counter_reset <= '0';
s_reset_bytes_c <= '0';
s_start_produce_p <= '0';
s_load_var <= '0';
s_counter_top <= s_silence_time;
consume_byte_p_o <= '0';
s_load_temp_var <= '0';
s_load_var <= '0';
s_counter_top <= s_silence_time;
consume_byte_p_o <= '0';
s_load_temp_var <= '0';
when others =>
......@@ -543,10 +543,10 @@ begin
if slone_i = '1' then
if nostat_i = '1' then
s_data_length <= "0000011"; -- 4 bytes (counting starts from 0)
s_data_length <= "00000011"; -- 4 bytes (counting starts from 0)
else
s_data_length <= "0000100"; -- 5 bytes (counting starts from 0)
s_data_length <= "00000100"; -- 5 bytes (counting starts from 0)
end if;
......
wf_package.vhd
View file @ 4303602e
......@@ -53,7 +53,7 @@ package wf_package is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--constants concerning the MPS status bits
constant c_REFRESHMENT_INDEX : integer := 0;
constant c_REFRESHMENT_INDEX : integer := 0;
constant c_SIGNIFICANCE_INDEX : integer := 2;
......@@ -91,16 +91,16 @@ package wf_package is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- construction of a table for the P3_LGTH[2:0] settings
type t_unsigned_array is array (natural range <>) of unsigned(6 downto 0);
type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0);
constant c_P3_LGTH_TABLE : t_unsigned_array(0 to 7) :=
(0 => "0000010", -- 2 bytes
1 => "0001000", -- 8 bytes
2 => "0010000", -- 16 bytes
3 => "0100000", -- 32 bytes
4 => "1000000", -- 64 bytes
5 => "1111100", -- 124 bytes
others => "0000000" -- reserved
(0 => "00000010", -- 2 bytes
1 => "00001000", -- 8 bytes
2 => "00010000", -- 16 bytes
3 => "00100000", -- 32 bytes
4 => "01000000", -- 64 bytes
5 => "01111100", -- 124 bytes
others => "00000000" -- reserved
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -136,9 +136,9 @@ package wf_package is
constant c_VAR_2_INDEX : integer := 4;
constant c_RESET_VAR_INDEX : integer := 5;
constant c_2nd_byte_addr : std_logic_vector(6 downto 0) := "0000010";
constant c_1st_byte_addr : std_logic_vector(6 downto 0) := "0000001";
constant c_CTRL_BYTE_INDEX : std_logic_vector(6 downto 0) := "0000000";
constant c_2nd_BYTE_INDEX : std_logic_vector(7 downto 0) := "00000010";
constant c_1st_BYTE_INDEX : std_logic_vector(7 downto 0) := "00000001";
constant c_CTRL_BYTE_INDEX : std_logic_vector(7 downto 0) := "00000000";
......@@ -316,13 +316,13 @@ package wf_package is
wb_rst_i : in std_logic;
wb_clk_i : in std_logic;
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_p_i : in std_logic;
wb_stb_r_edge_p_i : in std_logic;
wb_cyc_i : in std_logic;
byte_ready_p_i : in std_logic;
index_offset_i : in std_logic_vector(6 downto 0);
index_offset_i : in std_logic_vector(7 downto 0);
var_i : in t_var;
byte_i : in std_logic_vector(7 downto 0);
wb_data_o : out std_logic_vector (15 downto 0);
data_o : out std_logic_vector (15 downto 0);
wb_ack_cons_p_o : out std_logic;
reset_nFIP_and_FD_o : out std_logic;
reset_RSTON_o : out std_logic
......@@ -334,7 +334,6 @@ package wf_package is
component wf_produced_vars is
port (
uclk_i : in std_logic;
nFIP_rst_i : in std_logic;
slone_i : in std_logic;
nostat_i : in std_logic;
m_id_dec_i : in std_logic_vector (7 downto 0);
......@@ -343,14 +342,14 @@ package wf_package is
wb_clk_i : in std_logic;
data_i : in std_logic_vector (15 downto 0);
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_p_i : in std_logic;
wb_stb_r_edge_p_i : in std_logic;
wb_we_p_i : in std_logic;
wb_cyc_i : in std_logic;
nFIP_status_byte_i : in std_logic_vector(7 downto 0);
mps_byte_i : in std_logic_vector(7 downto 0);
var_i : in t_var;
data_length_i : in std_logic_vector(6 downto 0);
index_offset_i : in std_logic_vector(6 downto 0);
data_length_i : in std_logic_vector(7 downto 0);
index_offset_i : in std_logic_vector(7 downto 0);
sending_mps_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0);
......@@ -385,8 +384,8 @@ package wf_package is
var3_rdy_o: out std_logic;
var_o : out t_var;
consume_byte_p_o : out std_logic;
add_offset_o : out std_logic_vector(6 downto 0);
data_length_o : out std_logic_vector(6 downto 0)
add_offset_o : out std_logic_vector(7 downto 0);
data_length_o : out std_logic_vector(7 downto 0)
);
end component wf_engine_control;
......@@ -472,7 +471,8 @@ package wf_package is
fd_txer_i : in std_logic;
var1_access_a_i : in std_logic;
var2_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
var3_access_a_i : in std_logic;
var_i : in t_var;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
......
wf_produced_vars.vhd
View file @ 4303602e
......@@ -50,7 +50,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! \n\n<b>Last changes:</b>\n
--! -> egousiou: subs_i is not sent in the rp_dat frames \n
--! -> egousiou: pdu_type & length bytes not sent in slone \n
--! -> egousiou: signal s_wb_we includes the wb_stb_p_i \n
--! -> egousiou: signal s_wb_we includes the wb_stb_r_edge_p_i \n
--! -> egousiou: signal s_mem_byte was not in sensitivity list (pablo's varsion)! by adding it,
--! changes were essential in the timing of the tx (wf_osc, wf_tx, wf_engine_control
--! and the configuration of the memory needed few changes)
......@@ -73,7 +73,6 @@ entity wf_produced_vars is
-- INPUTS
-- User Interface general signals
uclk_i : in std_logic; --! 40MHz clock
nFIP_rst_i : in std_logic; --! internal reset
slone_i : in std_logic; --! stand-alone mode
nostat_i : in std_logic; --! if negated, nFIP status is sent
......@@ -93,7 +92,7 @@ entity wf_produced_vars is
-- (buffered once with wb_clk)
-- note: msb allways 0!
wb_stb_p_i : in std_logic; --! wishbone strobe
wb_stb_r_edge_p_i : in std_logic; --! wishbone strobe
-- (buffered once with wb_clk)
-- note: indication that the
-- master is ready to transfer data
......@@ -107,7 +106,7 @@ entity wf_produced_vars is
-- Signals from wf_engine_control
var_i : in t_var; --! variable received from id_dat
data_length_i: in std_logic_vector(6 downto 0); --! # bytes of Conrol&Data fields of rp_dat
data_length_i: in std_logic_vector(7 downto 0); --! # bytes of Conrol&Data fields of rp_dat
-- includes 1 byte for the rp_dat.Control,
-- 1 byte for rp_dat.Data.PDU_type,
-- 1 byte for rp_dat.Data.LENGTH
......@@ -116,7 +115,7 @@ entity wf_produced_vars is
-- 1 byte for rp_dat.Data.nanoFIP_status
index_offset_i : in std_logic_vector(6 downto 0); --! pointer to message bytes
index_offset_i : in std_logic_vector(7 downto 0); --! pointer to message bytes
-- including rp_dat.Control and rp_dat.Data
-- Signals from status_gen
......@@ -151,10 +150,10 @@ architecture rtl of wf_produced_vars is
signal s_length, s_mem_byte, s_io_byte : std_logic_vector(7 downto 0);
signal s_mem_addr_A : std_logic_vector(8 downto 0);
signal s_index_offset_d1 : std_logic_vector(6 downto 0);
signal s_index_offset_d1 : std_logic_vector(7 downto 0);
signal s_byte_index_aux : integer range 0 to 15;
signal s_base_addr, s_mem_addr_offset : unsigned(8 downto 0);
signal s_wb_ack_prod_p, wb_ack_prod_p_o_d : std_logic;
signal s_wb_ack_prod_p : std_logic;
signal s_byte_index : integer;
......@@ -197,32 +196,20 @@ architecture rtl of wf_produced_vars is
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Generate_wb_ack_prod_p_o: Generation of the wb_ack_prod_p_o signal
--!@brief Generate_wb_ack_prod_p_o: Generation of the wb_ack_prod_p_o signal
--! (acknowledgement from wishbone slave of the write cycle, as a response to the master's storbe).
--! wb_ack_prod_p_o is asserted two wb_clk cycles after the assertion of the input strobe signal
--! (reminder: stb_i is buffered once in the input stage), if the wishbone input address
--! corresponds to the Produced memory block and the wishbone write enable is asserted.
Generate_wb_ack_prod_p_o: process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
wb_ack_prod_p_o_d <='0';
else
wb_ack_prod_p_o_d <= s_wb_ack_prod_p; -- slave's indication: write cycle identified
-- & slave ready to latch data
end if;
end if;
end process;
Generate_wb_ack_prod_p_o: s_wb_ack_prod_p <= '1' when ((wb_stb_r_edge_p_i = '1') and
(wb_adr_i(9 downto 7) = "010") and
(wb_we_p_i = '1') and
(wb_cyc_i = '1'))
else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_wb_ack_prod_p <= '1' when (wb_stb_p_i = '1' and wb_we_p_i = '1' and
wb_adr_i(9 downto 7) = "010" and wb_cyc_i = '1')
else '0';
wb_ack_prod_p_o <= s_wb_ack_prod_p;
---------------------------------------------------------------------------------------------------
--!@brief synchronous process Delay_index_offset_i: in the combinatorial process that follows
--! (Bytes_Generation), according to the value of the signal s_byte_index, a byte is retreived
......@@ -250,11 +237,12 @@ architecture rtl of wf_produced_vars is
--! The output byte "byte_o" is sent to the transmitter(wf_tx)for serialization
Bytes_Generation: process (var_i, s_index_offset_d1, s_byte_index, data_length_i, c_id_dec_i,
m_id_dec_i,nFIP_status_byte_i, mps_byte_i, s_io_byte, s_mem_byte)
m_id_dec_i,nFIP_status_byte_i, mps_byte_i, s_io_byte, s_mem_byte,
slone_i, s_byte_index_aux, nostat_i)
begin
s_byte_index <= to_integer(unsigned(s_index_offset_d1));
s_byte_index <= to_integer(unsigned(s_index_offset_d1));
-- index of byte to be sent
s_byte_index_aux <= (to_integer(unsigned(s_index_offset_d1(3 downto 0))));
......@@ -263,7 +251,7 @@ architecture rtl of wf_produced_vars is
-- c_VARS_ARRAY.byte_array, with a predefined
-- width of 15 bytes
s_length <= std_logic_vector(resize((unsigned(data_length_i)-2),byte_o'length));
s_length <= std_logic_vector(resize((unsigned(data_length_i)-2),byte_o'length));
--signal used for the rp_dat.Data.LENGTH byte
-- it represents the # bytes of "pure data"
-- (P3_LGTH) plus 1 byte of rp_dat.Data.MPS
......@@ -282,10 +270,10 @@ architecture rtl of wf_produced_vars is
-- are predefined in the c_VARS_ARRAY(0).byte_array matrix
when presence_var =>
byte_o <= c_VARS_ARRAY(c_PRESENCE_VAR_INDEX).byte_array(s_byte_index_aux);
byte_o <= c_VARS_ARRAY(c_PRESENCE_VAR_INDEX).byte_array(s_byte_index_aux);
s_base_addr <= (others => '0');
sending_mps_o <= '0';
s_base_addr <= (others => '0');
sending_mps_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -297,17 +285,17 @@ architecture rtl of wf_produced_vars is
when identif_var =>
if s_byte_index = c_CONSTR_BYTE_INDEX then
byte_o <= c_id_dec_i;
byte_o <= c_id_dec_i;
elsif s_byte_index = c_MODEL_BYTE_INDEX then
byte_o <= m_id_dec_i;
byte_o <= m_id_dec_i;
else
byte_o <= c_VARS_ARRAY(c_IDENTIF_VAR_INDEX).byte_array(s_byte_index_aux);
byte_o <= c_VARS_ARRAY(c_IDENTIF_VAR_INDEX).byte_array(s_byte_index_aux);
end if;
s_base_addr <= (others => '0');
sending_mps_o <= '0';
s_base_addr <= (others => '0');
sending_mps_o <= '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -323,13 +311,13 @@ architecture rtl of wf_produced_vars is
-- In memory mode:
if slone_i = '0' then
s_base_addr <= c_VARS_ARRAY(c_VAR_3_INDEX).base_add; --retreival of info for mem base address
s_base_addr <= c_VARS_ARRAY(c_VAR_3_INDEX).base_add; --retreival of info for mem base address
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first (rp_dat.Control) and second (PDU type) bytes to be sent
-- are predefined in the c_VARS_ARRAY matrix of the wf_package
if s_byte_index <= c_VARS_ARRAY(c_VAR_3_INDEX).array_length then
if s_byte_index <= c_VARS_ARRAY(c_VAR_3_INDEX).array_length then -- less than or equal to
byte_o <= c_VARS_ARRAY(c_VAR_3_INDEX).byte_array(s_byte_index_aux);
sending_mps_o <= '0';
......@@ -366,7 +354,7 @@ architecture rtl of wf_produced_vars is
-- In standalone mode:
else
s_base_addr <= (others => '0'); -- no access in memory needed
s_base_addr <= (others => '0'); -- no access in memory needed
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The first byte to be sent is the rp_dat.Control, which is
......@@ -402,9 +390,9 @@ architecture rtl of wf_produced_vars is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
sending_mps_o <= '0';
byte_o <= (others => '0');
s_base_addr <= (others => '0');
sending_mps_o <= '0';
byte_o <= (others => '0');
s_base_addr <= (others => '0');
end case;
end process;
......
wf_rx.vhd
View file @ 4303602e
......@@ -139,7 +139,7 @@ architecture rtl of wf_rx is
signal s_frame_start_wrong_bit, s_frame_start_last_bit : std_logic;
signal s_frame_end_detected_p, s_frame_end_detection, s_frame_end_wrong_bit : std_logic;
signal s_violation_check, s_code_violation : std_logic;
signal s_violation_check, s_code_violation_p : std_logic;
signal s_calculate_crc, s_crc_ok_p, s_crc_ok, s_start_crc_p : std_logic;
signal s_byte_ok, s_write_bit_to_byte, s_rx_data_filtered_d: std_logic;
......@@ -204,7 +204,7 @@ architecture rtl of wf_rx is
s_frame_start_wrong_bit, s_manch_f_edge, rx_st,
s_frame_end_detected_p, s_frame_end_wrong_bit,
rx_data_f_edge_i, s_edge_outside_manch_window,
s_code_violation,s_bit_r_edge, s_manch_r_edge )
s_code_violation_p,s_bit_r_edge, s_manch_r_edge )
begin
nx_rx_st <= idle;
......@@ -224,34 +224,34 @@ architecture rtl of wf_rx is
when preamble_field_first_fe=>
if s_manch_r_edge = '1' then -- arrival of a manchester rising edge
nx_rx_st <= preamble_field_re; -- jump to preamble rising edge state
nx_rx_st <= preamble_field_re; -- jump to preamble rising edge state
elsif s_edge_outside_manch_window = '1' then -- arrival of any other edge,
nx_rx_st <= idle; -- jump back to the beginning
nx_rx_st <= idle; -- jump back to the beginning
else
nx_rx_st <= preamble_field_first_fe;
nx_rx_st <= preamble_field_first_fe;
end if;
when preamble_field_re =>
if s_manch_f_edge = '1' then -- arrival of a manchester falling edge
if s_manch_f_edge = '1' then -- arrival of a manchester falling edge
nx_rx_st <= preamble_field_fe; -- jump to preamble falling edge state
-- note: 4 loops between a rising and a
-- falling edge are expected for the preamble
elsif s_edge_outside_manch_window = '1' then -- arrival of any other edge
nx_rx_st <= idle; -- jump back to the beginning
else
nx_rx_st <= preamble_field_re;
elsif s_edge_outside_manch_window = '1' then -- arrival of any other edge
nx_rx_st <= idle; -- jump back to the beginning
else
nx_rx_st <= preamble_field_re;
end if;
when preamble_field_fe =>
if s_manch_r_edge = '1' then -- arrival of a manchester rising edge
nx_rx_st <= preamble_field_re; -- jump to preamble falling edge
elsif s_bit_r_edge = '1' then -- arrival of a bit rising edge
if s_manch_r_edge = '1' then -- arrival of a manchester rising edge
nx_rx_st <= preamble_field_re; -- jump to preamble falling edge
elsif s_bit_r_edge = '1' then -- arrival of a bit rising edge
nx_rx_st <= switch_to_deglitched; -- signaling the beginning of the
-- first V+ violation
elsif s_edge_outside_manch_window = '1' then -- arrival of any other edge
nx_rx_st <= idle; -- jump back to the beginning
else
nx_rx_st <= preamble_field_fe;
elsif s_edge_outside_manch_window = '1' then -- arrival of any other edge
nx_rx_st <= idle; -- jump back to the beginning
else
nx_rx_st <= preamble_field_fe;
end if;
-- A small delay is expected between the rx_data_i and the rx_data_filtered_i (output of the
......@@ -260,11 +260,11 @@ architecture rtl of wf_rx is
-- this purpose.
when switch_to_deglitched =>
if s_rx_data_filtered_f_edge = '1' then
nx_rx_st <= frame_start_field;
else
nx_rx_st <= switch_to_deglitched;
end if;
if s_rx_data_filtered_f_edge = '1' then
nx_rx_st <= frame_start_field;
else
nx_rx_st <= switch_to_deglitched;
end if;
-- For the monitoring of the frame start delimiter, the unit is sampling each manchester bit of
-- the incoming d_filtered signal and it is comparing it to the nominal bit of the frame start
......@@ -272,28 +272,28 @@ architecture rtl of wf_rx is
-- the complete byte is correctly received, it jumps to the data_field_byte state.
when frame_start_field =>
if s_frame_start_last_bit = '1' then-- reception of the last (15th) bit of
nx_rx_st <= data_field_byte; -- the fss, jump to data_field_byte state
if s_frame_start_last_bit = '1' then-- reception of the last (15th) bit of
nx_rx_st <= data_field_byte; -- the fss, jump to data_field_byte state
elsif s_frame_start_wrong_bit = '1' then -- wrong frame start bit
nx_rx_st <= idle; -- jump back to the beginning
elsif s_frame_start_wrong_bit = '1' then -- wrong frame start bit
nx_rx_st <= idle; -- jump back to the beginning
else
nx_rx_st <= frame_start_field;
end if;
else
nx_rx_st <= frame_start_field;
end if;
when data_field_byte =>
if s_frame_end_detected_p = '1' then
nx_rx_st <= idle;
if s_frame_end_detected_p = '1' then
nx_rx_st <= idle;
-- Is there a code violation that does not correspond to the queue pattern?
elsif s_frame_end_wrong_bit = '1' and s_code_violation = '1' then
nx_rx_st <= idle;
else
nx_rx_st <= data_field_byte;
end if;
elsif s_frame_end_wrong_bit = '1' and s_code_violation_p = '1' then
nx_rx_st <= idle;
else
nx_rx_st <= data_field_byte;
end if;
when others =>
nx_rx_st <= idle;
nx_rx_st <= idle;
end case;
end process;
......@@ -303,7 +303,7 @@ architecture rtl of wf_rx is
Receiver_FSM_Comb_Output_Signals: process (rx_st, pointer,sample_manch_bit_p_i,s_pointer_is_zero,
s_frame_start_last_bit, s_frame_end_detected_p,
s_code_violation,s_frame_end_wrong_bit,sample_bit_p_i)
s_code_violation_p,s_frame_end_wrong_bit,sample_bit_p_i)
begin
......@@ -313,115 +313,112 @@ architecture rtl of wf_rx is
-- initializations:
wait_d_first_f_edge_o <= '1'; -- signal for rx_osc
s_start_pointer <= to_unsigned(0,s_start_pointer'length);
s_load_pointer <= '0';
s_decr_pointer <= '0';
s_frame_start_bit <='0';
fss_decoded_p_o <= '0';
s_start_pointer <= to_unsigned(0,s_start_pointer'length);
s_load_pointer <= '0';
s_decr_pointer <= '0';
s_frame_start_bit <='0';
fss_decoded_p_o <= '0';
s_write_bit_to_byte <= '0';
s_byte_ok <= '0';
s_start_crc_p <= '0';
s_calculate_crc <= '0';
code_violation_p_o <= '0';
s_queue_bit <= '0';
s_byte_ok <= '0';
s_start_crc_p <= '0';
s_calculate_crc <= '0';
code_violation_p_o <= '0';
s_queue_bit <= '0';
when preamble_field_first_fe =>
wait_d_first_f_edge_o <= '0';
s_start_pointer <= to_unsigned(0,s_start_pointer'length);
s_load_pointer <= '0';
s_decr_pointer <= '0';
s_frame_start_bit <='0';
fss_decoded_p_o <= '0';
s_start_pointer <= to_unsigned(0,s_start_pointer'length);
s_load_pointer <= '0';
s_decr_pointer <= '0';
s_frame_start_bit <='0';
fss_decoded_p_o <= '0';
s_write_bit_to_byte <= '0';
s_byte_ok <= '0';
s_start_crc_p <= '0';
s_calculate_crc <= '0';
code_violation_p_o <= '0';
s_queue_bit <= '0';
s_byte_ok <= '0';
s_start_crc_p <= '0';
s_calculate_crc <= '0';
code_violation_p_o <= '0';
s_queue_bit <= '0';
when preamble_field_re =>
wait_d_first_f_edge_o <= '0';
s_start_pointer <= to_unsigned(0,s_start_pointer'length);
s_load_pointer <= '0';
s_decr_pointer <= '0';
s_frame_start_bit <='0';
fss_decoded_p_o <= '0';
s_write_bit_to_byte <= '0';
s_byte_ok <= '0';
s_start_crc_p <= '0';
s_calculate_crc <= '0';
code_violation_p_o <= '0';
s_queue_bit <= '0';
s_start_pointer <= to_unsigned(0,s_start_pointer'length);
s_load_pointer <= '0';
s_decr_pointer <= '0';
s_frame_start_bit <='0';
fss_decoded_p_o <= '0';
s_write_bit_to_byte <= '0';
s_byte_ok <= '0';
s_start_crc_p <= '0';
s_calculate_crc <= '0';
code_violation_p_o <= '0';
s_queue_bit <= '0';
when preamble_field_fe =>
wait_d_first_f_edge_o <= '0';
s_start_pointer <= to_unsigned(0,s_start_pointer'length);
s_load_pointer <= '0';
s_decr_pointer <= '0';
s_frame_start_bit <='0';
fss_decoded_p_o <= '0';
s_write_bit_to_byte <= '0';
s_byte_ok <= '0';
s_start_crc_p <= '0';
s_calculate_crc <= '0';
code_violation_p_o <= '0';
s_queue_bit <= '0';
s_start_pointer <= to_unsigned(0,s_start_pointer'length);
s_load_pointer <= '0';
s_decr_pointer <= '0';
s_frame_start_bit <='0';
fss_decoded_p_o <= '0';
s_write_bit_to_byte <= '0';
s_byte_ok <= '0';
s_start_crc_p <= '0';
s_calculate_crc <= '0';
code_violation_p_o <= '0';
s_queue_bit <= '0';
when switch_to_deglitched =>
s_load_pointer <= '1';
s_frame_start_bit <= FRAME_START(to_integer(pointer));
s_start_pointer <= to_unsigned(FRAME_START'left-1,s_start_pointer'length);
s_load_pointer <= '1';
s_frame_start_bit <= FRAME_START(to_integer(pointer));
s_start_pointer <= to_unsigned(FRAME_START'left-1,s_start_pointer'length);
wait_d_first_f_edge_o <= '0';
s_decr_pointer <= '0';
fss_decoded_p_o <= '0';
s_write_bit_to_byte <= '0';
s_byte_ok <= '0';
s_start_crc_p <= '0';
s_calculate_crc <= '0';
code_violation_p_o <= '0';
s_queue_bit <= '0';
s_decr_pointer <= '0';
fss_decoded_p_o <= '0';
s_write_bit_to_byte <= '0';
s_byte_ok <= '0';
s_start_crc_p <= '0';
s_calculate_crc <= '0';
code_violation_p_o <= '0';
s_queue_bit <= '0';
when frame_start_field =>
s_load_pointer <= s_pointer_is_zero and sample_manch_bit_p_i;
s_frame_start_bit <= FRAME_START(to_integer(pointer));
s_start_pointer <= to_unsigned(FRAME_END'left,s_start_pointer'length);
s_decr_pointer <= sample_manch_bit_p_i;
fss_decoded_p_o <= s_frame_start_last_bit;
s_start_crc_p <= '1';
s_calculate_crc <= '1';
--code_violation_p_o <= s_frame_end_wrong_bit and s_code_violation;
s_queue_bit <= '0';
s_load_pointer <= s_pointer_is_zero and sample_manch_bit_p_i;
s_frame_start_bit <= FRAME_START(to_integer(pointer));
s_start_pointer <= to_unsigned(FRAME_END'left,s_start_pointer'length);
s_decr_pointer <= sample_manch_bit_p_i;
fss_decoded_p_o <= s_frame_start_last_bit;
s_start_crc_p <= '1';
s_calculate_crc <= '1';
code_violation_p_o <= '0';
s_queue_bit <= '0';
wait_d_first_f_edge_o <= '0';
s_write_bit_to_byte <= '0';
s_byte_ok <= '0';
s_write_bit_to_byte <= '0';
s_byte_ok <= '0';
when data_field_byte =>
s_load_pointer <= s_pointer_is_zero and sample_manch_bit_p_i;
s_start_pointer <= to_unsigned(FRAME_END'left,s_start_pointer'length);
s_decr_pointer <= sample_manch_bit_p_i;
s_write_bit_to_byte <= sample_bit_p_i;
s_byte_ok <= s_pointer_is_zero and sample_manch_bit_p_i and
((not s_frame_end_detected_p) and (not s_code_violation));
s_queue_bit <= FRAME_END(to_integer(resize(pointer,4)));
code_violation_p_o <= '0';
s_start_crc_p <= '0';
s_calculate_crc <= '1';
s_frame_start_bit <= '0';
s_load_pointer <= s_pointer_is_zero and sample_manch_bit_p_i;
s_start_pointer <= to_unsigned(FRAME_END'left,s_start_pointer'length);
s_decr_pointer <= sample_manch_bit_p_i;
s_write_bit_to_byte <= sample_bit_p_i;
s_byte_ok <= s_pointer_is_zero and sample_manch_bit_p_i and
(not s_frame_end_detected_p);
s_queue_bit <= FRAME_END(to_integer(resize(pointer,4)));
code_violation_p_o <= s_code_violation_p;
s_start_crc_p <= '0';
s_calculate_crc <= '1';
s_frame_start_bit <= '0';
wait_d_first_f_edge_o <= '0';
fss_decoded_p_o <= '0';
fss_decoded_p_o <= '0';
when others =>
......@@ -431,27 +428,27 @@ architecture rtl of wf_rx is
---------------------------------------------------------------------------------------------------
-- concurrent signal assignments concerning edges detection for the preamble field
s_manch_r_edge <= signif_edge_window_i and rx_data_r_edge_i;
s_manch_f_edge <= signif_edge_window_i and rx_data_f_edge_i;
s_bit_r_edge <= adjac_bits_window_i and ( rx_data_r_edge_i);
s_edge_outside_manch_window <= (not signif_edge_window_i)and (rx_data_r_edge_i or rx_data_f_edge_i);
s_manch_r_edge <= signif_edge_window_i and rx_data_r_edge_i;
s_manch_f_edge <= signif_edge_window_i and rx_data_f_edge_i;
s_bit_r_edge <= adjac_bits_window_i and ( rx_data_r_edge_i);
s_edge_outside_manch_window <= (not signif_edge_window_i)and(rx_data_r_edge_i or rx_data_f_edge_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- concurrent signal assignments concerning the frame start field (used in frame_start_field state)
s_frame_start_wrong_bit <= (s_frame_start_bit xor rx_data_filtered_i) and sample_bit_p_i;
s_frame_start_last_bit <= s_pointer_is_zero and sample_manch_bit_p_i;
s_frame_start_last_bit <= s_pointer_is_zero and sample_manch_bit_p_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- concurrent signal assignments concerning the frame end field (used in data_field_byte state)
s_frame_end_wrong_bit <= (s_queue_bit xor rx_data_filtered_i) and sample_bit_p_i;
s_frame_end_wrong_bit <= (s_queue_bit xor rx_data_filtered_i) and sample_bit_p_i;
s_frame_end_detected_p <= s_frame_end_detection and sample_manch_bit_p_i and s_pointer_is_zero;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- extra concurrent signal assignments
s_code_violation <= (not (rx_data_filtered_i xor s_rx_data_filtered_d)) and s_violation_check;
s_code_violation_p <= (not (rx_data_filtered_i xor s_rx_data_filtered_d)) and s_violation_check;
s_pointer_is_zero <= '1' when pointer = 0 else '0';
-- s_frame_start_last_bit <= s_pointer_is_zero and s_frame_start_correct_bit and sample_manch_bit_p_i;
......@@ -467,9 +464,13 @@ architecture rtl of wf_rx is
s_frame_end_detection <= '1';
elsif s_pointer_is_zero = '1' and sample_manch_bit_p_i = '1' then
s_frame_end_detection <= '1';
elsif s_frame_end_wrong_bit = '1' then
s_frame_end_detection <= '0';
s_frame_end_detection <= '0';
end if;
end if;
end process;
......@@ -482,13 +483,15 @@ architecture rtl of wf_rx is
begin
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then
pointer <= (others => '0');
pointer <= (others => '0');
else
if s_load_pointer = '1' then
pointer <= s_start_pointer;
elsif s_decr_pointer = '1' then
pointer <= pointer - 1;
end if;
end if;
end if;
......@@ -523,8 +526,9 @@ architecture rtl of wf_rx is
if s_calculate_crc='0' then
s_crc_ok <= '0';
elsif s_crc_ok_p = '1' and s_calculate_crc='1' then
s_crc_ok <= '1';
s_crc_ok <= '1';
end if;
end if;
end if;
......@@ -567,29 +571,29 @@ end process;
begin
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then
byte_ready_p_o <= '0';
s_violation_check <='0';
s_sample_bit_p_d1 <= '0';
s_sample_bit_p_d2 <= '0';
s_rx_data_filtered_d <='0';
byte_ready_p_o <='0';
s_violation_check <='0';
s_sample_bit_p_d1 <='0';
s_sample_bit_p_d2 <='0';
s_rx_data_filtered_d <='0';
else
if sample_manch_bit_p_i = '1' then
s_rx_data_filtered_d <= rx_data_filtered_i;
end if;
s_violation_check <= s_sample_bit_p_d2;
s_sample_bit_p_d2 <= s_sample_bit_p_d1;
s_sample_bit_p_d1 <= sample_bit_p_i;
byte_ready_p_o <= s_byte_ok and (not s_frame_end_detected_p);
s_violation_check <= s_sample_bit_p_d2;
s_sample_bit_p_d2 <= s_sample_bit_p_d1;
s_sample_bit_p_d1 <= sample_bit_p_i;
byte_ready_p_o <= s_byte_ok and (not s_frame_end_detected_p);
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- output signals that have also been used in this unit's processes:
byte_o <= s_byte;
byte_o <= s_byte;
last_byte_p_o <= s_frame_end_detected_p;
crc_ok_p_o <= s_frame_end_detected_p and s_crc_ok;
crc_ok_p_o <= s_frame_end_detected_p and s_crc_ok;
crc_wrong_p_o <= s_frame_end_detected_p and (not s_crc_ok);
......
wf_rx_osc.vhd
View file @ 4303602e
......@@ -168,11 +168,12 @@ architecture rtl of wf_rx_osc is
--=================================================================================================
begin
s_period <= C_UCLK_TICKS(to_integer(unsigned(rate_i))); -- s_period: # uclock ticks for a period
s_half_period <= (s_period srl 1); -- s_period shifted 1 bit
s_one_forth_period <= s_period srl 2; -- s_period shifted 2 bits
s_jitter <= s_period srl 3; -- jitter defined as 1/8 of the period
s_counter_full <= s_period-1;
s_period <= C_UCLK_TICKS(to_integer(unsigned(rate_i))); -- # uclock ticks for a period
s_half_period <= (s_period srl 1); -- s_period shifted 1 bit
s_one_forth_period <= s_period srl 2; -- s_period shifted 2 bits
s_jitter <= s_period srl 3; -- jitter defined as 1/8 of
-- the period
s_counter_full <= s_period-1;
---------------------------------------------------------------------------------------------------
......@@ -191,9 +192,9 @@ begin
begin
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then
s_counter_tx <= (others => '0');
s_counter_rx <= (others => '0');
s_tx_clk_d1 <= '0';
s_counter_tx <= (others => '0');
s_counter_rx <= (others => '0');
s_tx_clk_d1 <= '0';
s_tx_clk_p_buff <= (others => '0');
else
......@@ -201,13 +202,13 @@ begin
-- transmission counter:
-- free counter measuring transmission periods
if (s_counter_tx = s_counter_full) then
s_counter_tx <= (others => '0');
s_counter_tx <= (others => '0');
else
s_counter_tx <= s_counter_tx + 1 ;
s_counter_tx <= s_counter_tx + 1 ;
end if;
-- clk signals:
s_tx_clk_d1 <= s_tx_clk;
s_tx_clk_d1 <= s_tx_clk;
s_tx_clk_p_buff <= s_tx_clk_p_buff (s_tx_clk_p_buff'left -1 downto 0) & s_tx_clk_p; -- buffer
......@@ -216,7 +217,7 @@ begin
-- counter initialized after the first falling edge of rx_data_i
if (wait_d_first_f_edge_i = '1') then
if rx_data_f_edge_i = '1' then -- 1st falling edge of an id_dat received
s_counter_rx <= (others => '0'); -- counter initialized
s_counter_rx <= (others => '0'); -- counter initialized
else
if (s_counter_rx=s_counter_full) then -- measurement of the first period
s_counter_rx <= (others => '0');
......@@ -228,14 +229,14 @@ begin
-- for the rest of the rxd
else
if (s_rx_signif_edge_window = '1') and (d_edge_i ='1') then
s_counter_rx <= (others => '0'); -- when an edge appears inside
s_counter_rx <= (others => '0'); -- when an edge appears inside
-- the expected window, the
-- counter is reinitialized
elsif (s_counter_rx=s_counter_full) then -- otherwise, it continues counting
s_counter_rx <= (others => '0'); -- complete nominal periods
s_counter_rx <= (others => '0'); -- complete nominal periods
else
s_counter_rx <= s_counter_rx + 1 ;
s_counter_rx <= s_counter_rx + 1 ;
end if;
end if;
......@@ -306,11 +307,11 @@ begin
if rising_edge(uclk_i) then
-- initializations:
if (nFIP_rst_i = '1') then
s_rx_manch_clk <='0';
s_rx_bit_clk <= '0';
s_rx_bit_clk_d1 <='0';
s_rx_manch_clk_d1 <='0';
s_signif_edge_found <='0';
s_rx_manch_clk <='0';
s_rx_bit_clk <='0';
s_rx_bit_clk_d1 <='0';
s_rx_manch_clk_d1 <='0';
s_signif_edge_found <='0';
s_adjac_bits_edge_found <='0';
......@@ -318,43 +319,46 @@ begin
-- regarding significant edges:
if (s_rx_signif_edge_window='1') then -- looking for a significant edge
if (d_edge_i='1') then -- inside the corresponding window
s_rx_manch_clk <= not s_rx_manch_clk;
s_signif_edge_found <= '1'; -- indication that the edge was found
s_rx_manch_clk <= not s_rx_manch_clk;
s_signif_edge_found <= '1'; -- indication that the edge was found
s_adjac_bits_edge_found <= '0';
end if;
elsif (s_signif_edge_found='0')and(s_counter_rx=s_jitter) then
s_rx_manch_clk <= not s_rx_manch_clk; --if a significant edge is not found where
s_rx_manch_clk <= not s_rx_manch_clk;
--if a significant edge is not found where
-- expected (code violation), the
-- rx_manch_clk is inverted right after the
-- end of the signif_edge_window
s_adjac_bits_edge_found <= '0'; -- re-initialization before the next cycle
s_adjac_bits_edge_found <= '0'; -- re-initialization before the next cycle
-- regarding edges between adjacent bits:
elsif (s_rx_adjac_bits_window='1') then -- looking for an edge inside
if (d_edge_i='1') then -- the corresponding window
s_rx_manch_clk <= not s_rx_manch_clk;-- inversion of rx_manch_clk
s_rx_bit_clk <= not s_rx_bit_clk; -- inversion of rx_bit_clk
s_adjac_bits_edge_found <= '1'; -- indication that an edge was found
elsif (s_rx_adjac_bits_window='1') then -- looking for an edge inside
if (d_edge_i='1') then -- the corresponding window
s_rx_manch_clk <= not s_rx_manch_clk;-- inversion of rx_manch_clk
s_rx_bit_clk <= not s_rx_bit_clk; -- inversion of rx_bit_clk
s_adjac_bits_edge_found <= '1'; -- indication that an edge was found
s_signif_edge_found <= '0'; -- re-initialization before the next cycle
s_signif_edge_found <= '0'; -- re-initialization before next cycle
end if;
elsif (s_adjac_bits_edge_found='0')and(s_counter_rx=s_half_period+s_jitter) then
s_rx_manch_clk <= not s_rx_manch_clk; -- if no edge occurs inside the
s_rx_bit_clk <= not s_rx_bit_clk; -- adjac_bits_edge_window, both clks are
-- inverted right after the end of it.
s_rx_manch_clk <= not s_rx_manch_clk; -- if no edge occurs inside the
s_rx_bit_clk <= not s_rx_bit_clk; --adjac_bits_edge_window,both clks are
-- inverted right after the end of it
s_signif_edge_found <= '0'; -- re-initialization before the next cycle
s_signif_edge_found <= '0'; -- reinitialization before next cycle
end if;
s_rx_manch_clk_d1 <= s_rx_manch_clk; -- s_rx_manch_clk: ____|-----|_____|-----|____
s_rx_manch_clk_d1 <= s_rx_manch_clk;
-- s_rx_manch_clk: ____|-----|_____|-----|____
-- s_rx_manch_clk_d1: ______|-----|_____|-----|__
-- rx_manch_clk_p_o: ____|-|___|-|___|-|___|-|__
s_rx_bit_clk_d1 <= s_rx_bit_clk; -- s_rx_bit_clk: ____|-----------|___________
s_rx_bit_clk_d1 <= s_rx_bit_clk;
-- s_rx_bit_clk: ____|-----------|___________
-- s_rx_bit_clk_d1: ______|-----------|_________
-- rx_bit_clk_p_o: ____|-|_________|-|_________
......@@ -372,18 +376,18 @@ begin
-- 2) a new bit
-- ___|-|___|-|___|-|___
rx_bit_clk_p_o <= s_rx_bit_clk xor s_rx_bit_clk_d1; -- a pulse 1-uclk period long, after
rx_bit_clk_p_o <= s_rx_bit_clk xor s_rx_bit_clk_d1; -- a pulse 1-uclk period long, after
-- a new bit
-- _________|-|_________
-- clocks needed for the transmitter:
tx_clk_o <= s_tx_clk_d1;
tx_clk_p_buff_o <= s_tx_clk_p_buff;
tx_clk_o <= s_tx_clk_d1;
tx_clk_p_buff_o <= s_tx_clk_p_buff;
-- output signals that have also been used in this unit's processes:
rx_signif_edge_window_o <= s_rx_signif_edge_window;
rx_adjac_bits_window_o <= s_rx_adjac_bits_window;
rx_adjac_bits_window_o <= s_rx_adjac_bits_window;
end architecture rtl;
......
wf_tx.vhd
View file @ 4303602e
......@@ -451,10 +451,13 @@ Input_Byte_Sampling: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then
s_byte <= (others => '0');
s_byte <= (others => '0');
else
if byte_ready_p_i = '1' then
s_byte <= byte_i;
end if;
end if;
end if;
......@@ -468,8 +471,8 @@ Input_Byte_Sampling: process(uclk_i)
Manchester_Encoder_byte: process(s_byte)
begin
for I in byte_i'range loop
s_byte_manch(I*2) <= not s_byte(I);
s_byte_manch(I*2+1) <= s_byte(I);
s_byte_manch(I*2) <= not s_byte(I);
s_byte_manch(I*2+1) <= s_byte(I);
end loop;
end process;
......@@ -481,8 +484,8 @@ Input_Byte_Sampling: process(uclk_i)
Manchester_Encoder_crc_byte: process(s_crc_byte_manch)
begin
for I in s_crc_byte_manch'range loop
s_manchester_crc(I*2) <= not s_crc_byte_manch(I);
s_manchester_crc(I*2+1) <= s_crc_byte_manch(I);
s_manchester_crc(I*2) <= not s_crc_byte_manch(I);
s_manchester_crc(I*2+1) <= s_crc_byte_manch(I);
end loop;
end process;
......@@ -497,7 +500,7 @@ Input_Byte_Sampling: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then
tx_data_o <= '0';
tx_data_o <= '0';
tx_enable_o <= '0';
else
......@@ -505,7 +508,7 @@ Input_Byte_Sampling: process(uclk_i)
tx_data_o <= s_data_bit;
end if;
tx_enable_o <= s_tx_enable;
tx_enable_o <= s_tx_enable;
end if;
end if;
......@@ -519,7 +522,7 @@ Input_Byte_Sampling: process(uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then
s_bit_index <= (others => '0');
s_bit_index <= (others => '0');
else
if s_bit_index_load = '1' then
......
wf_tx_rx.vhd
View file @ 4303602e
......@@ -71,21 +71,16 @@ entity wf_tx_rx is
port (
uclk_i : in std_logic; --! User Clock
nFIP_rst_i : in std_logic;
start_produce_p_i : in std_logic;
request_byte_p_o : out std_logic;
byte_ready_p_i : in std_logic;
byte_i : in std_logic_vector(7 downto 0);
last_byte_p_i : in std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
d_clk_o : out std_logic;
d_a_i : in std_logic;
rate_i : in std_logic_vector(1 downto 0);
byte_ready_p_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0);
last_byte_p_o : out std_logic;
......@@ -93,7 +88,6 @@ entity wf_tx_rx is
code_violation_p_o : out std_logic;
crc_wrong_p_o : out std_logic;
crc_ok_p_o : out std_logic
);
end entity wf_tx_rx;
......@@ -109,16 +103,14 @@ architecture rtl of wf_tx_rx is
constant C_CLKFCDLENTGTH : natural := 4;
signal s_d_d : std_logic_vector(2 downto 0);
signal s_d_re, s_d_fe : std_logic;
signal s_clk_fixed_carrier_p : std_logic;
signal s_data_in_d3 : std_logic_vector(2 downto 0);
signal s_data_in_r_edge, s_data_in_f_edge : std_logic;
signal s_d_filtered : std_logic;
signal s_d_ready_p : std_logic;
signal s_first_fe : std_logic;
signal s_clk_carrier_p : std_logic;
signal s_clk_bit_180_p, s_sample_bit_p, s_sample_manch_bit_p : std_logic;
signal s_edge_window, edge_180_window : std_logic;
signal s_d_edge, s_code_violation : std_logic;
signal s_data_in_edge, s_code_violation : std_logic;
signal s_clk_fixed_carrier_p_d : std_logic_vector(C_CLKFCDLENTGTH - 1 downto 0);
begin
......@@ -128,13 +120,19 @@ begin
process(uclk_i)
begin
if rising_edge(uclk_i) then
s_d_d <= s_d_d(1 downto 0) & d_a_i;
s_d_re <= (not s_d_d(2)) and s_d_d(1) and s_d_d(0);
s_d_fe <= (s_d_d(2)) and (not s_d_d(1)) and (not s_d_d(0));
s_data_in_d3 <= s_data_in_d3(1 downto 0) & d_a_i;
end if;
end process;
s_d_edge <= s_d_fe or s_d_re;
s_data_in_r_edge <= (not s_data_in_d3(2)) and s_data_in_d3(1); -- 1st flip-flop not considered (metastability)
-- transition on input signal of less than 2 clock cycles are not considered
s_data_in_f_edge <= s_data_in_d3(2) and (not s_data_in_d3(1));
s_data_in_edge <= s_data_in_f_edge or s_data_in_r_edge;
uwf_tx: wf_tx
generic map(C_CLKFCDLENTGTH => C_CLKFCDLENTGTH)
......@@ -162,20 +160,16 @@ begin
last_byte_p_o => last_byte_p_o,
fss_decoded_p_o => fss_decoded_p_o,
crc_ok_p_o => crc_ok_p_o,
rx_data_f_edge_i => s_d_fe,
rx_data_r_edge_i => s_d_re,
rx_data_f_edge_i => s_data_in_f_edge,
rx_data_r_edge_i => s_data_in_r_edge,
rx_data_filtered_i => s_d_filtered,
sample_manch_bit_p_i => s_sample_manch_bit_p,
wait_d_first_f_edge_o=> s_first_fe,
code_violation_p_o => code_violation_p_o,
crc_wrong_p_o => crc_wrong_p_o,
sample_bit_p_i => s_sample_bit_p,
signif_edge_window_i => s_edge_window,
adjac_bits_window_i => edge_180_window
);
......@@ -187,27 +181,16 @@ begin
port map(
uclk_i => uclk_i, --! User Clock
uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
d_edge_i => s_d_edge,
rx_data_f_edge_i => s_d_fe,
d_edge_i => s_data_in_edge,
rx_data_f_edge_i => s_data_in_f_edge,
wait_d_first_f_edge_i => s_first_fe,
--! Bit rate \n
--! 00: 31.25 kbit/s \n
--! 01: 1 Mbit/s \n
--! 10: 2.5 Mbit/s \n
--! 11: reserved, do not use
rate_i => rate_i, --! Bit rate
rate_i => rate_i,
tx_clk_p_buff_o => s_clk_fixed_carrier_p_d,
tx_clk_o => d_clk_o,
rx_manch_clk_p_o => s_clk_carrier_p,
rx_bit_clk_p_o => s_clk_bit_180_p,
rx_signif_edge_window_o => s_edge_window,
rx_adjac_bits_window_o => edge_180_window
);
......@@ -216,7 +199,7 @@ begin
generic map (C_ACULENGTH => 10)
Port map( uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
rx_data_i => s_d_d(2),
rx_data_i => s_data_in_d3(2),
rx_data_filtered_o => s_d_filtered,
sample_bit_p_i => s_clk_bit_180_p,
sample_manch_bit_p_i => s_clk_carrier_p,
......
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