Very preliminar design. Whisbone and status block to be added. CRC does not work yet.

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@10 7f0067c9-7624-46c7-bd39-3fb5400c0213

Very preliminar design. Whisbone and status block to be added. CRC does not work yet.
git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@10 7f0067c9-7624-46c7-bd39-3fb5400c0213
446f7203 · pabloalvarez · 3c5a585d · 446f7203 · 446f7203 · 446f7203
Commit 446f7203 authored Sep 24, 2009 by pabloalvarez
14 changed files
--- a/deglitcher.vhd
+++ b/deglitcher.vhd
+--===========================================================================
+--! @file deglitcher.vhd
+--! @brief Deserialises the WorldFIP data
+--===========================================================================
+--! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
+use IEEE.NUMERIC_STD.all;    --! conversion functions
+
+
+-------------------------------------------------------------------------------
+--                                                                           --
+--                                 deglitcher                                 --
+--                                                                           --
+--                               CERN, BE/CO/HT                              --
+--                                                                           --
+-------------------------------------------------------------------------------
+--
+-- unit name: deglitcher
+--
+--! @brief 1 microsecond pulse adapted filter
+--!
+--! Used in the NanoFIP design. \n
+--! This unit serializes the data.
+--!
+--!
+--! @author	    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
+--!
+--! @date 10/08/2009
+--
+--! @version v0.01
+--
+--! @details 
+--!
+--! <b>Dependencies:</b>\n
+--! wf_engine           \n
+--! tx_engine           \n
+--! clk_gen             \n
+--! reset_logic         \n
+--! consumed_ram        \n
+--!
+--!
+--! <b>References:</b>\n
+--! 
+--! 
+--!
+--! <b>Modified by:</b>\n
+--! Author: Erik van der Bij
+--!         Pablo Alvarez Sanchez
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! 07/08/2009  v0.02  PAAS Entity Ports added, start of architecture content
+--!
+-------------------------------------------------------------------------------
+--! @todo Define I/O signals \n
+--!
+-------------------------------------------------------------------------------
+
+
+
+--============================================================================
+--! Entity declaration for deglitcher
+--============================================================================
+
+entity deglitcher is
+    Generic (C_ACULENGTH : integer := 10);
+    Port ( uclk_i : in  STD_LOGIC;
+           d_i : in  STD_LOGIC;
+           d_o : out  STD_LOGIC;
+           carrier_p_i : in  STD_LOGIC;
+           d_ready_p_o : out  STD_LOGIC);
+end deglitcher;
+
+architecture Behavioral of deglitcher is
+
+signal s_onesc : signed(C_ACULENGTH - 1 downto 0);
+begin
+
+process(uclk_i)
+begin
+if rising_edge(uclk_i) then
+	if carrier_p_i = '1' then
+		s_onesc <= to_signed(0,s_onesc'length);
+	elsif  d_i = '1' then
+		s_onesc <= s_onesc - 1;
+	else
+		s_onesc <= s_onesc + 1;
+	end if;
+end if;
+end process;
+
+process(uclk_i)
+begin if rising_edge(uclk_i) then
+	if carrier_p_i = '1' then 		
+	   d_o <= s_onesc(s_onesc'left);
+	end if;
+	d_ready_p_o <= carrier_p_i;
+	end if;
+end process;
+
+end Behavioral;
+
--- a/dpblockram.vhd
+++ b/dpblockram.vhd
+-------------------------------------------------------------------------------
+--! @file dpblockram.vhd
+-------------------------------------------------------------------------------
+--! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+----------------------------------------------------------------------------
+----------------------------------------------------------------------------
+-- --
+-- CERN, BE  --
+-- --
+-------------------------------------------------------------------------------
+--
+-- unit name: dpblockram.vhd
+--
+--! @brief The dpblockram implements a template for a true dual port ram clocked on both ports by the same clock.
+--! 
+--! @author <Pablo Alvarez(pablo.alvarez.sanchez@cern.ch)>
+--
+--! @date 24\01\2009
+--
+--! @version 1
+--
+--! @details
+--!
+--! <b>Dependencies:</b>\n
+--! 
+--!
+--! <b>References:</b>\n
+--! <reference one> \n
+--! <reference two>
+--!
+--! <b>Modified by:</b>\n
+--! Author: <name>
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! 24\01\2009 paas header included\n
+--! <extended description>
+-------------------------------------------------------------------------------
+--! @todo Adapt vhdl sintax to ohr standard\n
+--! <another thing to do> \n
+--
+-------------------------------------------------------------------------------
+
+ entity dpblockram is
+ generic (dl : integer := 42; 		-- Length of the data word 
+ 			 al : integer := 10;			-- Size of the addr map (10 = 1024 words)
+			 nw : integer := 1024);    -- Number of words
+			 									-- 'nw' has to be coherent with 'al'
+
+ port (clk  : in std_logic; 			-- Global Clock
+ 	we   : in std_logic; 				-- Write Enable
+ 	aw    : in std_logic_vector(al - 1 downto 0); -- Write Address 
+ 	ar : in std_logic_vector(al - 1 downto 0); 	 -- Read Address
+ 	di   : in std_logic_vector(dl - 1 downto 0);  -- Data input
+ 	dw  : out std_logic_vector(dl - 1 downto 0);  -- Data write, normaly open
+ 	do  : out std_logic_vector(dl - 1 downto 0)); 	 -- Data output
+ end dpblockram; 
+ 												
+--library synplify;
+--use synplify.attributes.all;
+ architecture syn of dpblockram is 
+ 
+ type ram_type is array (nw - 1 downto 0) of std_logic_vector (dl - 1 downto 0); 
+ signal RAM : ram_type; 
+ signal read_a : std_logic_vector(al - 1 downto 0); 
+ signal read_ar : std_logic_vector(al - 1 downto 0); 
+--attribute syn_ramstyle of RAM : signal is "select_ram"; 
+--attribute syn_ramstyle of RAM : signal is "area "; 
+begin 
+
+ process (clk) 
+ begin 
+ 	if (clk'event and clk = '1') then  
+ 		if (we = '1') then 
+ 			RAM(conv_integer(aw)) <= di; 
+ 		end if; 
+ 		read_a <=aw ; 
+ 		read_ar <=ar ; 
+
+ 	end if; 
+ end process; 
+ 
+
+
+ dw <= RAM(conv_integer(read_a)); 
+ do <= RAM(conv_integer(read_ar)); -- Notice that the Data Output is not registered
+
+
+ end syn;
+
+ 
--- a/nanofip.vhd
+++ b/nanofip.vhd
--- a/wf_consumed_vars.vhd
+++ b/wf_consumed_vars.vhd
+--===========================================================================
+--! @file wf_consumed_vars.vhd
+--! @brief Nanofip control unit
+--===========================================================================
+--! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
+use IEEE.NUMERIC_STD.all;    --! conversion functions
+
+use work.wf_package.all;
+
+-------------------------------------------------------------------------------
+--                                                                           --
+--                                 wf_consumed_vars                                 --
+--                                                                           --
+--                               CERN, BE/CO/HT                              --
+--                                                                           --
+-------------------------------------------------------------------------------
+--
+-- unit name: wf_consumed_vars
+--
+--! @brief Nanofip control unit. It accepts variable data and store them into block ram or in stand alone mode directly to the wf_wishbone. \n
+--!
+--! 
+--!
+--!
+--!
+--!
+--!
+--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
+--
+--! @date 11/09/2009
+--
+--! @version v0.01
+--
+--! @details 
+--!
+--! <b>Dependencies:</b>\n
+--! wf_package           \n
+--!
+--!
+--! <b>References:</b>\n
+--! 
+--! 
+--!
+--! <b>Modified by:</b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! 11/09/2009  v0.01  EB  First version \n
+--!
+-------------------------------------------------------------------------------
+--! @todo 
+--!
+-------------------------------------------------------------------------------
+
+
+
+--============================================================================
+--! Entity declaration for wf_consumed_vars
+--============================================================================
+entity wf_consumed_vars is
+
+port (
+   uclk_i    : in std_logic; --! User Clock
+   rst_i     : in std_logic;
+
+      --! Stand-alone mode
+      --! If connected to Vcc, disables sending of NanoFIP status together with 
+      --! the produced data.
+   slone_i   : in  std_logic; --! Stand-alone mode
+
+   byte_ready_p_i : in std_logic;
+	var_i : in t_var;
+--	append_status_i : in std_logic;
+	add_offset_i : in std_logic_vector(6 downto 0);
+--	data_length_i : in std_logic_vector(6 downto 0);
+	byte_i : in std_logic_vector(7 downto 0);
+
+-------------------------------------------------------------------------------
+--!  USER INTERFACE. Data and address lines synchronized with uclk_i
+-------------------------------------------------------------------------------
+
+--   dat_i     : in  std_logic_vector (15 downto 0); --! 
+
+   dat_o     : out std_logic_vector (15 downto 0); --! 
+   adr_i     : in  std_logic_vector ( 9 downto 0) --! 
+--   stb_p_i     : in  std_logic; --! Strobe
+--   ack_p_o     : out std_logic; --! Acknowledge
+--   we_p_i      : in  std_logic  --! Write enable
+
+);
+
+end entity wf_consumed_vars;
+
+
+
+
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+--! ARCHITECTURE OF wf_control
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+architecture rtl of wf_consumed_vars is
+
+
+constant c_presence_pos : natural := 0;
+constant c_identification_pos : natural := 1;
+constant c_mem_pos : natural := 2;
+constant c_last_pos : natural := 2;
+signal base_add, add: std_logic_vector(9 downto 0);
+signal s_dat_ram : std_logic_vector(7 downto 0);
+signal we_ram_p : std_logic;
+signal we_byte_p : std_logic_vector(1 downto 0);
+signal s_dat : std_logic_vector(15 downto 0);
+begin
+
+ production_dpram : dpblockram 
+ generic map(dl => 8, 		-- Length of the data word 
+ 			 al => 7,			-- Size of the addr map (10 = 1024 words)
+			 nw => 2**7)    -- Number of words
+			 									-- 'nw' has to be coherent with 'al'
+
+ port map(clk  => uclk_i,			-- Global Clock
+ 	we  => we_ram_p, 				-- Write Enable
+ 	aw  => add(6 downto 0),  -- Write Address 
+ 	ar =>  adr_i(6 downto 0), -- Read Address
+ 	di =>  byte_i, -- Data input
+ 	dw  => open,  -- Data write, normaly open
+ 	do => s_dat_ram); 	 -- Data output
+
+add <= std_logic_vector(unsigned(add_offset_i) + unsigned(base_add));
+
+process(var_i, add_offset_i, slone_i, byte_ready_p_i)
+begin
+	we_ram_p <= '0';
+	we_byte_p <= (others => '0');
+   base_add <= (others => '0');
+
+   for I in c_var_array'range loop
+	   if (c_var_array(I).response = consume) then
+      if c_var_array(I).var = var_i then
+		   base_add <= c_var_array(I).base_add;
+         if slone_i = '0' then
+			   we_ram_p <= byte_ready_p_i;
+         elsif slone_i = '1' and I = c_var_var1_pos   then
+			   if unsigned(add_offset_i) = c_byte_0_add then
+	            we_byte_p(0) <= byte_ready_p_i ;					
+				end if;
+	         if unsigned(add_offset_i) = c_byte_1_add then
+	            we_byte_p(1) <= byte_ready_p_i ;		
+				end if;
+			end if;
+         exit;
+		  end if;
+        end if;		
+   end loop;
+end process;
+
+process(uclk_i)
+begin
+   if rising_edge(uclk_i) then
+      if rst_i = '1' then
+         s_dat <= (others => '0');
+      else
+         if we_byte_p(1) = '1' then
+            s_dat(15 downto 8) <= byte_i;
+         end if;
+         if we_byte_p(0) = '1' then
+            s_dat(7 downto 0) <= byte_i;
+         end if;
+      end if;
+   end if;
+end process;
+process(s_dat, s_dat_ram, slone_i)
+begin
+   dat_o <= (others => '0');
+      if slone_i = '1' then
+         dat_o <= s_dat;
+      else
+         dat_o(7 downto 0) <= s_dat_ram;
+      end if;
+end process;
+
+end architecture rtl;
+
+-------------------------------------------------------------------------------
+--                          E N D   O F   F I L E
+-------------------------------------------------------------------------------
--- a/wf_crc.vhd
+++ b/wf_crc.vhd
+--===========================================================================
+--! @file wf_crc.vhd
+--! @brief Calculates the crc of serialized data.
+--===========================================================================
+--! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
+use IEEE.NUMERIC_STD.all;    --! conversion functions
+
+
+-------------------------------------------------------------------------------
+--                                                                           --
+--                                 wf_crc                                 --
+--                                                                           --
+--                               CERN, BE/CO/HT                              --
+--                                                                           --
+-------------------------------------------------------------------------------
+--
+-- unit name: wf_crc
+--
+--! @brief Calculates the crc of serialized data. 
+--!
+--! Used in the NanoFIP design. \n
+--!  Calculates the crc of serialized data.
+--!
+--!
+--! @author	    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
+--!
+--! @date 10/08/2009
+--
+--! @version v0.01
+--
+--! @details 
+--!
+--! <b>Dependencies:</b>\n
+--!
+--!
+--! <b>References:</b>\n
+--! 
+--! 
+--!
+--! <b>Modified by:</b>\n
+--! Author: Pablo Alvarez Sanchez
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! 07/08/2009  v0.02  PAAS Entity Ports added, start of architecture content
+--!
+-------------------------------------------------------------------------------
+--! @todo Define I/O signals \n
+--!
+-------------------------------------------------------------------------------
+--============================================================================
+--! Entity declaration for wf_crc
+--============================================================================
+entity wf_crc is
+generic( 
+			c_poly_length :  natural := 16);
+port (
+   uclk_i    : in std_logic; --! User Clock
+   rst_i     : in std_logic;
+   
+   start_p_i : in std_logic;
+	d_i       : in std_logic;
+	d_rdy_p_i     : in std_logic;
+	data_fcs_sel_n : in std_logic;
+	crc_o     : out  std_logic_vector(c_poly_length - 1 downto 0);
+	crc_rdy_p_o : out std_logic;
+	crc_ok_p : out std_logic
+
+);
+
+end entity wf_crc;
+
+
+
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+--! ARCHITECTURE OF wf_crc
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+architecture rtl of wf_crc is
+
+
+--! shift register xor mask
+constant c_poly :  std_logic_vector(c_poly_length - 1 downto 0)      := "0001110111001111"; 
+--! crc check mask
+constant c_check_mask : std_logic_vector(c_poly_length - 1 downto 0) := "0001110001101011";
+
+signal s_q, s_q_nx  : std_logic_vector(c_poly_length - 1 downto 0);
+signal s_crc_rdy_p : std_logic;
+begin
+
+G: for I in 0 to c_poly'left generate
+
+G0: if I = 0 generate
+s_q_nx(I) <= data_fcs_sel_n and (d_i xor s_q(s_q'left));
+end generate;
+
+G1: if I > 0 generate
+s_q_nx(I) <= s_q(I-1) xor (c_poly(I) and data_fcs_sel_n and (d_i xor s_q(s_q'left)));
+end generate;
+end generate;
+
+process(uclk_i)
+begin
+if rising_edge(uclk_i) then
+if rst_i = '1' then
+s_q <= (others => '1');
+else
+if start_p_i = '1' then
+s_q <= (others => '1');
+elsif d_rdy_p_i = '1' then 
+s_q <= s_q_nx;
+end if;
+s_crc_rdy_p <= d_rdy_p_i; 
+end if;
+end if;
+end process;
+
+crc_o <= s_q;
+crc_rdy_p_o <= s_crc_rdy_p;
+
+process(s_q, s_crc_rdy_p)
+variable v_q_check_mask : std_logic_vector(c_poly_length - 1 downto 0);
+begin
+v_q_check_mask := s_q xor c_check_mask;
+crc_ok_p <= '0';
+if (unsigned(not v_q_check_mask)) = 0 then 
+crc_ok_p <= s_crc_rdy_p;
+end if;
+end process;
+
+
+end architecture rtl;
+-------------------------------------------------------------------------------
+--                          E N D   O F   F I L E
+-------------------------------------------------------------------------------
--- a/wf_engine_control.vhd
+++ b/wf_engine_control.vhd
--- a/wf_package.vhd
+++ b/wf_package.vhd
--- a/wf_produced_vars.vhd
+++ b/wf_produced_vars.vhd
+--===========================================================================
+--! @file wf_produced_vars.vhd
+--! @brief Nanofip control unit
+--===========================================================================
+--! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
+use IEEE.NUMERIC_STD.all;    --! conversion functions
+
+use work.wf_package.all;
+
+-------------------------------------------------------------------------------
+--                                                                           --
+--                                 wf_produced_vars                                 --
+--                                                                           --
+--                               CERN, BE/CO/HT                              --
+--                                                                           --
+-------------------------------------------------------------------------------
+--
+-- unit name: wf_produced_vars
+--
+--! @brief Nanofip control unit. It provides with a transparent interface between the wf_control state machine and the RAM and special \n
+--!                              variable bytes not stored in RAM. wf_wishbone has write access and wf_control read access.\n
+--!
+--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
+--
+--! @date 11/09/2009
+--!
+--! @version v0.01
+--!
+--! @details 
+--!
+--! <b>Dependencies:</b>\n
+--! wf_package           \n
+--!
+--!
+--! <b>References:</b>\n
+--! 
+--! 
+--!
+--! <b>Modified by:</b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! 11/09/2009  v0.01  EB  First version \n
+--!
+-------------------------------------------------------------------------------
+--! @todo 
+--!
+-------------------------------------------------------------------------------
+
+
+
+--============================================================================
+--! Entity declaration for wf_produced_vars
+--============================================================================
+entity wf_produced_vars is
+
+port (
+   uclk_i    : in std_logic; --! User Clock
+   rst_i     : in std_logic;
+
+ 
+
+	
+
+      --! Identification selection (see M_ID, C_ID)
+--   s_id_o    : out std_logic_vector (1 downto 0); --! Identification selection
+
+      --! Identification variable settings. 
+      --! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to 
+      --! obtain different values for the Model data (i=0,1,2,3).\n
+      --! M_ID[i] connected to: Gnd S_ID0 SID1 Vcc               \n
+      --! Model [2*i]            0    1    0    1                \n
+      --! Model [2*i+1]          0    0    1    1
+   m_id_i    : in  std_logic_vector (3 downto 0); --! Model identification settings
+
+      --! Constructor identification settings.
+      --! Connect the ID inputs either to Gnd, Vcc, S_ID[0] or S_ID[1] to 
+      --! obtain different values for the Model data (i=0,1,2,3).\n
+      --! C_ID[i] connected to: Gnd S_ID0 SID1 Vcc               \n
+      --! Constructor[2*i]       0    1    0    1                \n
+      --! Constructor[2*i+1]     0    0    1    1
+   c_id_i    : in  std_logic_vector (3 downto 0); --! Constructor identification settings
+
+      --! Stand-alone mode
+      --! If connected to Vcc, disables sending of NanoFIP status together with 
+      --! the produced data.
+   slone_i   : in  std_logic; --! Stand-alone mode
+
+
+      --! No NanoFIP status transmission
+      --! If connected to Vcc, disables sending of NanoFIP status together with 
+      --! the produced data.
+   nostat_i  : in  std_logic; --! No NanoFIP status transmission
+
+   stat_i : in std_logic_vector(7 downto 0); -- NanoFIP status 
+	
+--   prod_byte_i : in std_logic_vector(7 downto 0);
+	var_i : in t_var;
+	append_status_i : in std_logic;
+	add_offset_i : in std_logic_vector(6 downto 0);
+	data_length_i : in std_logic_vector(6 downto 0);
+	byte_o : out std_logic_vector(7 downto 0);
+
+-------------------------------------------------------------------------------
+--!  USER INTERFACE. Data and address lines synchronized with uclk_i
+-------------------------------------------------------------------------------
+
+   dat_i     : in  std_logic_vector (15 downto 0); --! 
+
+--   dat_o     : out std_logic_vector (15 downto 0); --! 
+   adr_i     : in  std_logic_vector ( 9 downto 0); --! 
+--   stb_p_i     : in  std_logic; --! Strobe
+--   ack_p_o     : out std_logic; --! Acknowledge
+   we_p_i      : in  std_logic  --! Write enable
+
+);
+
+end entity wf_produced_vars;
+
+
+
+
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+--! ARCHITECTURE OF wf_produced_vars
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+architecture rtl of wf_produced_vars is
+
+
+constant c_presence_pos : natural := 0;
+constant c_identification_pos : natural := 1;
+constant c_mem_pos : natural := 2;
+constant c_last_pos : natural := 2;
+signal s_byte: std_logic_vector(7 downto 0);
+signal s_mem_byte : std_logic_vector(7 downto 0);
+signal s_io_byte : std_logic_vector(7 downto 0);
+signal base_add, add: std_logic_vector(9 downto 0);
+
+begin
+
+ production_dpram : dpblockram 
+ generic map(dl => 8, 		-- Length of the data word 
+ 			 al => 7,			-- Size of the addr map (10 = 1024 words)
+			 nw => 2**7)    -- Number of words
+			 									-- 'nw' has to be coherent with 'al'
+
+ port map(clk  => uclk_i,			-- Global Clock
+ 	we  => we_p_i, 				-- Write Enable
+ 	aw  => adr_i(6 downto 0),  -- Write Address 
+ 	ar => add(6 downto 0), -- Read Address
+ 	di =>  dat_i(7 downto 0), -- Data input
+ 	dw  => open,  -- Data write, normaly open
+ 	do => s_mem_byte); 	 -- Data output
+
+-- For the moment there is only one variable produced, but I think it is nice to have
+-- defined an offset for every variable in case we produce more variables in the future
+
+add <= std_logic_vector(unsigned(add_offset_i) + unsigned(base_add));
+
+process(s_mem_byte, var_i, add_offset_i, s_io_byte, data_length_i, append_status_i, stat_i, slone_i, c_id_i, m_id_i)
+begin
+   s_byte <= (others => '0');
+	base_add <= (others => '0');
+   for I in c_var_array'range loop
+	   if (c_var_array(I).response = produce) then
+      if c_var_array(I).var = var_i then
+		   base_add <= c_var_array(I).base_add;
+         if  c_var_array(I).var = c_st_var_identification then
+		      if unsigned(add_offset_i) = c_cons_byte_add then
+               s_byte(c_id_i'range) <= c_id_i;
+				exit;
+		      elsif unsigned(add_offset_i) = c_model_byte_add then
+               s_byte(m_id_i'range) <= m_id_i;
+				exit;
+				end if;
+			end if;
+		   if unsigned(add_offset_i) = c_pdu_byte_add then
+            s_byte <= c_var_array(I).byte_array(to_integer(unsigned(add_offset_i(3 downto 0))));
+         elsif unsigned(add_offset_i) = c_var_length_add then
+            s_byte(data_length_i'range) <= data_length_i;
+         elsif (unsigned(add_offset_i) = unsigned(data_length_i)) and append_status_i = '1' then
+            s_byte <= stat_i;
+         elsif unsigned(add_offset_i) <  c_var_array(I).array_length then
+            s_byte <= s_mem_byte;
+         elsif slone_i = '1' then
+            s_byte <= s_io_byte;
+         else
+            s_byte <= c_var_array(I).byte_array(to_integer(unsigned(add_offset_i(3 downto 0))));
+         end if;
+         exit;
+		end if;
+		end if;
+   end loop;
+end process;
+
+s_io_byte <= dat_i(15 downto 8) when add_offset_i(0) = '1' else dat_i(7 downto 0);
+byte_o <= s_byte;
+end architecture rtl;
+-------------------------------------------------------------------------------
+--                          E N D   O F   F I L E
+-------------------------------------------------------------------------------
--- a/wf_rx.vhd
+++ b/wf_rx.vhd
--- a/wf_rx_osc.vhd
+++ b/wf_rx_osc.vhd
+--===========================================================================
+--! @file wf_rx_osc.vhd
+--! @brief Deserialises the WorldFIP data
+--===========================================================================
+--! Standard library
+library IEEE;
+--! Standard packages
+use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
+use IEEE.NUMERIC_STD.all;    --! conversion functions
+
+
+-------------------------------------------------------------------------------
+--                                                                           --
+--                                 wf_rx                                 --
+--                                                                           --
+--                               CERN, BE/CO/HT                              --
+--                                                                           --
+-------------------------------------------------------------------------------
+--
+-- unit name: wf_rx_osc
+--
+--! @brief Numeric oscillator that generates a 1MHz pulse locked to a 
+--!
+--! Used in the NanoFIP design. \n
+--! This unit serializes the data.
+--!
+--!
+--! @author	    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
+--!
+--! @date 10/08/2009
+--
+--! @version v0.01
+--
+--! @details 
+--!
+--! <b>Dependencies:</b>\n
+--! wf_engine           \n
+--! tx_engine           \n
+--! clk_gen             \n
+--! reset_logic         \n
+--! consumed_ram        \n
+--!
+--!
+--! <b>References:</b>\n
+--! 
+--! 
+--!
+--! <b>Modified by:</b>\n
+--! Author: Erik van der Bij
+--!         Pablo Alvarez Sanchez
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! 07/08/2009  v0.02  PAAS Entity Ports added, start of architecture content
+--!
+-------------------------------------------------------------------------------
+--! @todo Define I/O signals \n
+--!
+-------------------------------------------------------------------------------
+
+
+
+--============================================================================
+--! Entity declaration for wf_rx_osc
+--============================================================================
+entity wf_rx_osc is
+generic (C_OSC_LENGTH : integer := 20;
+         C_QUARTZ_PERIOD : real := 25.0;
+			C_CLKFCDLENTGTH :  natural := 3 
+			);
+
+port (
+   uclk_i    : in std_logic; --! User Clock
+   rst_i     : in std_logic;
+
+	d_edge_i : in std_logic;
+
+   load_phase_i : in std_logic;	
+    
+      --! Bit rate         \n
+      --! 00: 31.25 kbit/s => 62.5 KHz \n
+      --! 01: 1 Mbit/s  => 2 MHz  \n
+      --! 10: 2.5 Mbit/s  => 5 MHz  \n
+      --! 11: reserved, do not use
+   rate_i    : in  std_logic_vector (1 downto 0); --! Bit rate
+
+   clk_fixed_carrier_p_o : out std_logic;
+   clk_fixed_carrier_p_d_o : out std_logic_vector(C_CLKFCDLENTGTH -1 downto 0);
+   clk_fixed_carrier_o : out std_logic;
+	
+   clk_carrier_p_o : out std_logic;
+	clk_carrier_180_p_o : out std_logic;
+	
+	clk_bit_p_o  : out std_logic;
+	clk_bit_90_p_o  : out std_logic;
+	clk_bit_180_p_o  : out std_logic;
+	clk_bit_270_p_o  : out std_logic;
+	
+	edge_window_o : out std_logic;
+   edge_180_window_o : out std_logic;
+	phase_o : out std_logic_vector(C_OSC_LENGTH -1  downto 0)
+);
+
+end entity wf_rx_osc;
+
+
+
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+--! ARCHITECTURE OF wf_rx_osc
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+architecture rtl of wf_rx_osc is
+
+      --! Bit rate         \n
+      --! 31.25 kbit => 62.5 KHz carrier \n
+constant c_period_31_25kbit : real := (C_QUARTZ_PERIOD*real(2**C_OSC_LENGTH))/32000.0;
+      --! 1 Mbit/s  => 2MHz  carrier  \n
+constant c_period_1_mbit : real := (C_QUARTZ_PERIOD*real(2**C_OSC_LENGTH))/1000.0;
+      --! 2.5 Mbit/s  => 5MHz carrier \n
+constant c_period_2_5mbit : real := (C_QUARTZ_PERIOD*real(2**C_OSC_LENGTH))/400.0;
+--
+--constant c_period_31_25kbit_signed : signed(C_OSC_LENGTH -1 downto 0) := to_signed(integer(c_period_31_25kbit), C_OSC_LENGTH);
+--      --! 1 Mbit/s     \n
+--constant c_period_1_mbit_signed : signed(C_OSC_LENGTH -1 downto 0) := to_signed(integer(c_period_1_mbit), C_OSC_LENGTH);
+--      --! 2.5 Mbit/s   \n
+--constant c_period_2_5mbit_signed : signed(C_OSC_LENGTH -1 downto 0) := to_signed(integer(c_period_2_5mbit), C_OSC_LENGTH);
+
+ type t_period is array (Natural range <>) of signed(C_OSC_LENGTH -1 downto 0);
+
+
+constant C_PERIOD : t_period(3 downto 0) := (0 => to_signed(integer(c_period_31_25kbit), C_OSC_LENGTH),
+                                 1 => to_signed(integer(c_period_1_mbit), C_OSC_LENGTH),
+                                 2 => to_signed(integer(c_period_2_5mbit), C_OSC_LENGTH),
+                                 3 => to_signed(integer(c_period_2_5mbit), C_OSC_LENGTH));
+
+											
+signal s_tag, s_phase, s_free_c :  signed(C_OSC_LENGTH -1 downto 0);
+
+
+signal s_period : signed(C_OSC_LENGTH -1 downto 0);
+signal s_nx_clk_bit  : std_logic;
+signal s_nx_clk_bit_90  :  std_logic;
+signal s_nx_clk_bit_180  :  std_logic;
+signal s_nx_clk_bit_270  :  std_logic;
+
+signal s_clk_bit  :  std_logic;
+signal s_clk_bit_90  :  std_logic;
+signal s_clk_bit_180  :  std_logic;
+signal s_clk_bit_270  :  std_logic;
+signal s_clk_fixed_carrier, s_nx_clk_fixed_carrier, s_clk_fixed_carrier_p :  std_logic;
+signal s_clk_fixed_carrier_p_d : std_logic_vector(C_CLKFCDLENTGTH -1 downto 0);
+begin
+
+s_period <= C_PERIOD(to_integer(unsigned(rate_i)));
+
+process(uclk_i)
+   begin
+      if rising_edge(uclk_i) then
+		   if rst_i = '1' then
+			   s_free_c <= to_signed(0, s_free_c'length);
+				s_tag <= to_signed(0, s_free_c'length);
+            s_clk_bit      <= '0';
+            s_clk_bit_90   <= '0';
+            s_clk_bit_180  <= '0';
+            s_clk_bit_270  <= '0';
+			   s_clk_fixed_carrier <= '0';
+			   s_clk_fixed_carrier_p_d <= (others => '0');
+			else
+            s_free_c <= s_free_c + s_period;
+				if load_phase_i = '1' and d_edge_i = '1' then
+				   s_tag <=  s_free_c; 
+				end if;
+            s_clk_bit      <= s_nx_clk_bit;
+            s_clk_bit_90   <= s_nx_clk_bit_90;
+            s_clk_bit_180  <= s_nx_clk_bit_180;
+            s_clk_bit_270  <= s_nx_clk_bit_270;
+			   s_clk_fixed_carrier <= s_nx_clk_fixed_carrier;
+			   s_clk_fixed_carrier_p_d <=s_clk_fixed_carrier_p_d(s_clk_fixed_carrier_p_d'left -1 downto 0)&s_clk_fixed_carrier_p;
+		   end if;
+      end if;
+end process;
+	clk_fixed_carrier_o <= s_clk_fixed_carrier;
+   clk_fixed_carrier_p_d_o <= s_clk_fixed_carrier_p_d;
+	
+	clk_bit_p_o  <= s_nx_clk_bit and (not s_clk_bit); 
+	clk_bit_90_p_o  <= s_nx_clk_bit_90 and (not s_clk_bit_90); 
+	clk_bit_180_p_o  <= s_nx_clk_bit_180 and (not s_clk_bit_180); 
+	clk_bit_270_p_o  <= s_nx_clk_bit_270 and (not s_clk_bit_270); 
+
+   s_clk_fixed_carrier_p <= s_nx_clk_fixed_carrier and (not s_clk_fixed_carrier);
+   clk_fixed_carrier_p_o <= s_clk_fixed_carrier_p; 
+
+   clk_carrier_p_o  <= s_nx_clk_bit xor s_clk_bit; 
+	clk_carrier_180_p_o <= s_nx_clk_bit_90 xor s_clk_bit_90; 
+
+
+s_phase <= s_tag - s_free_c;
+phase_o <= std_logic_vector(s_phase);
+
+process( s_phase, s_period, s_free_c)
+begin
+   edge_window_o <= '0';
+   edge_180_window_o <= '1';
+   s_nx_clk_bit <= '0';
+   s_nx_clk_bit_90 <= '0';
+   s_nx_clk_bit_180 <= '0';
+   s_nx_clk_bit_270 <= '0'; 
+   s_nx_clk_fixed_carrier <= '0';
+
+	if (signed(s_free_c(s_free_c'left -1 downto 0)) < 0) then
+    s_nx_clk_fixed_carrier<= '1';
+	else
+    s_nx_clk_fixed_carrier <= '0';
+   end if;	
+
+
+	if (s_phase < (4*s_period)) and (s_phase > (-4*s_period)) then
+      edge_window_o <= '1';
+	else
+      edge_window_o <= '0';
+   end if;
+	
+	if ((s_phase - 2**(s_phase'length-1)) < (4*s_period)) and ((s_phase - 2**(s_phase'length-1)) > (-4*s_period)) then
+      edge_180_window_o <= '1';
+	else
+      edge_180_window_o <= '0';
+   end if;
+	
+	
+	if (s_phase < 0) then
+      s_nx_clk_bit <= '1';
+      s_nx_clk_bit_180 <= '0';
+	else
+      s_nx_clk_bit <= '0';
+      s_nx_clk_bit_180 <= '1';
+   end if;	
+
+
+	if ((s_phase - (2**(C_OSC_LENGTH-2))) < 0) then
+      s_nx_clk_bit_90 <= '0';
+      s_nx_clk_bit_270 <= '1';
+	else
+      s_nx_clk_bit_90 <= '1';
+      s_nx_clk_bit_270 <= '0';
+   end if;	
+
+
+end process;
+
+
+end architecture rtl;
+-------------------------------------------------------------------------------
+--                          E N D   O F   F I L E
+-------------------------------------------------------------------------------
--- a/wf_rx_osc_tb.vhd
+++ b/wf_rx_osc_tb.vhd
+
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   14:47:37 08/13/2009
+-- Design Name:   wf_rx_osc
+-- Module Name:   C:/ohr/CernFIP/trunk/software/ISE/CernFIP/wf_rx_osc_tb.vhd
+-- Project Name:  CernFIP
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: wf_rx_osc
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
+-- that these types always be used for the top-level I/O of a design in order 
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.ALL;
+
+ENTITY wf_rx_osc_tb_vhd IS
+END wf_rx_osc_tb_vhd;
+
+ARCHITECTURE behavior OF wf_rx_osc_tb_vhd IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT wf_rx_osc
+	PORT(
+		uclk_i : IN std_logic;
+		rst_i : IN std_logic;
+		d_re_i : IN std_logic;
+		load_phase_i : IN std_logic;
+		rate_i : IN std_logic_vector(1 downto 0);
+		  clk_carrier_p_o : out std_logic;
+        clk_carrier_180_p_o : out std_logic;    
+		      
+		clk_bit_p_o : OUT std_logic;
+		clk_bit_90_p_o : OUT std_logic;
+		clk_bit_180_p_o : OUT std_logic;
+		clk_bit_270_p_o : OUT std_logic;
+		edge_window_o : OUT std_logic;
+		phase_o : OUT std_logic_vector(19 downto 0)
+		);
+	END COMPONENT;
+
+	--Inputs
+	SIGNAL uclk_i :  std_logic := '0';
+	SIGNAL rst_i :  std_logic := '0';
+	SIGNAL d_re_i :  std_logic := '0';
+	SIGNAL load_phase_i :  std_logic := '0';
+	SIGNAL rate_i :  std_logic_vector(1 downto 0) := (others=>'0');
+
+	--Outputs
+	SIGNAL clk_bit_p_o :  std_logic;
+	SIGNAL clk_bit_90_p_o :  std_logic;
+	SIGNAL clk_bit_180_p_o :  std_logic;
+	SIGNAL clk_bit_270_p_o :  std_logic;
+	SIGNAL edge_window_o :  std_logic;
+	signal clk_carrier_p_o : std_logic;
+	signal clk_carrier_180_p_o : std_logic;
+	
+	SIGNAL phase_o :  std_logic_vector(19 downto 0);
+   signal s_bit_period : time;
+BEGIN
+
+
+process
+begin
+uclk_i <= '0';
+wait for 13 ns;
+uclk_i <= '1';
+wait for 12 ns;
+end process;
+
+rst_i <= '0', '1' after 110 ns, '0' after 130 ns;
+
+s_bit_period <= 2 us;
+rate_i <= "01";
+
+process
+begin
+wait for 1 ns;
+while true loop
+d_re_i <= '0';
+wait for s_bit_period - 30 ns;
+wait until falling_edge(uclk_i);
+d_re_i <= '1';
+wait until falling_edge(uclk_i);
+end loop;
+end process;
+
+
+
+
+load_phase_i  <= '0', '1' after 210 ns, '0' after 100030 ns;
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: wf_rx_osc PORT MAP(
+		uclk_i => uclk_i,
+		rst_i => rst_i,
+		d_re_i => d_re_i,
+		load_phase_i => load_phase_i,
+		rate_i => rate_i,
+
+      clk_carrier_p_o => clk_carrier_p_o,
+	   clk_carrier_180_p_o => clk_carrier_180_p_o,
+
+		clk_bit_p_o => clk_bit_p_o,
+		clk_bit_90_p_o => clk_bit_90_p_o,
+		clk_bit_180_p_o => clk_bit_180_p_o,
+		clk_bit_270_p_o => clk_bit_270_p_o,
+		edge_window_o => edge_window_o,
+		phase_o => phase_o
+	);
+
+--	tb : PROCESS
+--	BEGIN
+--
+--		-- Wait 100 ns for global reset to finish
+--		wait for 100 ns;
+--
+--		-- Place stimulus here
+--
+--		wait; -- will wait forever
+--	END PROCESS;
+
+END;
--- a/wf_rx_tb.vhd
+++ b/wf_rx_tb.vhd
+
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:42:52 08/14/2009
+-- Design Name:   wf_rx
+-- Module Name:   C:/ohr/CernFIP/trunk/hdl/design/wf_rx_tb.vhd
+-- Project Name:  CernFIP
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: wf_rx
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
+-- that these types always be used for the top-level I/O of a design in order 
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.ALL;
+
+ENTITY wf_rx_tb_vhd IS
+END wf_rx_tb_vhd;
+
+ARCHITECTURE behavior OF wf_rx_tb_vhd IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT wf_rx
+	PORT(
+		uclk_i : IN std_logic;
+		rst_i : IN std_logic;
+		d_a_i : IN std_logic;
+		rate_i : IN std_logic_vector(1 downto 0);
+		start_send_p_i : IN std_logic;
+		byte_ready_p_i : IN std_logic;
+		byte_i : IN std_logic_vector(7 downto 0);
+		last_byte_i : IN std_logic;          
+		request_byte_p_o : OUT std_logic;
+		send_ended_p_o : OUT std_logic;
+		bit_strobe_p_o : OUT std_logic;
+		data_o : OUT std_logic_vector(7 downto 0);
+		data_e_o : OUT std_logic
+		);
+	END COMPONENT;
+
+	--Inputs
+	SIGNAL uclk_i :  std_logic := '0';
+	SIGNAL rst_i :  std_logic := '0';
+	SIGNAL d_a_i :  std_logic := '0';
+	SIGNAL start_send_p_i :  std_logic := '0';
+	SIGNAL byte_ready_p_i :  std_logic := '0';
+	SIGNAL last_byte_i :  std_logic := '0';
+	SIGNAL rate_i :  std_logic_vector(1 downto 0) := (others=>'0');
+	SIGNAL byte_i :  std_logic_vector(7 downto 0) := (others=>'0');
+
+	--Outputs
+	SIGNAL request_byte_p_o :  std_logic;
+	SIGNAL send_ended_p_o :  std_logic;
+	SIGNAL bit_strobe_p_o :  std_logic;
+	SIGNAL data_o :  std_logic_vector(7 downto 0);
+	SIGNAL data_e_o :  std_logic;
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: wf_rx PORT MAP(
+		uclk_i => uclk_i,
+		rst_i => rst_i,
+		d_a_i => d_a_i,
+		rate_i => rate_i,
+		start_send_p_i => start_send_p_i,
+		request_byte_p_o => request_byte_p_o,
+		byte_ready_p_i => byte_ready_p_i,
+		byte_i => byte_i,
+		last_byte_i => last_byte_i,
+		send_ended_p_o => send_ended_p_o,
+		bit_strobe_p_o => bit_strobe_p_o,
+		data_o => data_o,
+		data_e_o => data_e_o
+	);
+
+	tb : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 100 ns;
+
+		-- Place stimulus here
+
+		wait; -- will wait forever
+	END PROCESS;
+
+END;
--- a/wf_tx.vhd
+++ b/wf_tx.vhd
--- a/wf_tx_rx.vhd
+++ b/wf_tx_rx.vhd