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nanoFIP - Gateware
Commit 5f70c25e authored by kblantos's avatar kblantos
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JTAG TRST controller introduced. It allows to reprogram the Rad-Tol DI/OT SB through worldfip

parent 3ed0201d
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Showing with 180 additions and 24 deletions
src/Manifest.py
View file @ 5f70c25e
......@@ -24,4 +24,5 @@ files = [
"wf_status_bytes_gen.vhd",
"wf_tx_osc.vhd",
"wf_tx_serializer.vhd",
"wf_wb_controller.vhd"]
"wf_wb_controller.vhd",
"wf_trst_controller.vhd"]
src/wf_jtag_controller.vhd
View file @ 5f70c25e
......@@ -338,7 +338,7 @@ begin
(s_tck_c = (5*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (7*s_tck_half_period) +s_tck_quarter_period) else '0';
jc_tck_o <= 'Z' when (jc_st = IDLE) else s_tck;
jc_tck_o <= s_tck;
......@@ -432,13 +432,8 @@ begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
jc_tms_o <= 'Z'; --'0';
jc_tdi_o <= 'Z'; --'0';
elsif jc_st = IDLE then
jc_tms_o <= 'Z';
jc_tdi_o <= 'Z';
jc_tms_o <= '0';
jc_tdi_o <= '0';
elsif s_tck_f_edge_p = '1' then
......@@ -518,4 +513,4 @@ end architecture rtl;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
\ No newline at end of file
src/wf_package.vhd
View file @ 5f70c25e
......@@ -931,6 +931,7 @@ end component wf_rx_osc;
r_fcser_o : out std_logic;
ack_o : out std_logic;
dat_o : out std_logic_vector (15 downto 0);
jc_trst_n_o : out std_logic;
jc_tms_o : out std_logic;
jc_tdi_o : out std_logic;
jc_tck_o : out std_logic);
......@@ -1062,6 +1063,17 @@ end component wf_wb_controller;
---------------------------------------------------------------------------------------------------
component wf_trst_controller is
port (
uclk_i : in std_logic;
nfip_rst_i : in std_logic;
var_id_i : in t_var;
jc_trst_o : out std_logic);
-----------------------------------------------------------------
end component wf_trst_controller;
---------------------------------------------------------------------------------------------------
function f_manch_encoder (word_i :std_logic_vector) return std_logic_vector;
......@@ -1106,4 +1118,4 @@ end wf_package;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
---------------------------------------------------------------------------------------------------
src/wf_trst_controller.vhd 0 → 100644
View file @ 5f70c25e
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CEM-EDL |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_trst_controller |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_trst_controller.vhd |
-- |
-- Description After the reception and validation of a consumed var_4 RP_DAT frame, the unit |
-- is responsible for driving the "nanoFIP, User Interface, JTAG TRST Controller" |
-- signal JC_TRST_N which is the reset of the JTAG TAP copntroller. |
-- |
-- o JC_TRST should be asserted in order to allow reprogramming of the Radiation |
-- tolerant DI/OT System Board through worldfip. |
-- |
-- |
-- Authors Konstantinos Blantos <Konstantinos.Blantos@cern.ch> |
-- Date 03/2024 |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- SOLDERPAD LICENSE |
-- Copyright CERN 2014-2018 |
-- ------------------------------------ |
-- Copyright and related rights are licensed under the Solderpad Hardware License, Version 2.0 |
-- (the "License"); you may not use this file except in compliance with the License. |
-- You may obtain a copy of the License at http://solderpad.org/licenses/SHL-2.0. |
-- Unless required by applicable law or agreed to in writing, software, hardware and materials |
-- distributed under this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR |
-- CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language |
-- governing permissions and limitations under the License. |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_jtag_controller
--=================================================================================================
entity wf_trst_controller is port(
-- INPUTS
-- nanoFIP User Interface, General signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the wf_engine_control unit
var_id_i : in t_var;
-- OUTPUTS
-- nanoFIP User Interface, JTAG TRST Controller signal
jc_trst_o : out std_logic); -- JTAG TRST output
end entity wf_trst_controller;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_trst_controller is
-- Internal JTAG TRST signal
signal s_jc_trst : std_logic;
-- Internal var_id signal
signal s_var : t_var;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
-- Assign var_id
s_var <= var_id_i;
-- Assign output JTAG TRST signal
JC_TRST_Controller : process(uclk_i)
begin
if rising_edge(uclk_i) then
if nfip_rst_i = '1' then
s_jc_trst <= '0';
elsif (s_var = var_4 or s_var = var_5) then
s_jc_trst <= '1';
elsif (s_var = var_rst) then
s_jc_trst <= '0';
end if;
end if;
end process JC_TRST_Controller;
jc_trst_o <= s_jc_trst;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
syn/Designer_Synpl_Pinout.pdc
View file @ 5f70c25e
......@@ -19,7 +19,7 @@
set_io fd_rstn_o \
-pinname 118 \
-fixed yes \
-iostd LVTTL \
-iostd LVTTL \
-DIRECTION Output
......@@ -598,28 +598,33 @@ set_io rstpon_i \
-DIRECTION Input
set_io jc_tck_o \
set_io jc_tck_o \
-pinname 42 \
-fixed yes \
-fixed yes \
-DIRECTION Output
set_io jc_tms_o \
set_io jc_tms_o \
-pinname 44 \
-fixed yes \
-res_pull down \
-fixed yes \
-DIRECTION Output
set_io jc_tdi_o \
set_io jc_tdi_o \
-pinname 43 \
-fixed yes \
-res_pull down \
-fixed yes \
-DIRECTION Output
set_io jc_tdo_i \
set_io jc_tdo_i \
-pinname 47 \
-fixed yes \
-fixed yes \
-DIRECTION Input
set_io jc_trst_n_o \
-pinname 39 \
-fixed yes \
-res_pull down \
-DIRECTION Output
#set_io fd_rxcdn_i \
# -pinname 121 \
......
syn/build_nanofip.tcl
View file @ 5f70c25e
......@@ -58,6 +58,7 @@ import_files \
-hdl_source {../src/wf_tx_osc.vhd} \
-hdl_source {../src/wf_tx_serializer.vhd} \
-hdl_source {../src/wf_wb_controller.vhd} \
-hdl_source {../src/wf_trst_controller.vhd} \
-hdl_source {../top/nanofip.vhd}
create_links \
......
top/nanofip.vhd
View file @ 5f70c25e
......@@ -314,6 +314,7 @@ entity nanofip is port(
-- User Interface, JTAG Controller
jc_trst_n_o: out std_logic; -- Drives the JTAG Test Reset
jc_tms_o : out std_logic; -- Drives the JTAG Test Mode Select of the target TAP
jc_tdi_o : out std_logic; -- Drives the JTAG Test Data In of the target TAP
jc_tck_o : out std_logic); -- Drives the JTAG Test Clock of the target TAP
......@@ -355,6 +356,11 @@ architecture struc of nanofip is
-- wf_model_constr_dec outputs
signal s_jc_mem_adr_rd : std_logic_vector (8 downto 0);
signal s_jc_tdo_byte : std_logic_vector (7 downto 0);
-- wf_jtag_controller outputs
signal s_jc_trst : std_logic;
-- wf nanofip output data and acknowledge
signal s_data_o : std_logic_vector (15 downto 0);
signal s_ack_o : std_logic;
signal r_tler, u_pacer, u_cacer, r_fcser : std_logic; -- for v3
......@@ -412,13 +418,14 @@ begin
var1_rdy_o => s_var1_rdy,
var2_rdy_o => s_var2_rdy,
jc_start_p_o => s_jc_start_p,
data_o => dat_o,
data_o => s_data_o,
nfip_status_r_tler_p_o => s_nfip_status_r_tler,
assert_rston_p_o => s_assert_RSTON_p,
rst_nfip_and_fd_p_o => s_reset_nFIP_and_FD_p,
jc_mem_data_o => s_jc_mem_data);
-------------------------------------------------------------
dat_o <= s_data_o;
---------------------------------------------------------------------------------------------------
......@@ -530,6 +537,7 @@ begin
jc_mem_adr_rd_o => s_jc_mem_adr_rd);
-----------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- wf_engine_control --
---------------------------------------------------------------------------------------------------
......@@ -567,6 +575,22 @@ begin
var3_rdy_o <= s_var3_rdy;
---------------------------------------------------------------------------------------------------
-- wf_trst_controller --
---------------------------------------------------------------------------------------------------
jtag_trst_controller : wf_trst_controller
port map(
uclk_i => uclk_i,
nfip_rst_i => s_nfip_intern_rst,
var_id_i => s_var,
-------------------------------------------------------------
jc_trst_o => s_jc_trst);
-------------------------------------------------------------
jc_trst_n_o <= s_jc_trst;
---------------------------------------------------------------------------------------------------
-- wf_model_constr_decoder --
......@@ -600,9 +624,11 @@ begin
wb_adr_id_i => adr_i (9 downto 7),
-------------------------------------------------------------
wb_ack_prod_p_o => s_wb_ack_prod,
wb_ack_p_o => ack_o);
wb_ack_p_o => s_ack_o);
-------------------------------------------------------------
ack_o <= s_ack_o;
end architecture struc;
--=================================================================================================
......
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