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nanoFIP - Gateware
Commit 622c4116 authored by egousiou's avatar egousiou
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trial: ack signal only 1 clk tick after stb 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@64 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent d6fdf0fd
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Showing with 187 additions and 159 deletions
nanofip.vhd
View file @ 622c4116
......@@ -189,7 +189,6 @@ architecture struc of nanofip is
end component;
signal s_append_status_from_control : std_logic;
signal s_data_length_from_control : std_logic_vector(6 downto 0);
signal s_byte_to_tx : std_logic_vector(7 downto 0);
signal s_rst : std_logic;
......@@ -216,7 +215,7 @@ architecture struc of nanofip is
signal s_mps : std_logic_vector(7 downto 0);
signal s_wb_d_d : std_logic_vector(15 downto 0);
signal s_m_id_dec_o, s_c_id_dec_o : std_logic_vector(7 downto 0);
signal s_stb_d, s_we_d : std_logic;
signal s_stb_d, s_we_d, s_cyc_d : std_logic;
signal s_reset_nFIP_and_FD, s_reset_rston : std_logic;
signal s_adr_d : std_logic_vector ( 9 downto 0);
......@@ -261,7 +260,6 @@ begin
var2_rdy_o => s_var2_rdy,
var3_rdy_o => s_var3_rdy,
var_o => s_var_from_control,
append_status_o => s_append_status_from_control,
add_offset_o => s_add_offset_from_control,
data_length_o => s_data_length_from_control,
consume_byte_p_o => s_cons_byte_we_from_control
......@@ -302,7 +300,7 @@ begin
subs_i => subs_i,
byte_ready_p_i => s_cons_byte_we_from_control,
var_i => s_var_from_control,
add_offset_i => s_add_offset_from_control,
index_offset_i => s_add_offset_from_control,
byte_i => s_byte_from_rx,
wb_rst_i => rst_i,
wb_clk_i => wclk_i,
......@@ -328,8 +326,7 @@ begin
nFIP_status_byte_i => s_stat,
mps_byte_i => s_mps,
var_i => s_var_from_control,
append_status_i => s_append_status_from_control,
add_offset_i => s_add_offset_from_control,
index_offset_i => s_add_offset_from_control,
data_length_i => s_data_length_from_control,
byte_o => s_byte_to_tx,
wb_rst_i => rst_i,
......@@ -337,7 +334,7 @@ begin
wb_clk_i => wclk_i,
wb_adr_i => s_adr_d,
wb_stb_p_i => s_stb_d,
wb_cyc_i => cyc_i,
wb_cyc_i => s_cyc_d,
wb_ack_prod_p_o => s_ack_produced,
wb_we_p_i => s_we_d
);
......@@ -388,6 +385,7 @@ begin
s_adr_d <= (others => '0');
else
s_wb_d_d <= dat_i;
s_cyc_d <= cyc_i;
s_stb_d <= stb_i;
s_we_d <= we_i;
s_adr_d <= adr_i;
......
wf_consumed_vars.vhd
View file @ 622c4116
......@@ -94,7 +94,7 @@ port (
-- Signals for the wf_engine_control
byte_ready_p_i : in std_logic;
add_offset_i : in std_logic_vector(6 downto 0);
index_offset_i : in std_logic_vector(6 downto 0);
var_i : in t_var;
-- Signals for the receiver wf_rx
......@@ -192,11 +192,11 @@ end process;
--! s_rp_dat_control_byte_ok stays asserted until a new consumed variable arrives and its
--! rp_dat.Control byte is to be checked. The signal is used by the process Bytes_Consumption.
Check_rp_dat_control_byte: process (byte_ready_p_i,add_offset_i,byte_i)
Check_rp_dat_control_byte: process (byte_ready_p_i,index_offset_i,byte_i)
begin
if ((byte_ready_p_i='1') and (add_offset_i = c_CTRL_BYTE_INDEX)) then
if ((byte_ready_p_i='1') and (index_offset_i = c_CTRL_BYTE_INDEX)) then
if byte_i = c_ID_DAT_CTRL_BYTE then --** has to be rp!!
s_rp_dat_control_byte_ok <= '1';
......@@ -224,13 +224,13 @@ end process;
--! Note: in stand-alone mode nanoFIP does not handdle the var2 broadcast variable.
Bytes_Consumption: process (var_i, add_offset_i, slone_i, byte_ready_p_i)
Bytes_Consumption: process (var_i, index_offset_i, slone_i, byte_ready_p_i)
begin
if s_rp_dat_control_byte_ok = '1' then -- only if the rp_dat.control byte is correct the
-- process continues with the bytes' consumption
s_addr <= std_logic_vector(unsigned(add_offset_i)+s_base_addr);-- address in memory
s_addr <= std_logic_vector(unsigned(index_offset_i)+s_base_addr);-- address in memory
-- of the byte to be
-- written
case var_i is
......@@ -258,11 +258,11 @@ Bytes_Consumption: process (var_i, add_offset_i, slone_i, byte_ready_p_i)
s_write_byte_to_mem_p <= '0';
if add_offset_i = c_1st_byte_addr then -- 1st byte to be transferred
if index_offset_i = c_1st_byte_addr then -- 1st byte to be transferred
s_slone_write_byte_p(0) <= byte_ready_p_i ;
end if;
if add_offset_i = c_2nd_byte_addr then -- 2nd byte to be transferred
if index_offset_i = c_2nd_byte_addr then -- 2nd byte to be transferred
s_slone_write_byte_p(1) <= byte_ready_p_i ;
end if;
end if;
......@@ -299,14 +299,14 @@ Bytes_Consumption: process (var_i, add_offset_i, slone_i, byte_ready_p_i)
s_slone_write_byte_p <= (others => '0');
s_base_addr <= c_VARS_ARRAY(c_RESET_VAR_INDEX).base_add;-- base addr info from the wf_package
if ((byte_ready_p_i = '1')and(add_offset_i = c_1st_byte_addr)) then -- 1st byte
if ((byte_ready_p_i = '1')and(index_offset_i = c_1st_byte_addr)) then -- 1st byte
if byte_i = subs_i then
reset_nFIP_and_FD_o <= '1'; -- reset_nFIP_and_FD_o stays asserted until
end if; -- the end of this rp_dat frame
elsif ((byte_ready_p_i='1')and(add_offset_i=c_2nd_byte_addr)) then -- 2nd byte
elsif ((byte_ready_p_i='1')and(index_offset_i=c_2nd_byte_addr)) then -- 2nd byte
if byte_i = subs_i then
reset_RSTON_o <= '1'; -- reset_RSTON_o stays asserted until
......
wf_dec_m_ids.vhd
View file @ 622c4116
......@@ -98,10 +98,10 @@ end entity wf_dec_m_ids;
architecture rtl of wf_dec_m_ids is
signal s_c, s_c_n : unsigned(8 downto 0);
signal s_load_val : std_logic;
signal s_c, s_c_n : unsigned(8 downto 0);
signal s_m_even, s_m_odd : std_logic_vector(3 downto 0);
signal s_c_even, s_c_odd : std_logic_vector(3 downto 0);
signal s_load_val : std_logic;
--=================================================================================================
......@@ -116,22 +116,31 @@ begin
begin
if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then
s_m_even <= (others => '0');
s_c_even <= (others => '0');
s_c <= to_unsigned(0, s_c'length);
m_id_dec_o <= (others => '0');
c_id_dec_o <= (others => '0');
s_m_even <= (others => '0');
s_m_odd <= (others => '0');
s_c_odd <= (others => '0');
s_c_even <= (others => '0');
s_c <= (others => '0');
else
s_m_odd <= m_id_i;
s_m_even <= s_m_odd;
s_c_odd <= c_id_i;
s_m_even <= s_m_odd;
s_c_even <= s_c_odd;
s_c <= s_c_n;
if s_load_val = '1' then
for I in 0 to 3 loop
m_id_dec_o(I*2) <= s_m_even(I);
m_id_dec_o(I*2) <= s_m_even(I);
m_id_dec_o(I*2+1) <= s_m_odd(I);
c_id_dec_o(I*2) <= s_c_even(I);
c_id_dec_o(I*2) <= s_c_even(I);
c_id_dec_o(I*2+1) <= s_c_odd(I);
end loop;
end if;
......@@ -139,7 +148,7 @@ begin
end if;
end process;
s_id_o <= std_logic_vector(s_c((s_c'left - 1) downto (s_c'left - 2)));
s_id_o <= std_logic_vector(s_c((s_c'left - 1) downto (s_c'left - 2))); -- 2 msb of s_c
end architecture rtl;
......
wf_engine_control.vhd
View file @ 622c4116
......@@ -108,7 +108,6 @@ entity wf_engine_control is
last_byte_p_o : out std_logic;
start_produce_p_o : out std_logic;
var_o : out t_var;
append_status_o : out std_logic;
add_offset_o : out std_logic_vector(6 downto 0);
data_length_o : out std_logic_vector(6 downto 0);
consume_byte_p_o : out std_logic
......@@ -137,7 +136,7 @@ architecture rtl of wf_engine_control is
signal s_start_produce_p, s_start_produce_p_d1 : std_logic;
signal s_respon_silen_c_is_zero, s_broadcast_var : std_logic;
signal s_inc_bytes_c, s_reset_bytes_c, s_last_byte_p : std_logic;
signal data_length_match, s_byte_ready_p, s_append_status : std_logic;
signal s_data_length_match, s_byte_ready_p : std_logic;
signal s_p3_length_decoded, s_data_length : unsigned(6 downto 0);
signal s_bytes_c : unsigned(7 downto 0);
signal s_respon_silen_c, s_counter_top: signed(16 downto 0);
......@@ -268,7 +267,7 @@ begin
s_produce_or_consume, s_start_produce_p_d1,
request_byte_p_i, s_respon_silen_c_is_zero,
byte_ready_p_i,s_response_time, s_silence_time,
data_length_match)
s_data_length_match)
begin
case control_st is
......@@ -394,10 +393,10 @@ begin
when produce =>
s_last_byte_p <= data_length_match and request_byte_p_i;
s_last_byte_p <= s_data_length_match and request_byte_p_i;
s_byte_ready_p <= request_byte_p_i or s_start_produce_p_d1;
s_inc_bytes_c <= request_byte_p_i;
s_reset_id_dat <= data_length_match and request_byte_p_i;
s_reset_id_dat <= s_data_length_match and request_byte_p_i;
add_offset_o <= std_logic_vector(resize(s_bytes_c, add_offset_o'length));
s_counter_reset <= '0';
......@@ -497,39 +496,66 @@ begin
---------------------------------------------------------------------------------------------------
--!@brief:Combinatorial process data_length_calcul_produce: calculation of the total amount of data
--! bytes that have to be transferreed when a variable is produced, including the rp_dat.Control as
--! well as the rp_dat.Data.mps and rp_dat.Data.nanoFIPstatus bytes. In the case of presence and
--! identification variables, the data length is predefined in the wf_package.
--! well as the rp_dat.Data.mps and rp_dat.Data.nanoFIPstatus bytes. In the case of the presence
--! and the identification variables, the data length is predefined in the wf_package.
--! In the case of a var_3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation
data_length_calcul_produce: process ( s_var, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i )
variable v_nostat : std_logic_vector(1 downto 0);
begin
s_append_status <= not nostat_i;
s_data_length <= to_unsigned (0, s_data_length'length);
s_p3_length_decoded <= to_unsigned (c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i))),
s_p3_length_decoded'length);
s_data_length <= (others => '0');
s_p3_length_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i)));
case s_var is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package)
when presence_var =>
s_data_length<=to_unsigned(c_VARS_ARRAY(c_PRESENCE_VAR_INDEX).array_length-1,s_data_length'length);
s_data_length<=to_unsigned(c_VARS_ARRAY(c_PRESENCE_VAR_INDEX).array_length,s_data_length'length);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package)
when identif_var =>
s_data_length<=to_unsigned(c_VARS_ARRAY(c_IDENTIF_VAR_INDEX).array_length-1,s_data_length'length);
s_data_length<=to_unsigned(c_VARS_ARRAY(c_IDENTIF_VAR_INDEX).array_length,s_data_length'length);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- data length calculation according to the operational mode (memory or stand-alone)
-- in slone mode 2 bytes of "pure" data are produced
-- to these there should be added: 1 byte rp_dat.Control
-- 1 byte MPS
-- optionally 1 byte nFIP status
-- in memory mode the signal "s_p3_length_decoded" indicates the amount of "pure" data
-- to these, there should be added 1 byte rp_dat.Control
-- 1 byte PDU
-- 1 byte Length
-- 1 byte MPS
-- optionally 1 byte nFIP status
when var_3 =>
if slone_i = '1' then
if s_append_status = '0' then
s_data_length <= to_unsigned(3,s_data_length'length); -- counting starts from 0 (4 bytes) -- control byte + 2 bytes data + mps
if nostat_i = '1' then
s_data_length <= "0000011"; -- 4 bytes (counting starts from 0)
else
s_data_length <= to_unsigned(4,s_data_length'length); -- counting starts from 0 (5 bytes) -- control byte + 2 bytes data + mos + nFIP status
s_data_length <= "0000100"; -- 5 bytes (counting starts from 0)
end if;
else
if s_append_status = '1' then
s_data_length <= s_p3_length_decoded + 4; -- control byte + pdu + length + data bytes + nFIP status + mps (bytes counting starts from 0)
if nostat_i = '0' then
s_data_length <= s_p3_length_decoded + 4; -- (bytes counting starts from 0)
else
s_data_length <= s_p3_length_decoded + 3; -- control byte + pdu + length + data bytes + mps (bytes counting starts from 0)
s_data_length <= s_p3_length_decoded + 3; -- (bytes counting starts from 0)
end if;
end if;
......@@ -545,8 +571,7 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- output signals that have been also used in the process
append_status_o <= s_append_status;
data_length_o <= std_logic_vector(s_data_length); -- control byte+data bytes+nanoFIP status+mps status+pdu+data length (counting starts from 0)
data_length_o <= std_logic_vector(s_data_length);
---------------------------------------------------------------------------------------------------
......@@ -566,8 +591,8 @@ begin
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- when s_data_length bytes have been counted, the signal data_length_match is activated
data_length_match <= '1' when s_bytes_c = s_data_length else '0';
-- when s_data_length bytes have been counted, the signal s_data_length_match is activated
s_data_length_match <= '1' when s_bytes_c = s_data_length else '0';
---------------------------------------------------------------------------------------------------
-- retrieval of response and silence times information (in equivalent number of uclk ticks) from
......
wf_package.vhd
View file @ 622c4116
......@@ -23,26 +23,26 @@ package wf_package is
constant C_QUARTZ_PERIOD : real := 24.8;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- constants regarding the manchester coding
constant VP : std_logic_vector(1 downto 0) := "11";
constant VN : std_logic_vector(1 downto 0) := "00";
constant ONE : std_logic_vector(1 downto 0) := "10";
constant ZERO : std_logic_vector(1 downto 0) := "01";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- constants regarding the ID_DAT and RP_DAT frame structure
constant PREAMBLE : std_logic_vector(15 downto 0) := ONE&ZERO&ONE&ZERO&ONE&ZERO&ONE&ZERO;
constant FRAME_START : std_logic_vector(15 downto 0) := ONE&VP&VN&ONE&ZERO&VN&VP&ZERO;
constant FRAME_END : std_logic_vector(15 downto 0) := ONE&VP&VN&VP&VN&ONE&ZERO&ONE;
constant FSS : std_logic_vector(31 downto 0) := PREAMBLE&FRAME_START;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- constants concerning the control byte of an ID_DAT and RP_DAT frames
constant c_ID_DAT_CTRL_BYTE : std_logic_vector(7 downto 0) := "00000011";
constant c_RP_DAT_CTRL_BYTE : std_logic_vector(7 downto 0) := "00000010";
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--constants concerning the nanoFIP status bits
constant c_U_CACER_INDEX : integer := 2;
constant c_U_PACER_INDEX : integer := 3;
......@@ -51,13 +51,13 @@ package wf_package is
constant c_T_TXER_INDEX : integer := 6;
constant c_T_WDER_INDEX : integer := 7;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--constants concerning the MPS status bits
constant c_REFRESHMENT_INDEX : integer := 0;
constant c_SIGNIFICANCE_INDEX : integer := 2;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- construction of a table with the timeout and silence times for each bit rate
-- the table contains the number of uclk tick corresponding to the respone/ silence times
type t_timeouts is
......@@ -89,18 +89,19 @@ package wf_package is
silence => integer(5160000.0/C_QUARTZ_PERIOD))
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- construction of a table for the P3_LGTH[2:0] settings
type t_integer_array is array (natural range <>) of integer;
constant c_P3_LGTH_TABLE : t_integer_array(0 to 7) :=
(0 => 2,
1 => 8,
2 => 16,
3 => 32,
4 => 64,
5 => 124,
others => 0);
type t_unsigned_array is array (natural range <>) of unsigned(6 downto 0);
constant c_P3_LGTH_TABLE : t_unsigned_array(0 to 7) :=
(0 => "0000010", -- 2 bytes
1 => "0001000", -- 8 bytes
2 => "0010000", -- 16 bytes
3 => "0100000", -- 32 bytes
4 => "1000000", -- 64 bytes
5 => "1111100", -- 124 bytes
others => "0000000" -- reserved
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -317,7 +318,7 @@ package wf_package is
wb_adr_i : in std_logic_vector (9 downto 0);
wb_stb_p_i : in std_logic;
byte_ready_p_i : in std_logic;
add_offset_i : in std_logic_vector(6 downto 0);
index_offset_i : in std_logic_vector(6 downto 0);
var_i : in t_var;
byte_i : in std_logic_vector(7 downto 0);
......@@ -349,8 +350,7 @@ package wf_package is
mps_byte_i : in std_logic_vector(7 downto 0);
var_i : in t_var;
data_length_i : in std_logic_vector(6 downto 0);
append_status_i : in std_logic;
add_offset_i : in std_logic_vector(6 downto 0);
index_offset_i : in std_logic_vector(6 downto 0);
sending_mps_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0);
......@@ -384,7 +384,6 @@ package wf_package is
var2_rdy_o: out std_logic;
var3_rdy_o: out std_logic;
var_o : out t_var;
append_status_o : out std_logic;
consume_byte_p_o : out std_logic;
add_offset_o : out std_logic_vector(6 downto 0);
data_length_o : out std_logic_vector(6 downto 0)
......
wf_produced_vars.vhd
View file @ 622c4116
This diff is collapsed.
wf_rx.vhd
View file @ 622c4116
......@@ -136,7 +136,7 @@ architecture rtl of wf_rx is
signal s_frame_start_bit, s_queue_bit : std_logic;
signal s_frame_start_correct_bit, s_frame_start_wrong_bit, s_frame_start_last_bit : std_logic;
signal s_frame_start_wrong_bit, s_frame_start_last_bit : std_logic;
signal s_frame_end_detected_p, s_frame_end_detection, s_frame_end_wrong_bit : std_logic;
signal s_violation_check, s_code_violation : std_logic;
......@@ -569,6 +569,8 @@ end process;
if nFIP_rst_i = '1' then
byte_ready_p_o <= '0';
s_violation_check <='0';
s_sample_bit_p_d1 <= '0';
s_sample_bit_p_d2 <= '0';
s_rx_data_filtered_d <='0';
else
......
wf_tx.vhd
View file @ 622c4116
......@@ -55,7 +55,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! \n\n<b>Last changes:</b>\n
--! -> v0.02 PAS Entity Ports added, start of architecture content
--! -> v0.03 EG timing changes; tx_clk_p_buff_i got 1 more bit
--! briefly add_offset_i needed to arrive 1 clock tick earlier
--! briefly index_offset_i needed to arrive 1 clock tick earlier
--
---------------------------------------------------------------------------------------------------
--
......@@ -73,25 +73,27 @@ entity wf_tx is
port (
-- INPUTS
-- user interface general signals
uclk_i : in std_logic; --! 40MHz clock
uclk_i : in std_logic; --! 40MHz clock
-- Signal from the reset_logic unit
nFIP_rst_i : in std_logic; --! internal reset
nFIP_rst_i : in std_logic; --! internal reset
-- Signals from the wf_engine_control
start_produce_p_i : in std_logic; --! indication that wf_engine_control is in prod_watchdog state
-- a correct id_dat asking for a produced var has been
-- received and ............
byte_ready_p_i : in std_logic; --! indication that a byte is ready to be delivered
last_byte_p_i : in std_logic; --! indication that it is the last byte of data
-- crc bytes follow
start_produce_p_i : in std_logic; --! indication that wf_engine_control is in prod_watchdog state
-- a correct id_dat asking for a produced var has been
-- received and ............
byte_ready_p_i : in std_logic; --! indication that a byte is ready to be delivered
last_byte_p_i : in std_logic; --! indication that it is the last byte of data
-- crc bytes follow
-- Signals from the wf_produced_vars
byte_i : in std_logic_vector(7 downto 0); --! byte of data to be delivered
byte_i : in std_logic_vector(7 downto 0);
--! data byte to be delivered
-- Signal from the wf_rx_tx_osc
tx_clk_p_buff_i : in std_logic_vector(C_CLKFCDLENTGTH-1 downto 0);--!clk for transmission synch
-- ronization
tx_clk_p_buff_i : in std_logic_vector(C_CLKFCDLENTGTH-1 downto 0);
--! clk for transmission synchronization
-- OUTPUTS
......@@ -99,8 +101,8 @@ entity wf_tx is
request_byte_p_o : out std_logic;
-- nanoFIP output signals
tx_data_o : out std_logic;
tx_enable_o : out std_logic
tx_data_o : out std_logic; --! transmitter serial data
tx_enable_o : out std_logic --! transmitter enable
);
end entity wf_tx;
......@@ -121,12 +123,12 @@ architecture rtl of wf_tx is
signal s_d_to_crc_rdy_p : std_logic;
signal s_data_bit, s_tx_enable : std_logic;
signal s_load_pointer, s_decr_pointer : std_logic;
signal s_nx_data_to_crc, s_tx_finished_p : std_logic;
signal s_tx_finished_p : std_logic;
signal s_pointer_is_zero, s_pointer_is_one : std_logic;
signal s_pointer, s_top_pointer : unsigned(4 downto 0);
signal s_byte : std_logic_vector(7 downto 0);
signal s_manchester_crc : std_logic_vector(31 downto 0);
signal s_crc, s_manchester_byte : std_logic_vector(15 downto 0);
signal s_pointer, s_top_pointer : unsigned(4 downto 0);
--=================================================================================================
......@@ -140,31 +142,29 @@ begin
generic map(
c_GENERATOR_POLY_length => 16)
port map(
uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
start_crc_p_i => s_start_crc_p,
data_bit_ready_p_i => s_d_to_crc_rdy_p,
data_bit_i => s_nx_data_to_crc,
crc_o => s_crc,
crc_ok_p => open
uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i,
start_crc_p_i => s_start_crc_p,
data_bit_ready_p_i => s_d_to_crc_rdy_p,
data_bit_i => s_data_bit,
crc_o => s_crc,
crc_ok_p => open
);
s_nx_data_to_crc <= s_data_bit;
---------------------------------------------------------------------------------------------------
--!@brief Transmitter's state machine: the state machine is divided in three parts (a clocked
--! process to store the current state, a combinatorial process to manage state transitions and
--! finally a combinatorial process to manage the output signals), which are the 3 processes that
--! follow. The unit,
--! follow.
--! The signal tx_clk_p_buff_i is used for the synchronization of all the transitions and actions
--! in the unit.
--! The signal tx_clk_p_buff_i is used for the synchronization of the transitions of the state
--! machine as well as the actions on the output signals.
-- The following draft drawing shows the transitions of the signal tx_clk_p_buff_i with respect to
-- the transmission clock tx_clk (tx_clk is not used in this unit, but it may be used by the
-- receiver for the decoding and synchronization of the incoming data)
-- the line driver half bit clock tx_clk.
-- tx_clk: __________|----------------|________________|----------------|_______________
-- tx_clk_p_buff (2): |0|0|0|1 |0|0|0|1
-- tx_clk_p_buff (2): |0|0|1|0 |0|0|1|0
-- tx_clk_p_buff (1): |0|1|0|0 |0|1|0|0
-- tx_clk_p_buff (0): |1|0|0|0 |1|0|0|0
......
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