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nanoFIP - Gateware
Commit 7da7370b authored by egousiou's avatar egousiou
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wf_engine_control small issue with FES detection solved 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@124 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 2e4bdf05
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Showing with 153 additions and 160 deletions
nanofip.vhd
View file @ 7da7370b
...@@ -432,7 +432,7 @@ begin ...@@ -432,7 +432,7 @@ begin
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nfip_rst_i => s_rst, nfip_rst_i => s_rst,
rxd_edge_i => s_fd_rxd_edge_p, rxd_edge_p_i => s_fd_rxd_edge_p,
rst_rx_osc_i => s_rst_rx_osc, rst_rx_osc_i => s_rst_rx_osc,
rate_i => s_rate_synch, rate_i => s_rate_synch,
--------------------------------------------------------- ---------------------------------------------------------
......
wf_bits_to_txd.vhd
View file @ 7da7370b
...@@ -126,7 +126,7 @@ architecture rtl of WF_bits_to_txd is ...@@ -126,7 +126,7 @@ architecture rtl of WF_bits_to_txd is
begin begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! @brief Synchronous process Bits_Delivery: managment of nanoFIP output signal FD_TXD by --! @brief Synchronous process Bits_Delivery: handling of nanoFIP output signal FD_TXD by
--! placing bits of data according to the state of WF_tx_serializer's state machine (sending_fss, --! placing bits of data according to the state of WF_tx_serializer's state machine (sending_fss,
--! sending_data, sending_crc, sending_fes, stop_transmission) and to the counter txd_bit_index. --! sending_data, sending_crc, sending_fes, stop_transmission) and to the counter txd_bit_index.
--! The delivery is synchronised by the tx_clk_p_buff(1) signal. --! The delivery is synchronised by the tx_clk_p_buff(1) signal.
...@@ -151,7 +151,7 @@ begin ...@@ -151,7 +151,7 @@ begin
txd_o <= crc_byte_manch_i (to_integer (txd_bit_index_i)); -- CRC: 2 bytes long txd_o <= crc_byte_manch_i (to_integer (txd_bit_index_i)); -- CRC: 2 bytes long
elsif sending_fes_i = '1' then elsif sending_fes_i = '1' then
txd_o <= c_FES(to_integer (resize(txd_bit_index_i,4))); -- FES: 1 byte txd_o <= c_FES(to_integer (resize(txd_bit_index_i,4))); -- FES: 1 byte
else else
txd_o <= '0'; txd_o <= '0';
...@@ -180,12 +180,12 @@ begin ...@@ -180,12 +180,12 @@ begin
(sending_crc_i = '1') or (sending_fes_i = '1') or (stop_transmission_i = '1')) then (sending_crc_i = '1') or (sending_fes_i = '1') or (stop_transmission_i = '1')) then
if tx_clk_p_i = '1' then -- in order to synchronise the if tx_clk_p_i = '1' then -- in order to synchronise the
tx_enable_o <= '1'; -- activation of tx_enabble with the tx_enable_o <= '1'; -- activation of tx_enable with the
end if; -- the delivery of the 1st FSS bit end if; -- the delivery of the 1st FSS bit
-- txd (FSS) :________|-----|___________|-------- -- FD_TXD (FSS) :________|-----|___________|--------
-- tx_clk_p_buff(1):______|-|___|-|___|-|___|-|___|-|__ -- tx_clk_p_buff(1):______|-|___|-|___|-|___|-|___|-|__
-- sending_FSS :___|------------------------------- -- sending_FSS :___|-------------------------------
-- tx_enable :________|-------------------------- -- FD_TXENA :________|--------------------------
else else
tx_enable_o <= '0'; tx_enable_o <= '0';
end if; end if;
......
wf_cons_bytes_processor.vhd
View file @ 7da7370b
...@@ -33,21 +33,22 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -33,21 +33,22 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! --!
--! o If the consumed variable had been a var_1 or a var_2: --! o If the consumed variable had been a var_1 or a var_2:
--! --!
--! o If the operation is in memory mode : the unit is registering the pure-data --! o If the operation is in memory mode : the unit is registering the
--! bytes along with the PDU_TYPE, Length and MPS bytes in the Consumed memories --! application-data bytes along with the PDU_TYPE, Length and MPS bytes in the
--! Consumed memories
--! --!
--! o If the operation is in standalone mode: the unit is transferring the 2 --! o If the operation is in standalone mode: the unit is transferring the 2 appli-
--! pure-data bytes to the "nanoFIP User Interface, NON_WISHBONE" data bus DAT_O. --! cation-data bytes to the "nanoFIP User Interface, NON_WISHBONE" data bus DAT_O
--! --!
--! o If the consumed variable had been a var_rst, the 2 pure-data bytes are just --! o If the consumed variable had been a var_rst, the 2 application-data bytes are just
--! identified and sent to the WF_reset_unit. --! identified and sent to the WF_reset_unit.
--! --!
--! ------------------------------------------------------------------------------------ --! ------------------------------------------------------------------------------------
--! Reminder: --! Reminder:
--! --!
--! Consumed RP_DAT frame structure : --! Consumed RP_DAT frame structure :
--! ___________ ______ _______ ________ ________________ _______ ___________ _______ --! ___________ ______ _______ ________ __________________ _______ ___________ _______
--! |____FSS____|_Ctrl_||__PDU__|__LGTH__|__..PureData..__|__MPS__||____FCS____|__FES__| --! |____FSS____|_Ctrl_||__PDU__|__LGTH__|__..ApplicData..__|__MPS__||____FCS____|__FES__|
--! --!
--! |-------LGTH bytes-------| --! |-------LGTH bytes-------|
--! |--------write to Consumed memory---------| --! |--------write to Consumed memory---------|
...@@ -114,7 +115,7 @@ entity WF_cons_bytes_processor is ...@@ -114,7 +115,7 @@ entity WF_cons_bytes_processor is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk) -- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode (active high) slone_i : in std_logic; --! stand-alone mode (active high)
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
......
wf_cons_bytes_to_dato.vhd
View file @ 7da7370b
...@@ -28,8 +28,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -28,8 +28,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- --
-- --
--! @brief In stand-alone mode, after the reception of a consumed or consumed broadcast --! @brief In stand-alone mode, after the reception of a consumed or consumed broadcast
--! variable, the unit is responsible for transering the two pure-data bytes to the --! variable, the unit is responsible for transering the two application-data bytes to
--! 2-bytes long bus DAT_O. --! the 2-bytes long bus DAT_O.
--! The bytes are put in the bus one by one as they arrive, as the signal --! The bytes are put in the bus one by one as they arrive, as the signal
--! transfer_byte_p_i indicates. --! transfer_byte_p_i indicates.
--! --!
...@@ -88,7 +88,7 @@ entity WF_cons_bytes_to_dato is ...@@ -88,7 +88,7 @@ entity WF_cons_bytes_to_dato is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk) -- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit unit -- Signal from the WF_reset_unit unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
...@@ -134,14 +134,14 @@ Data_Transfer_To_Dat_o: process (uclk_i) ...@@ -134,14 +134,14 @@ Data_Transfer_To_Dat_o: process (uclk_i)
if transfer_byte_p_i(0) = '1' then -- the 1st byte is transfered in the lsb of the bus if transfer_byte_p_i(0) = '1' then -- the 1st byte is transfered in the lsb of the bus
slone_data_o(7 downto 0) <= byte_i; -- it stays there until a new cons. var arrives slone_data_o(7 downto 0) <= byte_i; -- it stays there until a new cons. var arrives
-- (or until a reset!)
end if; end if;
if transfer_byte_p_i(1) = '1' then -- the 2nd byte is transfered in the msb of the bus if transfer_byte_p_i(1) = '1' then -- the 2nd byte is transfered in the msb of the bus
slone_data_o(15 downto 8) <= byte_i; -- it stays there until a new cons. var arrives slone_data_o(15 downto 8) <= byte_i; -- it stays there until a new cons. var arrives
-- (or until a reset!)
end if; end if;
......
wf_cons_outcome.vhd
View file @ 7da7370b
...@@ -90,7 +90,7 @@ entity WF_cons_outcome is ...@@ -90,7 +90,7 @@ entity WF_cons_outcome is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk) -- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40 MHz clock
slone_i : in std_logic; --! stand-alone mode slone_i : in std_logic; --! stand-alone mode
-- nanoFIP WorldFIP Settings (synchronized with uclk) -- nanoFIP WorldFIP Settings (synchronized with uclk)
......
wf_decr_counter.vhd
View file @ 7da7370b
...@@ -72,7 +72,7 @@ entity WF_decr_counter is ...@@ -72,7 +72,7 @@ entity WF_decr_counter is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface general signal -- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
......
wf_engine_control.vhd
View file @ 7da7370b
...@@ -30,9 +30,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -30,9 +30,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! @brief The WF_engine_control is following the reception of an incoming ID_DAT frame and --! @brief The WF_engine_control is following the reception of an incoming ID_DAT frame and
--! o identifies the variable to be treated --! o identifies the variable to be treated
--! o signals accordingly the WF_production and WF_consumption units. --! o signals accordingly the WF_production and WF_consumption units.
--! Its main output var_i is crucial for the units WF_cons_bytes_processor and --! During the production or consumption the unit is keeping track of the amounts of
--! WF_prod_bytes_retriever as it defines the structure of the frames that are expected --! produced and consumed bytes.
--! to arrive or to be produced.
--! --!
--! ------------------------------------------------------------------------------------ --! ------------------------------------------------------------------------------------
--! Reminder --! Reminder
...@@ -49,7 +48,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -49,7 +48,7 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! --!
--! Consumed RP_DAT frame structure : --! Consumed RP_DAT frame structure :
--! ___________ ______ _______ ______ _________________________ _______ ___________ _______ --! ___________ ______ _______ ______ _________________________ _______ ___________ _______
--! |____FSS____|_Ctrl_||__PDU__|_LGTH_|______..Pure-Data..______|__MPS__||____FCS____|__FES__| --! |____FSS____|_Ctrl_||__PDU__|_LGTH_|_____..Applic-Data.._____|__MPS__||____FCS____|__FES__|
--! --!
--! --!
--! Turnaround time : Time between the end of the reception of an ID_DAT frame --! Turnaround time : Time between the end of the reception of an ID_DAT frame
...@@ -90,15 +89,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -90,15 +89,17 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! PDU,length,ctrl bytes of RP_DAT checked bf VAR1_RDY/ var_2_rdy assertion; --! PDU,length,ctrl bytes of RP_DAT checked bf VAR1_RDY/ var_2_rdy assertion;
--! if ID_DAT>8 bytes or RP_DAT>134 (bf reception of a FES) go to idle; --! if ID_DAT>8 bytes or RP_DAT>134 (bf reception of a FES) go to idle;
--! state consume_wait_FSS, for the correct use of the silence time(time --! state consume_wait_FSS, for the correct use of the silence time(time
--! stops counting when an RP_DAT frame has started) --! stops counting when an RP_DAT frame has started)
--! --! 12/2010 v0.03 EG state machine rewritten mealy style; removed check on slone mode
--! 12/2010 v0.02 EG removed check on slone mode for #bytes>4; --! for #bytes>4; in slone no broadcast
--! in slone no broadcast --! 01/2011 v0.04 EG signals named according to their origin; signals var_rdy (1,2,3),
--! 01/2011 v0.03 EG signals named according to their origin; signals removed.... --! assert_rston_p_o,rst_nfip_and_fd_p_o, nFIP status bits and
--! rx_byte_ready_p_o removedl cleaning-up+commenting
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo -> add FES detection --! @todo -> add an extra time counter (on top of the more complicated bytes counters) that after
--! 134*8 transmission periods can reset tx and rx
--! --!
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -152,7 +153,9 @@ entity WF_engine_control is ...@@ -152,7 +153,9 @@ entity WF_engine_control is
rx_fss_crc_fes_manch_ok_p_i: in std_logic; --! indication of a frame (ID_DAT or RP_DAT) with rx_fss_crc_fes_manch_ok_p_i: in std_logic; --! indication of a frame (ID_DAT or RP_DAT) with
--! correct FSS, FES, CRC and manch. encoding --! correct FSS, FES, CRC and manch. encoding
rx_crc_wrong_p_i : in std_logic; --! indication of a frame with a wrong CRC (pulse after FES arrival) rx_crc_wrong_p_i : in std_logic; --! indication of a frame with a wrong CRC
-- pulse arrives after the FES detection
rx_fss_received_p_i : in std_logic; --! pulse after a correct FSS detection (ID/ RP_DAT) rx_fss_received_p_i : in std_logic; --! pulse after a correct FSS detection (ID/ RP_DAT)
...@@ -164,7 +167,7 @@ entity WF_engine_control is ...@@ -164,7 +167,7 @@ entity WF_engine_control is
-- Signals to the WF_production -- Signals to the WF_production
-- Signal to the WF_tx_serializer unit -- Signal to the WF_tx_serializer unit
tx_byte_request_accept_p_o : out std_logic;--! tx_byte_request_accept_p_o : out std_logic;--! answer to tx_byte_request_p_i
tx_last_byte_p_o : out std_logic;--! indication that it is the last data-byte tx_last_byte_p_o : out std_logic;--! indication that it is the last data-byte
tx_start_prod_p_o : out std_logic;--! launches the transmitters's FSM tx_start_prod_p_o : out std_logic;--! launches the transmitters's FSM
...@@ -185,15 +188,15 @@ entity WF_engine_control is ...@@ -185,15 +188,15 @@ entity WF_engine_control is
-- Signals to the WF_production & WF_consumption -- Signals to the WF_production & WF_consumption
-- Signal to the WF_cons_bytes_processor, WF_prod_bytes_retriever -- Signal to the WF_cons_bytes_processor, WF_prod_bytes_retriever
prod_cons_byte_index_o : out std_logic_vector (7 downto 0); prod_cons_byte_index_o : out std_logic_vector (7 downto 0); --! index of the byte being
--! consumed/ produced
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the WF_production, WF_consumption, WF_reset_unit -- Signals to the WF_production, WF_consumption, WF_reset_unit
-- Signal to the WF_cons_bytes_processor, WF_prod_bytes_retriever, WF_reset_unit -- Signal to the WF_cons_bytes_processor, WF_prod_bytes_retriever, WF_reset_unit
var_o : out t_var --! variable received by a valid ID_DAT frame var_o : out t_var --! variable received by a valid ID_DAT frame
--! that concerns this station --! that concerns this station
); );
end entity WF_engine_control; end entity WF_engine_control;
...@@ -210,8 +213,8 @@ architecture rtl of WF_engine_control is ...@@ -210,8 +213,8 @@ architecture rtl of WF_engine_control is
consume, consume_wait_FSS, consume, consume_wait_FSS,
produce_wait_turnar_time, produce); produce_wait_turnar_time, produce);
signal control_st, nx_control_st : control_st_t; signal control_st, nx_control_st :control_st_t;
signal s_var_aux, s_var, s_var_id : t_var; signal s_var_aux, s_var, s_var_id : t_var;
signal s_time_c_is_zero, s_broadcast_var, s_tx_start_prod_p, s_inc_rx_bytes_counter : std_logic; signal s_time_c_is_zero, s_broadcast_var, s_tx_start_prod_p, s_inc_rx_bytes_counter : std_logic;
signal s_producing, s_consuming, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic; signal s_producing, s_consuming, s_rst_prod_bytes_counter, s_inc_prod_bytes_counter : std_logic;
...@@ -241,12 +244,12 @@ begin ...@@ -241,12 +244,12 @@ begin
--! The FSM starts in idle and expects from the WF_rx_deserializer to indicate the arrival of the --! The FSM starts in idle and expects from the WF_rx_deserializer to indicate the arrival of the
--! FSS of an ID_DAT. It continues by checking one by one the bytes of the ID_DAT as they arrive: --! FSS of an ID_DAT. It continues by checking one by one the bytes of the ID_DAT as they arrive:
--! if the Control byte is the nominal, --! o if the Control byte is the nominal,
--! if the variable byte corresponds to a defined variable, --! o if the variable byte corresponds to a defined variable,
--! if the subscriber byte matches the station's address, or if the variable is a broadcast --! o if the subscriber byte matches the station's address, or if the variable is a broadcast
--! and if the ID_DAT frame has been characterised as a valid one (the WF_rx_deserializer sends --! o and if the ID_DAT frame has been characterised as a valid one (the WF_rx_deserializer sends
--! a dedicated pulse at the end of the FES if the CRC has been correct and there have been no --! a dedicated pulse at the end of the FES if the CRC has been correct and there have been no
--! unexpected manch. code violations throughout the frame). --! unexpected manch. code violations throughout the frame).
--! If the received variable is a produced (var_presence, var_identif, var_3) the FSM stays --! If the received variable is a produced (var_presence, var_identif, var_3) the FSM stays
--! in the "produce_wait_turnar_time" state until the expiration of the turnaround time and then --! in the "produce_wait_turnar_time" state until the expiration of the turnaround time and then
--! jumps to the "produce" state, waiting for the WF_serializer to send its last data-byte; then --! jumps to the "produce" state, waiting for the WF_serializer to send its last data-byte; then
...@@ -350,9 +353,9 @@ begin ...@@ -350,9 +353,9 @@ begin
elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_produce_or_consume = "01") then elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_produce_or_consume = "01") then
nx_control_st <= consume_wait_FSS; -- CRC & FES check ok! station has to consume nx_control_st <= consume_wait_FSS; -- CRC & FES check ok! station has to consume
elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_rx_bytes_c > 2) then -- 3 bytes after the arrival of the subscriber----->2---------------- elsif (rx_fss_crc_fes_manch_ok_p_i = '1') and (s_rx_bytes_c > 2) then
-- 3 bytes after the arrival of the subscriber
nx_control_st <= idle; -- byte, a FES has not been detected nx_control_st <= idle; -- byte, a FES has not been detected
-- s_rx_bytes_c: starts counting at this state
else else
nx_control_st <= id_dat_frame_ok; -- CRC & FES bytes being arriving nx_control_st <= id_dat_frame_ok; -- CRC & FES bytes being arriving
...@@ -567,8 +570,8 @@ begin ...@@ -567,8 +570,8 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of the WF_prod_data_lgth_calc unit that calculates the total amount of --! @brief Instantiation of the WF_prod_data_lgth_calc unit that calculates the total amount of
--! data-bytes that have to be transferred when a variable is produced (including the --! bytes that have to be transferred when a variable is produced (including the RP_DAT.Control,
--! RP_DAT.Control, RP_DAT.Data.MPS_status and RP_DAT.Data.nanoFIP_status bytes). --! RP_DAT.Data.MPS_status and RP_DAT.Data.nanoFIP_status bytes).
Produced_Data_Length_Calculator: WF_prod_data_lgth_calc Produced_Data_Length_Calculator: WF_prod_data_lgth_calc
port map( port map(
...@@ -603,21 +606,6 @@ begin ...@@ -603,21 +606,6 @@ begin
-- when s_prod_data_length bytes have been counted,the signal s_prod_data_length_match is activated -- when s_prod_data_length bytes have been counted,the signal s_prod_data_length_match is activated
s_prod_data_length_match <= '1' when s_prod_bytes_c = unsigned (s_prod_data_length) else '0'; s_prod_data_length_match <= '1' when s_prod_bytes_c = unsigned (s_prod_data_length) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of a WF_incr_counter for the counting of the production time.
Produced_Time_Counter: WF_incr_counter
generic map(g_counter_lgth => 18)
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
reinit_counter_i => s_rst_prod_bytes_counter,
incr_counter_i => '1',
-------------------------------------------------------
counter_o => open,
counter_is_full_o => s_prod_time_over
-------------------------------------------------------
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--! @brief Instantiation of a WF_incr_counter for the counting of the number of bytes that are --! @brief Instantiation of a WF_incr_counter for the counting of the number of bytes that are
...@@ -903,7 +891,7 @@ begin ...@@ -903,7 +891,7 @@ begin
-- bytes and consumed RP_DAT > 130 bytes) -- bytes and consumed RP_DAT > 130 bytes)
rst_rx_unit_p_o <= s_idle_state and rx_byte_ready_p_i; rst_rx_unit_p_o <= s_idle_state and rx_byte_ready_p_i;
-- Production starts after the expiration of the silence time -- Production starts after the expiration of the turnaround time
tx_start_prod_p_o <= s_tx_start_prod_p; tx_start_prod_p_o <= s_tx_start_prod_p;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
......
wf_incr_counter.vhd
View file @ 7da7370b
...@@ -66,7 +66,7 @@ entity WF_incr_counter is ...@@ -66,7 +66,7 @@ entity WF_incr_counter is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface general signal -- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
......
wf_inputs_synchronizer.vhd
View file @ 7da7370b
...@@ -84,7 +84,7 @@ entity WF_inputs_synchronizer is ...@@ -84,7 +84,7 @@ entity WF_inputs_synchronizer is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface, General signals -- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40 MHz clock
nostat_a_i : in std_logic; nostat_a_i : in std_logic;
rstin_a_i : in std_logic; rstin_a_i : in std_logic;
slone_a_i : in std_logic; slone_a_i : in std_logic;
......
wf_manch_code_viol_check.vhd
View file @ 7da7370b
...@@ -90,7 +90,7 @@ entity WF_rx_manch_code_check is ...@@ -90,7 +90,7 @@ entity WF_rx_manch_code_check is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface general signal -- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
......
wf_package.vhd
View file @ 7da7370b
...@@ -184,7 +184,7 @@ package WF_package is ...@@ -184,7 +184,7 @@ package WF_package is
-- Creation of a table with the c_BIT_RATE_UCLK_TICKS info per bit rate -- Creation of a table with the c_BIT_RATE_UCLK_TICKS info per bit rate
type t_uclk_ticks is array (Natural range <>) of unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0); type t_uclk_ticks is array (Natural range <>) of unsigned (C_PERIODS_COUNTER_LENGTH-1 downto 0);
constant c_BIT_RATE_UCLK_TICKS : t_uclk_ticks(3 downto 0):= constant c_BIT_RATE_UCLK_TICKS : t_uclk_ticks (3 downto 0):=
(0 => (c_BIT_RATE_UCLK_TICKS_31_25Kbit), (0 => (c_BIT_RATE_UCLK_TICKS_31_25Kbit),
1 => (c_BIT_RATE_UCLK_TICKS_1_Mbit), 1 => (c_BIT_RATE_UCLK_TICKS_1_Mbit),
2 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit), 2 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit),
...@@ -278,7 +278,6 @@ package WF_package is ...@@ -278,7 +278,6 @@ package WF_package is
response => produce, response => produce,
base_addr => "---------", base_addr => "---------",
array_length => "00001010", -- 11 bytes in total including the Control byte array_length => "00001010", -- 11 bytes in total including the Control byte
-- (counting starts from 0)
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"52", 2 => x"08", byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => x"52", 2 => x"08",
3 => x"01", 4 => x"00", 5 => x"00", 6 => x"ff", 3 => x"01", 4 => x"00", 5 => x"00", 6 => x"ff",
7 => x"ff", 8 => x"00", 9 => x"00", 10 => x"00", 7 => x"ff", 8 => x"00", 9 => x"00", 10 => x"00",
...@@ -290,7 +289,7 @@ package WF_package is ...@@ -290,7 +289,7 @@ package WF_package is
response => produce, response => produce,
base_addr => "100000000", base_addr => "100000000",
array_length => "00000001", -- only the Control and PDU type bytes are array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0) -- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE, byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")), others => x"ff")),
...@@ -300,17 +299,17 @@ package WF_package is ...@@ -300,17 +299,17 @@ package WF_package is
response => consume, response => consume,
base_addr => "000000000", base_addr => "000000000",
array_length => "00000001", -- only the Control and PDU type bytes are array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0) -- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE, byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")), others => x"ff")),
c_VAR_2_INDEX => (var => var_2, c_VAR_2_INDEX => (var => var_2,
hexvalue => x"91", -------------- hexvalue => x"91",
response => consume, response => consume,
base_addr => "010000000", base_addr => "010000000",
array_length => "00000001", -- only the Control and PDU type bytes are array_length => "00000001", -- only the Control and PDU type bytes are
-- predefined (counting starts from 0) -- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE, byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff")), others => x"ff")),
...@@ -318,8 +317,8 @@ package WF_package is ...@@ -318,8 +317,8 @@ package WF_package is
hexvalue => x"e0", hexvalue => x"e0",
response => reset, response => reset,
base_addr => "---------", base_addr => "---------",
array_length => "00000001", -- only the Control byte is predefined array_length => "00000001", -- only the Control and PDU type bytes are
-- (counting starts from 0) -- predefined
byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE, byte_array => (0 => c_RP_DAT_CTRL_BYTE, 1 => c_PROD_CONS_PDU_TYPE_BYTE,
others => x"ff"))); others => x"ff")));
...@@ -450,7 +449,7 @@ end component WF_inputs_synchronizer; ...@@ -450,7 +449,7 @@ end component WF_inputs_synchronizer;
uclk_i : in std_logic; uclk_i : in std_logic;
rate_i : in std_logic_vector (1 downto 0); rate_i : in std_logic_vector (1 downto 0);
nfip_rst_i : in std_logic; nfip_rst_i : in std_logic;
rxd_edge_i : in std_logic; rxd_edge_p_i : in std_logic;
rst_rx_osc_i : in std_logic; rst_rx_osc_i : in std_logic;
------------------------------------------------------------------------- -------------------------------------------------------------------------
rx_manch_clk_p_o : out std_logic; rx_manch_clk_p_o : out std_logic;
......
wf_prod_bytes_retriever.vhd
View file @ 7da7370b
...@@ -130,7 +130,7 @@ entity WF_prod_bytes_retriever is ...@@ -130,7 +130,7 @@ entity WF_prod_bytes_retriever is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk) -- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40 MHz clock
nostat_i : in std_logic; --! if negated, nFIP status is sent nostat_i : in std_logic; --! if negated, nFIP status is sent
slone_i : in std_logic; --! stand-alone mode slone_i : in std_logic; --! stand-alone mode
......
wf_prod_bytes_to_dati.vhd
View file @ 7da7370b
...@@ -82,7 +82,7 @@ entity WF_prod_bytes_from_dati is ...@@ -82,7 +82,7 @@ entity WF_prod_bytes_from_dati is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface, General signals -- nanoFIP User Interface, General signals
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
......
wf_prod_permit.vhd
View file @ 7da7370b
...@@ -80,7 +80,7 @@ entity WF_prod_permit is ...@@ -80,7 +80,7 @@ entity WF_prod_permit is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface, General signals (synchronized with uclk) -- nanoFIP User Interface, General signals (synchronized with uclk)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
......
wf_rx_deserializer.vhd
View file @ 7da7370b
...@@ -58,8 +58,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -58,8 +58,8 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--! Reminder: --! Reminder:
--! --!
--! Consumed RP_DAT frame structure : --! Consumed RP_DAT frame structure :
--! _______ _______ ______ _______ ______ ______________ _______ ___________ _______ --! _______ _______ ______ _______ ______ ________________ _______ ___________ _______
--! |__PRE__|__FSD__|_Ctrl_||__PDU__|_LGTH_|_..PureData.._|__MPS__||____FCS____|__FES__| --! |__PRE__|__FSD__|_Ctrl_||__PDU__|_LGTH_|_..ApplicData.._|__MPS__||____FCS____|__FES__|
--! --!
--! ------------------------------------------------------------------------------------ --! ------------------------------------------------------------------------------------
-- --
...@@ -130,7 +130,7 @@ entity WF_rx_deserializer is ...@@ -130,7 +130,7 @@ entity WF_rx_deserializer is
port ( port (
-- INPUTS -- INPUTS
-- nanoFIP User Interface general signal -- nanoFIP User Interface general signal
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the WF_reset_unit -- Signal from the WF_reset_unit
nfip_rst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
...@@ -201,7 +201,7 @@ architecture rtl of WF_rx_deserializer is ...@@ -201,7 +201,7 @@ architecture rtl of WF_rx_deserializer is
signal s_manch_bit_index, s_manch_bit_index_top : unsigned(3 downto 0); signal s_manch_bit_index, s_manch_bit_index_top : unsigned(3 downto 0);
signal s_byte : std_logic_vector (7 downto 0); signal s_byte : std_logic_vector (7 downto 0);
signal s_CRC_ok_p_buff, s_arriving_fes : std_logic_vector (15 downto 0); signal s_CRC_ok_p_buff, s_arriving_fes : std_logic_vector (15 downto 0);
signal s_arriving_fes : std_logic_vector (14 downto 0);
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
...@@ -336,7 +336,7 @@ architecture rtl of WF_rx_deserializer is ...@@ -336,7 +336,7 @@ architecture rtl of WF_rx_deserializer is
-- nanoFIP can receive ID_DATs of a predefined length of 8 bytes and RP_DATs of any length -- nanoFIP can receive ID_DATs of a predefined length of 8 bytes and RP_DATs of any length
-- (not predefined) up to 132 bytes (FSD+Ctrl+PDU_TYPE+LGTH+124 pure_data+MPS+FCS+FES). -- (not predefined) up to 132 bytes (FSD+Ctrl+PDU_TYPE+LGTH+124 application_data+MPS+FCS+FES).
-- The WF_engine_control unit is following the amount of bytes being received and in case -- The WF_engine_control unit is following the amount of bytes being received and in case
-- their number overpasses the expected one, it activates the signal rst_rx_unit_p_i. -- their number overpasses the expected one, it activates the signal rst_rx_unit_p_i.
-- Therefore, the Receiver_FSM stays in the data_fcs_fes_fields state until the arrival of a -- Therefore, the Receiver_FSM stays in the data_fcs_fes_fields state until the arrival of a
...@@ -551,17 +551,19 @@ architecture rtl of WF_rx_deserializer is ...@@ -551,17 +551,19 @@ architecture rtl of WF_rx_deserializer is
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nfip_rst_i = '1' then if nfip_rst_i = '1' then
s_arriving_fes <= (others =>'0'); s_arriving_fes <= (others =>'0');
else else
if s_receiving_bytes = '1' and sample_manch_bit_p_i = '1' then if s_receiving_bytes = '0' then
s_arriving_fes <= (others =>'0');
elsif s_receiving_bytes = '1' and sample_manch_bit_p_i = '1' then
s_arriving_fes <= s_arriving_fes (14 downto 0) & rxd_filtered_i; s_arriving_fes <= s_arriving_fes (14 downto 0) & rxd_filtered_i;
end if; end if;
end if; end if;
end if; end if;
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_fes_detected_p <= '1' when s_arriving_fes = (c_FES) and sample_manch_bit_p_i = '1' else '0'; s_fes_detected_p <= '1' when s_arriving_fes = (c_FES);
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -626,7 +628,7 @@ architecture rtl of WF_rx_deserializer is ...@@ -626,7 +628,7 @@ architecture rtl of WF_rx_deserializer is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--!@brief Synchronous process that handles the CRC signal: The crc_ok_p coming from the CRC --!@brief Synchronous process that handles the CRC signal: The crc_ok_p coming from the CRC
--! calculator unit is delayed for 16 manch. encoded bits. The matching of this delayed pulse --! calculator unit is delayed for 15 manch. encoded bits. The matching of this delayed pulse
--! with the end of frame pulse (s_fes_detected_p), would confirm that the two last bytes --! with the end of frame pulse (s_fes_detected_p), would confirm that the two last bytes
--! received before the FES were the correct CRC. --! received before the FES were the correct CRC.
...@@ -656,7 +658,7 @@ architecture rtl of WF_rx_deserializer is ...@@ -656,7 +658,7 @@ architecture rtl of WF_rx_deserializer is
end if; end if;
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_crc_ok_p_d16 <= s_CRC_ok_p_buff(15); -- pulse 1 half-bit-clock period long s_crc_ok_p_d16 <= s_CRC_ok_p_buff(14); -- pulse 1 half-bit-clock period long
......
wf_rx_tx_osc.vhd
View file @ 7da7370b
...@@ -28,26 +28,31 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -28,26 +28,31 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
-- unit name WF_rx_tx_osc -- unit name WF_rx_tx_osc
-- --
--! @brief Generation the clock signals needed for the receiver (WF_rx_deglitcher and --! @brief Generation the clock signals needed for the receiver (WF_rx_deglitcher and
--! WF_rx_deserializer)and transmiter(WF_tx_serializer)\n --! WF_rx_deserializer) and transmiter (WF_tx_serializer)\n
--! --!
--! Concerning the reception, even if the bit rate of the communication is known, jitter --! o Concerning the reception, even if the bit rate of the communication is known,
--! is expected to affect the arriving time of the incoming signal. The main idea of the --! jitter is expected to affect the arriving time of the incoming signal. The main idea
--! unit is to recalculate the expected arrival time of the next incoming bit, based on --! of the unit is to recalculate the expected arrival time of the next incoming bit,
--! the arrival of the previous one, so that drifts are not accumulated. The clock --! based on the arrival of the previous one, so that drifts are not accumulated. The
--! recovery is based on the Manchester 2 coding which ensures that there is one edge --! clock recovery is based on the Manchester 2 coding which ensures that there is one
--! (transition) for each bit. In this unit, we refer to a significant edge for an edge --! edge (transition) for each bit.
--! of a Manchester 2 encoded bit (eg: bit0: _|-, bit 1: -|_) and to a transition between --!
--! adjacent bits for a transition that may or may not give an edge between adjacent --! In this unit, we refer to
--! bits (e.g.: a 0/1 followed by a 0/1 will give an edge _|-|_|-, but a 0/1 followed by --! o a significant edge : for the edge of a manch. encoded bit
--! a 1/0 will not _|--|_ ). --! (bit 0: _|-, bit 1: -|_)
-- --! o a transition : for the moment in between two adjacent bits,
--! Concerning the transmission, the unit generates the nanoFIP output signal tx_clk --! that may or may not result in an edge (eg. a 0 followed by a 0 will give an edge
--! (line driver half bit clock) and the nanoFIP internal signal tx_clk_p_buff: --! _|-|_|-, but a 0 followed by a 1 will not _|--|_ ).
--! tx_clk: ___|--------...--------|________...________|--------...--------|__ --!
--! tx_clk_p_buff (3): |0|0|0|1 |0|0|0|1 --!
--! tx_clk_p_buff (2): |0|0|1|0 |0|0|1|0 --! o Concerning the transmission, the unit generates the nanoFIP FIELDRIVE output
--! tx_clk_p_buff (1): |0|1|0|0 |0|1|0|0 --! FD_TXCK (line driver half bit clock) and the nanoFIP internal signal tx_clk_p_buff:
--! tx_clk_p_buff (0): |1|0|0|0 |1|0|0|0 --!
--! FD_TXCK :___|--------...--------|________...________|--------...--------|__
--! tx_clk_p_buff (3) : |0|0|0|1 |0|0|0|1
--! tx_clk_p_buff (2) : |0|0|1|0 |0|0|1|0
--! tx_clk_p_buff (1) : |0|1|0|0 |0|1|0|0
--! tx_clk_p_buff (0) : |1|0|0|0 |1|0|0|0
--! --!
-- --
-- --
...@@ -74,12 +79,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities ...@@ -74,12 +79,13 @@ use work.WF_PACKAGE.all; --! definitions of types, constants, entities
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! -> 08/2009 v0.01 PS Entity Ports added, start of architecture content \n --! -> 08/2009 v0.01 PS Entity Ports added, start of architecture content \n
--! -> 07/2010 v0.02 EG tx, rx counter changed from 20 bits signed, to 11 bits unsigned; --! -> 07/2010 v0.02 EG tx, rx counter changed from 20 bits signed, to 11 bits unsigned;
--! rx clk generation depends on edge detection; code cleaned-up+commented --! rx clk generation depends on edge detection;code cleanedup+commented
--! c_TX_CLK_BUFF_LGTH got 1 bit more\n --! c_TX_CLK_BUFF_LGTH got 1 bit more\n
--! rst_rx_osc signal clearified --! rst_rx_osc signal clearified
--! -> 12/2010 v0.03 EG code cleaned-up --! -> 12/2010 v0.03 EG code cleaned-up
--! -> 01/2011 v0.031 EG rxd_edge_i became rxd_edge_p_i; small correctiond on comments
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
...@@ -119,7 +125,7 @@ entity WF_rx_tx_osc is ...@@ -119,7 +125,7 @@ entity WF_rx_tx_osc is
nfip_rst_i : in std_logic; --! nanoFIP internal reset nfip_rst_i : in std_logic; --! nanoFIP internal reset
-- Signal from the WF_synchronizer unit -- Signal from the WF_synchronizer unit
rxd_edge_i : in std_logic; --! indication of an edge on fd_rxd rxd_edge_p_i : in std_logic; --! indication of an edge on fd_rxd
-- Signal from WF_rx_deserializer unit -- Signal from WF_rx_deserializer unit
rst_rx_osc_i : in std_logic; --! resets the clock recovery procedure of the rx_osc rst_rx_osc_i : in std_logic; --! resets the clock recovery procedure of the rx_osc
...@@ -129,13 +135,13 @@ entity WF_rx_tx_osc is ...@@ -129,13 +135,13 @@ entity WF_rx_tx_osc is
-- Output signals needed in the reception -- Output signals needed in the reception
-- Signals to the WF_rx_deserializer and the WF_rx_deglitcher -- Signals to the WF_rx_deserializer and the WF_rx_deglitcher
rx_manch_clk_p_o : out std_logic; --! signal with uclk-wide pulses rx_manch_clk_p_o : out std_logic; --! signal with uclk-wide pulses
--! 1) on a significant edge --! o on a significant edge
--! 2) between adjacent bits --! o between adjacent bits
--! ____|-|___|-|___|-|___ --! ____|-|___|-|___|-|___
rx_bit_clk_p_o : out std_logic; --! signal with uclk-wide pulses rx_bit_clk_p_o : out std_logic; --! signal with uclk-wide pulses
--! between adjacent bits --! o between adjacent bits
--! __________|-|_________ --! __________|-|_________
rx_signif_edge_window_o : out std_logic; --! time window where a significant edge is expected rx_signif_edge_window_o : out std_logic; --! time window where a significant edge is expected
...@@ -192,17 +198,16 @@ begin ...@@ -192,17 +198,16 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- rx_osc -- -- rx_osc --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Synchronous process rx_periods_count: --!@brief Synchronous process rx_periods_count : the rx_counter starts counting after a falling
-- the rx_counter starts counting after a falling edge on the fd_rxd (indicated by the signal --! edge on the fd_rxd (indicated by the signal rst_rx_osc_i from the WF_rx_deserializer unit);
-- rst_rx_osc_i from the WF_rx_deserializer unit); this edge should be representing the 1st --! this edge should be representing the 1st Manchester (manch.) encoded bit '1' of the preamble.
-- Manchester (manch.) encoded bit '1' of the preamble. --! Starting from this edge, other falling or rising significant edges, are expected around one
-- Starting from this edge, other falling or rising significant edges, are expected around one --! period later. A time window around the expected arrival time is set and its length is defined
-- period later. A time window around the expected arrival time is set and its length is defined --! as 1/4th of the period (1/8th before and 1/8th after the expected time). When the actual edge
-- as 1/4th of the period (1/8th before and 1/8th after the expected time). When the actual edge --! arrives, the counter is reset.
-- arrives, the counter is reset. --! If that first falling edge of fd_rxd is finally proven not to belong to a valid preambe
-- If that first falling edge of fd_rxd is finally proven not to belong to a valid preambe --! (the state machine of the WF_rx_deserializer unit is checking that and generating the
-- (the state machine of the WF_rx_deserializer unit is checking that and generating the --! rst_rx_osc_i), the counter is reinitialialized.
-- rst_rx_osc_i), the counter is reinitialialized.
rx_periods_count: process (uclk_i) rx_periods_count: process (uclk_i)
begin begin
...@@ -221,7 +226,7 @@ begin ...@@ -221,7 +226,7 @@ begin
-- counter counting -- counter counting
else else
if (s_rxd_signif_edge_window = '1') and (rxd_edge_i = '1') then if (s_rxd_signif_edge_window = '1') and (rxd_edge_p_i = '1') then
s_rx_counter <= (others => '0'); -- when an edge appears inside s_rx_counter <= (others => '0'); -- when an edge appears inside
-- the expected window, the -- the expected window, the
-- counter is reinitialized -- counter is reinitialized
...@@ -239,14 +244,12 @@ begin ...@@ -239,14 +244,12 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignments concerning the receiver: --!@brief Concurrent signal assignments concerning the receiver: creation of the windows where
-- creation of the windows where "significant edges" and "adjacent bits transitions" are expected --! "significant edges" and "adjacent bits transitions" are expected on the input signal.
-- on the input signal. --! o s_rxd_signif_edge_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after
--! the completion of a period, where significant edges are expected.
-- s_rxd_signif_edge_window: extends s_jitter uclk ticks before and s_jitter uclk ticks after the --! o s_rx_adjac_bits_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after
-- completion of a period, where significant edges are expected. --! the middle of a period, where transitions between adjacent bits are expected.
-- s_rx_adjac_bits_window : extends s_jitter uclk ticks before and s_jitter uclk ticks after the
-- middle of a period, where transitions between adjacent bits are expected.
s_rxd_signif_edge_window <= '1' when ((s_rx_counter < s_jitter) or s_rxd_signif_edge_window <= '1' when ((s_rx_counter < s_jitter) or
(s_rx_counter > s_counter_full - s_jitter-1)) (s_rx_counter > s_counter_full - s_jitter-1))
...@@ -259,13 +262,12 @@ begin ...@@ -259,13 +262,12 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Synchronous process rx_clk: --!@brief Synchronous process rx_clks: the process rx_clk is following the edges that appear on the
-- the process rx_clk is following the edges that appear on the input signal fd_rxd and constructs --! nanoFIP FIELDRIVE input fd_rxd and constructs two clock signals: rx_manch_clk & rx_bit_clk.
-- two clock signals: rx_manch_clk and rx_bit_clk.
-- In detail, the process is looking for moments: -- In detail, the process is looking for moments :
-- 1) of significant edges -- o of significant edges
-- 2) between boundary bits -- o between boundary bits
-- the signal rx_manch_clk: is inverted on each significant edge,as well as between adjacent bits -- the signal rx_manch_clk: is inverted on each significant edge,as well as between adjacent bits
-- the signal rx_bit_clk : is inverted only between adjacent bits -- the signal rx_bit_clk : is inverted only between adjacent bits
...@@ -277,11 +279,10 @@ begin ...@@ -277,11 +279,10 @@ begin
-- Edges between adjacent bits are expected inside the adjac_bits_window; if they do not arrive -- Edges between adjacent bits are expected inside the adjac_bits_window; if they do not arrive
-- the rx_manch_clk and rx_bit_clk are inverted right after the end of the adjac_bits_window. -- the rx_manch_clk and rx_bit_clk are inverted right after the end of the adjac_bits_window.
rx_clk: process (uclk_i) rx_clks: process (uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
-- initializations:
if (nfip_rst_i = '1') then if (nfip_rst_i = '1') then
s_rx_manch_clk <='0'; s_rx_manch_clk <='0';
s_rx_bit_clk <='0'; s_rx_bit_clk <='0';
...@@ -296,7 +297,7 @@ begin ...@@ -296,7 +297,7 @@ begin
-- regarding significant edges: -- regarding significant edges:
-- looking for a significant edge inside the corresponding window -- looking for a significant edge inside the corresponding window
if (s_rxd_signif_edge_window = '1') and (rxd_edge_i = '1') then if (s_rxd_signif_edge_window = '1') and (rxd_edge_p_i = '1') then
s_rx_manch_clk <= not s_rx_manch_clk; -- inversion of rx_manch_clk s_rx_manch_clk <= not s_rx_manch_clk; -- inversion of rx_manch_clk
s_signif_edge_found <= '1'; -- indication that the edge was found s_signif_edge_found <= '1'; -- indication that the edge was found
...@@ -315,7 +316,7 @@ begin ...@@ -315,7 +316,7 @@ begin
-- regarding edges between adjacent bits: -- regarding edges between adjacent bits:
-- looking for an edge inside the corresponding window -- looking for an edge inside the corresponding window
elsif (s_rx_adjac_bits_window = '1') and (rxd_edge_i = '1') then elsif (s_rx_adjac_bits_window = '1') and (rxd_edge_p_i = '1') then
s_rx_manch_clk <= not s_rx_manch_clk;-- inversion of rx_manch_clk s_rx_manch_clk <= not s_rx_manch_clk;-- inversion of rx_manch_clk
s_rx_bit_clk <= not s_rx_bit_clk; -- inversion of rx_bit_clk s_rx_bit_clk <= not s_rx_bit_clk; -- inversion of rx_bit_clk
...@@ -354,7 +355,8 @@ begin ...@@ -354,7 +355,8 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- tx_osc -- -- tx_osc --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Synchronous process tx_periods_count: implementation of a counter counting transmission periods. --!@brief Synchronous process tx_periods_count: implementation of a counter counting transmission
--! periods.
tx_periods_count: process (uclk_i) tx_periods_count: process (uclk_i)
begin begin
...@@ -385,10 +387,10 @@ begin ...@@ -385,10 +387,10 @@ begin
end process; end process;
--------------------------------------------------------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignments concerning the transmitter: --!@brief Concurrent signal assignments concerning the transmitter:
-- creation of the clock for the transmitter with period: 1/2 transmission period -- Creation of the clock for the transmitter with period: 1/2 transmission period
s_tx_clk <= '1' when ((s_tx_counter < s_one_forth_period) or s_tx_clk <= '1' when ((s_tx_counter < s_one_forth_period) or
((s_tx_counter > (2*s_one_forth_period)-1) and ((s_tx_counter > (2*s_one_forth_period)-1) and
(s_tx_counter < 3*s_one_forth_period))) (s_tx_counter < 3*s_one_forth_period)))
...@@ -398,7 +400,7 @@ begin ...@@ -398,7 +400,7 @@ begin
-- s_tx_clk : _|----|_____|----|_____|-- -- s_tx_clk : _|----|_____|----|_____|--
-- creation of a pulse starting 1 uclk period before tx_clk_o -- Creation of a pulse starting 1 uclk period before tx_clk_o
s_tx_clk_p <= s_tx_clk and (not s_tx_clk_d1); s_tx_clk_p <= s_tx_clk and (not s_tx_clk_d1);
-- s_tx_clk : __|-----|_____|-----|_____ -- s_tx_clk : __|-----|_____|-----|_____
-- tx_clk_o/ s_tx_clk_d1 : ____|-----|_____|-----|___ -- tx_clk_o/ s_tx_clk_d1 : ____|-----|_____|-----|___
...@@ -412,17 +414,18 @@ begin ...@@ -412,17 +414,18 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Output signals construction: -- Output signals construction:
-- clocks needed for the receiver: -- Clocks needed for the receiver:
rx_manch_clk_p_o <= s_rx_manch_clk_d1 xor s_rx_manch_clk; -- a pulse 1-uclk period long, after rx_manch_clk_p_o <= s_rx_manch_clk_d1 xor s_rx_manch_clk; -- a pulse 1-uclk period long, after
-- 1) a significant edge -- o a significant edge
-- 2) a new bit -- o a new bit
-- ___|-|___|-|___|-|___ -- ___|-|___|-|___|-|___
rx_bit_clk_p_o <= s_rx_bit_clk xor s_rx_bit_clk_d1; -- a pulse 1-uclk period long, after rx_bit_clk_p_o <= s_rx_bit_clk xor s_rx_bit_clk_d1; -- a pulse 1-uclk period long, after
-- a new bit -- o a new bit
-- _________|-|_________ -- _________|-|_________
-- clocks needed for the transmitter:
-- Clocks needed for the transmitter:
tx_clk_o <= s_tx_clk_d1; tx_clk_o <= s_tx_clk_d1;
tx_clk_p_buff_o <= s_tx_clk_p_buff; tx_clk_p_buff_o <= s_tx_clk_p_buff;
......
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